1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 (Add(Ptr|64|32|16|8) ...) => (ADD ...)
6 (Add(32|64)F ...) => (FADD(S|D) ...)
7
8 (Sub(Ptr|64|32|16|8) ...) => (SUB ...)
9 (Sub(32|64)F ...) => (FSUB(S|D) ...)
10
11 (Mul64 ...) => (MUL ...)
12 (Mul(32|16|8) ...) => (MULW ...)
13 (Mul(32|64)F ...) => (FMUL(S|D) ...)
14
15 (Hmul64 ...) => (MULH ...)
16 (Hmul64u ...) => (UMULH ...)
17 (Hmul32 x y) => (SRAconst (MULL <typ.Int64> x y) [32])
18 (Hmul32u x y) => (SRAconst (UMULL <typ.UInt64> x y) [32])
19 (Select0 (Mul64uhilo x y)) => (UMULH x y)
20 (Select1 (Mul64uhilo x y)) => (MUL x y)
21
22 (Div64 [false] x y) => (DIV x y)
23 (Div32 [false] x y) => (DIVW x y)
24 (Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y))
25 (Div16u x y) => (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y))
26 (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y))
27 (Div8u x y) => (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y))
28 (Div64u ...) => (UDIV ...)
29 (Div32u ...) => (UDIVW ...)
30 (Div32F ...) => (FDIVS ...)
31 (Div64F ...) => (FDIVD ...)
32
33 (Mod64 x y) => (MOD x y)
34 (Mod32 x y) => (MODW x y)
35 (Mod64u ...) => (UMOD ...)
36 (Mod32u ...) => (UMODW ...)
37 (Mod(16|8) x y) => (MODW (SignExt(16|8)to32 x) (SignExt(16|8)to32 y))
38 (Mod(16|8)u x y) => (UMODW (ZeroExt(16|8)to32 x) (ZeroExt(16|8)to32 y))
39
40 // (x + y) / 2 with x>=y => (x - y) / 2 + y
41 (Avg64u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y)
42
43 (And(64|32|16|8) ...) => (AND ...)
44 (Or(64|32|16|8) ...) => (OR ...)
45 (Xor(64|32|16|8) ...) => (XOR ...)
46
47 // unary ops
48 (Neg(64|32|16|8) ...) => (NEG ...)
49 (Neg(32|64)F ...) => (FNEG(S|D) ...)
50 (Com(64|32|16|8) ...) => (MVN ...)
51
52 // math package intrinsics
53 (Abs ...) => (FABSD ...)
54 (Sqrt ...) => (FSQRTD ...)
55 (Ceil ...) => (FRINTPD ...)
56 (Floor ...) => (FRINTMD ...)
57 (Round ...) => (FRINTAD ...)
58 (RoundToEven ...) => (FRINTND ...)
59 (Trunc ...) => (FRINTZD ...)
60 (FMA x y z) => (FMADDD z x y)
61
62 (Sqrt32 ...) => (FSQRTS ...)
63
64 (Min(64|32)F ...) => (FMIN(D|S) ...)
65 (Max(64|32)F ...) => (FMAX(D|S) ...)
66
67 // lowering rotates
68 // we do rotate detection in generic rules, if the following rules need to be changed, check generic rules first.
69 (RotateLeft8 <t> x (MOVDconst [c])) => (Or8 (Lsh8x64 <t> x (MOVDconst [c&7])) (Rsh8Ux64 <t> x (MOVDconst [-c&7])))
70 (RotateLeft8 <t> x y) => (OR <t> (SLL <t> x (ANDconst <typ.Int64> [7] y)) (SRL <t> (ZeroExt8to64 x) (ANDconst <typ.Int64> [7] (NEG <typ.Int64> y))))
71 (RotateLeft16 <t> x (MOVDconst [c])) => (Or16 (Lsh16x64 <t> x (MOVDconst [c&15])) (Rsh16Ux64 <t> x (MOVDconst [-c&15])))
72 (RotateLeft16 <t> x y) => (RORW <t> (ORshiftLL <typ.UInt32> (ZeroExt16to32 x) (ZeroExt16to32 x) [16]) (NEG <typ.Int64> y))
73 (RotateLeft32 x y) => (RORW x (NEG <y.Type> y))
74 (RotateLeft64 x y) => (ROR x (NEG <y.Type> y))
75
76 (Ctz(64|32|16|8)NonZero ...) => (Ctz(64|32|32|32) ...)
77
78 (Ctz64 <t> x) => (CLZ (RBIT <t> x))
79 (Ctz32 <t> x) => (CLZW (RBITW <t> x))
80 (Ctz16 <t> x) => (CLZW <t> (RBITW <typ.UInt32> (ORconst <typ.UInt32> [0x10000] x)))
81 (Ctz8 <t> x) => (CLZW <t> (RBITW <typ.UInt32> (ORconst <typ.UInt32> [0x100] x)))
82
83 (PopCount64 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> x))))
84 (PopCount32 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt32to64 x)))))
85 (PopCount16 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt16to64 x)))))
86
87 // Load args directly into the register class where it will be used.
88 (FMOVDgpfp <t> (Arg [off] {sym})) => @b.Func.Entry (Arg <t> [off] {sym})
89 (FMOVDfpgp <t> (Arg [off] {sym})) => @b.Func.Entry (Arg <t> [off] {sym})
90
91 // Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set.
92 (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) => (FMOVDstore [off] {sym} ptr val mem)
93 (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) => (MOVDstore [off] {sym} ptr val mem)
94 (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) => (FMOVSstore [off] {sym} ptr val mem)
95 (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem)
96
97 // float <=> int register moves, with no conversion.
98 // These come up when compiling math.{Float64bits, Float64frombits, Float32bits, Float32frombits}.
99 (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) => (FMOVDfpgp val)
100 (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) => (FMOVDgpfp val)
101 (MOVWUload [off] {sym} ptr (FMOVSstore [off] {sym} ptr val _)) => (FMOVSfpgp val)
102 (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (FMOVSgpfp val)
103
104 (BitLen64 x) => (SUB (MOVDconst [64]) (CLZ <typ.Int> x))
105 (BitLen32 x) => (SUB (MOVDconst [32]) (CLZW <typ.Int> x))
106 (BitLen(16|8) x) => (BitLen64 (ZeroExt(16|8)to64 x))
107
108 (Bswap64 ...) => (REV ...)
109 (Bswap32 ...) => (REVW ...)
110 (Bswap16 ...) => (REV16W ...)
111
112 (BitRev64 ...) => (RBIT ...)
113 (BitRev32 ...) => (RBITW ...)
114 (BitRev16 x) => (SRLconst [48] (RBIT <typ.UInt64> x))
115 (BitRev8 x) => (SRLconst [56] (RBIT <typ.UInt64> x))
116
117 // In fact, UMOD will be translated into UREM instruction, and UREM is originally translated into
118 // UDIV and MSUB instructions. But if there is already an identical UDIV instruction just before or
119 // after UREM (case like quo, rem := z/y, z%y), then the second UDIV instruction becomes redundant.
120 // The purpose of this rule is to have this extra UDIV instruction removed in CSE pass.
121 (UMOD <typ.UInt64> x y) => (MSUB <typ.UInt64> x y (UDIV <typ.UInt64> x y))
122 (UMODW <typ.UInt32> x y) => (MSUBW <typ.UInt32> x y (UDIVW <typ.UInt32> x y))
123
124 // 64-bit addition with carry.
125 (Select0 (Add64carry x y c)) => (Select0 <typ.UInt64> (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] c))))
126 (Select1 (Add64carry x y c)) => (ADCzerocarry <typ.UInt64> (Select1 <types.TypeFlags> (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] c)))))
127
128 // 64-bit subtraction with borrowing.
129 (Select0 (Sub64borrow x y bo)) => (Select0 <typ.UInt64> (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags bo))))
130 (Select1 (Sub64borrow x y bo)) => (NEG <typ.UInt64> (NGCzerocarry <typ.UInt64> (Select1 <types.TypeFlags> (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags bo))))))
131
132 // boolean ops -- booleans are represented with 0=false, 1=true
133 (AndB ...) => (AND ...)
134 (OrB ...) => (OR ...)
135 (EqB x y) => (XOR (MOVDconst [1]) (XOR <typ.Bool> x y))
136 (NeqB ...) => (XOR ...)
137 (Not x) => (XOR (MOVDconst [1]) x)
138
139 // shifts
140 // hardware instruction uses only the low 6 bits of the shift
141 // we compare to 64 to ensure Go semantics for large shifts
142 // Rules about rotates with non-const shift are based on the following rules,
143 // if the following rules change, please also modify the rules based on them.
144
145 // check shiftIsBounded first, if shift value is proved to be valid then we
146 // can do the shift directly.
147 // left shift
148 (Lsh32x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...)
149 (Lsh16x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...)
150 (Lsh8x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...)
151
152 (Lsh64x(64|32|16|8) <t> x y) && ssa.ShiftIsBounded(v) => (SLL <t> x y)
153
154 // signed right shift
155 (Rsh32x(64|32|16|8) <t> [bounded] x y) => (Rsh64x(64|32|16|8) <t> [bounded] (SignExt32to64 x) y)
156 (Rsh16x(64|32|16|8) <t> [bounded] x y) => (Rsh64x(64|32|16|8) <t> [bounded] (SignExt16to64 x) y)
157 (Rsh8x(64|32|16|8) <t> [bounded] x y) => (Rsh64x(64|32|16|8) <t> [bounded] (SignExt8to64 x) y)
158
159 (Rsh64x(64|32|16|8) <t> x y) && ssa.ShiftIsBounded(v) => (SRA <t> x y)
160
161 // unsigned right shift
162 (Rsh32Ux(64|32|16|8) <t> [bounded] x y) => (Rsh64Ux(64|32|16|8) <t> [bounded] (ZeroExt32to64 x) y)
163 (Rsh16Ux(64|32|16|8) <t> [bounded] x y) => (Rsh64Ux(64|32|16|8) <t> [bounded] (ZeroExt16to64 x) y)
164 (Rsh8Ux(64|32|16|8) <t> [bounded] x y) => (Rsh64Ux(64|32|16|8) <t> [bounded] (ZeroExt8to64 x) y)
165
166 (Rsh64Ux(64|32|16|8) <t> x y) && ssa.ShiftIsBounded(v) => (SRL <t> x y)
167
168 // shift value may be out of range, use CMP + CSEL instead
169 (Lsh64x64 <t> x y) && !ssa.ShiftIsBounded(v) => (CSEL [ssaop.OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] y))
170 (Lsh64x32 <t> x y) && !ssa.ShiftIsBounded(v) => (CSEL [ssaop.OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPWconst [64] y))
171 (Lsh64x(16|8) <t> [bounded] x y) && !ssa.ShiftIsBounded(v) => (Lsh64x32 <t> [bounded] x (ZeroExt(16|8)to32 y))
172
173 (Rsh64Ux64 <t> x y) && !ssa.ShiftIsBounded(v) => (CSEL [ssaop.OpARM64LessThanU] (SRL <t> x y) (Const64 <t> [0]) (CMPconst [64] y))
174 (Rsh64Ux32 <t> x y) && !ssa.ShiftIsBounded(v) => (CSEL [ssaop.OpARM64LessThanU] (SRL <t> x y) (Const64 <t> [0]) (CMPWconst [64] y))
175 (Rsh64Ux(16|8) <t> [bounded] x y) && !ssa.ShiftIsBounded(v) => (Rsh64Ux32 <t> [bounded] x (ZeroExt(16|8)to32 y))
176
177 (Rsh64x64 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA x (CSEL [ssaop.OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] y)))
178 (Rsh64x32 <t> x y) && !ssa.ShiftIsBounded(v) => (SRA x (CSEL [ssaop.OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPWconst [64] y)))
179 (Rsh64x(16|8) <t> [bounded] x y) && !ssa.ShiftIsBounded(v) => (Rsh64x32 <t> [bounded] x (ZeroExt(16|8)to32 y))
180
181 // constants
182 (Const(64|32|16|8) [val]) => (MOVDconst [int64(val)])
183 (Const(32|64)F [val]) => (FMOV(S|D)const [float64(val)])
184 (ConstNil) => (MOVDconst [0])
185 (ConstBool [t]) => (MOVDconst [ssa.B2i(t)])
186
187 (Slicemask <t> x) => (SRAconst (NEG <t> x) [63])
188
189 // truncations
190 // Because we ignore high parts of registers, truncates are just copies.
191 (Trunc16to8 ...) => (Copy ...)
192 (Trunc32to8 ...) => (Copy ...)
193 (Trunc32to16 ...) => (Copy ...)
194 (Trunc64to8 ...) => (Copy ...)
195 (Trunc64to16 ...) => (Copy ...)
196 (Trunc64to32 ...) => (Copy ...)
197
198 // Zero-/Sign-extensions
199 (ZeroExt8to16 ...) => (MOVBUreg ...)
200 (ZeroExt8to32 ...) => (MOVBUreg ...)
201 (ZeroExt16to32 ...) => (MOVHUreg ...)
202 (ZeroExt8to64 ...) => (MOVBUreg ...)
203 (ZeroExt16to64 ...) => (MOVHUreg ...)
204 (ZeroExt32to64 ...) => (MOVWUreg ...)
205
206 (SignExt8to16 ...) => (MOVBreg ...)
207 (SignExt8to32 ...) => (MOVBreg ...)
208 (SignExt16to32 ...) => (MOVHreg ...)
209 (SignExt8to64 ...) => (MOVBreg ...)
210 (SignExt16to64 ...) => (MOVHreg ...)
211 (SignExt32to64 ...) => (MOVWreg ...)
212
213 // float <=> int conversion
214 (Cvt32to32F ...) => (SCVTFWS ...)
215 (Cvt32to64F ...) => (SCVTFWD ...)
216 (Cvt64to32F ...) => (SCVTFS ...)
217 (Cvt64to64F ...) => (SCVTFD ...)
218 (Cvt32Uto32F ...) => (UCVTFWS ...)
219 (Cvt32Uto64F ...) => (UCVTFWD ...)
220 (Cvt64Uto32F ...) => (UCVTFS ...)
221 (Cvt64Uto64F ...) => (UCVTFD ...)
222 (Cvt32Fto32 ...) => (FCVTZSSW ...)
223 (Cvt64Fto32 ...) => (FCVTZSDW ...)
224 (Cvt32Fto64 ...) => (FCVTZSS ...)
225 (Cvt64Fto64 ...) => (FCVTZSD ...)
226 (Cvt32Fto32U ...) => (FCVTZUSW ...)
227 (Cvt64Fto32U ...) => (FCVTZUDW ...)
228 (Cvt32Fto64U ...) => (FCVTZUS ...)
229 (Cvt64Fto64U ...) => (FCVTZUD ...)
230 (Cvt32Fto64F ...) => (FCVTSD ...)
231 (Cvt64Fto32F ...) => (FCVTDS ...)
232
233 (CvtBoolToUint8 ...) => (Copy ...)
234
235 (Round32F ...) => (LoweredRound32F ...)
236 (Round64F ...) => (LoweredRound64F ...)
237
238 // comparisons
239 (Eq8 x y) => (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
240 (Eq16 x y) => (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
241 (Eq32 x y) => (Equal (CMPW x y))
242 (Eq64 x y) => (Equal (CMP x y))
243 (EqPtr x y) => (Equal (CMP x y))
244 (Eq32F x y) => (Equal (FCMPS x y))
245 (Eq64F x y) => (Equal (FCMPD x y))
246
247 (Neq8 x y) => (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
248 (Neq16 x y) => (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
249 (Neq32 x y) => (NotEqual (CMPW x y))
250 (Neq64 x y) => (NotEqual (CMP x y))
251 (NeqPtr x y) => (NotEqual (CMP x y))
252 (Neq(32|64)F x y) => (NotEqual (FCMP(S|D) x y))
253
254 (Less(8|16) x y) => (LessThan (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
255 (Less32 x y) => (LessThan (CMPW x y))
256 (Less64 x y) => (LessThan (CMP x y))
257
258 // Set condition flags for floating-point comparisons "x < y"
259 // and "x <= y". Because if either or both of the operands are
260 // NaNs, all three of (x < y), (x == y) and (x > y) are false,
261 // and ARM Manual says FCMP instruction sets PSTATE.<N,Z,C,V>
262 // of this case to (0, 0, 1, 1).
263 (Less32F x y) => (LessThanF (FCMPS x y))
264 (Less64F x y) => (LessThanF (FCMPD x y))
265
266 // For an unsigned integer x, the following rules are useful when combining branch
267 // 0 < x => x != 0
268 // x <= 0 => x == 0
269 // x < 1 => x == 0
270 // 1 <= x => x != 0
271 (Less(8U|16U|32U|64U) zero:(MOVDconst [0]) x) => (Neq(8|16|32|64) zero x)
272 (Leq(8U|16U|32U|64U) x zero:(MOVDconst [0])) => (Eq(8|16|32|64) x zero)
273 (Less(8U|16U|32U|64U) x (MOVDconst [1])) => (Eq(8|16|32|64) x (MOVDconst [0]))
274 (Leq(8U|16U|32U|64U) (MOVDconst [1]) x) => (Neq(8|16|32|64) (MOVDconst [0]) x)
275
276 (Less8U x y) => (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
277 (Less16U x y) => (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
278 (Less32U x y) => (LessThanU (CMPW x y))
279 (Less64U x y) => (LessThanU (CMP x y))
280
281 (Leq8 x y) => (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y)))
282 (Leq16 x y) => (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y)))
283 (Leq32 x y) => (LessEqual (CMPW x y))
284 (Leq64 x y) => (LessEqual (CMP x y))
285
286 // Refer to the comments for op Less64F above.
287 (Leq32F x y) => (LessEqualF (FCMPS x y))
288 (Leq64F x y) => (LessEqualF (FCMPD x y))
289
290 (Leq8U x y) => (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
291 (Leq16U x y) => (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
292 (Leq32U x y) => (LessEqualU (CMPW x y))
293 (Leq64U x y) => (LessEqualU (CMP x y))
294
295 // Optimize comparison between a floating-point value and 0.0 with "FCMP $(0.0), Fn"
296 (FCMPS x (FMOVSconst [0])) => (FCMPS0 x)
297 (FCMPS (FMOVSconst [0]) x) => (InvertFlags (FCMPS0 x))
298 (FCMPD x (FMOVDconst [0])) => (FCMPD0 x)
299 (FCMPD (FMOVDconst [0]) x) => (InvertFlags (FCMPD0 x))
300
301 // Float min/max comparison-select idioms lower to a compare plus FCSEL on the
302 // FP registers. The ops carry their semantics directly, so lowering always
303 // triggers.
304 (Min64FSel x y) => (FCSELD [ssaop.OpARM64LessThanF] x y (FCMPD x y))
305 (Min32FSel x y) => (FCSELS [ssaop.OpARM64LessThanF] x y (FCMPS x y))
306 (Max64FSel x y) => (FCSELD [ssaop.OpARM64GreaterThanF] x y (FCMPD x y))
307 (Max32FSel x y) => (FCSELS [ssaop.OpARM64GreaterThanF] x y (FCMPS x y))
308
309 // CSEL needs a flag-generating argument. Synthesize a TSTW if necessary.
310 (CondSelect x y boolval) && ssa.FlagArg(boolval) != nil => (CSEL [boolval.Op] x y ssa.FlagArg(boolval))
311 (CondSelect x y boolval) && ssa.FlagArg(boolval) == nil => (CSEL [ssaop.OpARM64NotEqual] x y (TSTWconst [1] boolval))
312
313 (OffPtr [off] ptr:(SP)) && ssa.Is32Bit(off) => (MOVDaddr [int32(off)] ptr)
314 (OffPtr [off] ptr) => (ADDconst [off] ptr)
315
316 (Addr {sym} base) => (MOVDaddr {sym} base)
317 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVDaddr {sym} (SPanchored base mem))
318 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVDaddr {sym} base)
319
320 // loads
321 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
322 (Load <t> ptr mem) && (ssa.Is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
323 (Load <t> ptr mem) && (ssa.Is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
324 (Load <t> ptr mem) && (ssa.Is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
325 (Load <t> ptr mem) && (ssa.Is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
326 (Load <t> ptr mem) && (ssa.Is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
327 (Load <t> ptr mem) && (ssa.Is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
328 (Load <t> ptr mem) && (ssa.Is64BitInt(t) ||ssa.IsPtr(t)) => (MOVDload ptr mem)
329 (Load <t> ptr mem) && ssa.Is32BitFloat(t) => (FMOVSload ptr mem)
330 (Load <t> ptr mem) && ssa.Is64BitFloat(t) => (FMOVDload ptr mem)
331 (Load <t> ptr mem) && t.Size() == 16 => (FMOVQload ptr mem)
332
333 // stores
334 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
335 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
336 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
337 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() && !t.IsSIMD() => (MOVDstore ptr val mem)
338 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
339 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
340 (Store {t} ptr val mem) && t.Size() == 16 => (FMOVQstore ptr val mem)
341
342 // zeroing
343 (Zero [0] _ mem) => mem
344 (Zero [1] ptr mem) => (MOVBstore ptr (MOVDconst [0]) mem)
345 (Zero [2] ptr mem) => (MOVHstore ptr (MOVDconst [0]) mem)
346 (Zero [4] ptr mem) => (MOVWstore ptr (MOVDconst [0]) mem)
347 (Zero [3] ptr mem) =>
348 (MOVBstore [2] ptr (MOVDconst [0])
349 (MOVHstore ptr (MOVDconst [0]) mem))
350 (Zero [5] ptr mem) =>
351 (MOVBstore [4] ptr (MOVDconst [0])
352 (MOVWstore ptr (MOVDconst [0]) mem))
353 (Zero [6] ptr mem) =>
354 (MOVHstore [4] ptr (MOVDconst [0])
355 (MOVWstore ptr (MOVDconst [0]) mem))
356 (Zero [7] ptr mem) =>
357 (MOVWstore [3] ptr (MOVDconst [0])
358 (MOVWstore ptr (MOVDconst [0]) mem))
359 (Zero [8] ptr mem) => (MOVDstore ptr (MOVDconst [0]) mem)
360 (Zero [9] ptr mem) =>
361 (MOVBstore [8] ptr (MOVDconst [0])
362 (MOVDstore ptr (MOVDconst [0]) mem))
363 (Zero [10] ptr mem) =>
364 (MOVHstore [8] ptr (MOVDconst [0])
365 (MOVDstore ptr (MOVDconst [0]) mem))
366 (Zero [11] ptr mem) =>
367 (MOVDstore [3] ptr (MOVDconst [0])
368 (MOVDstore ptr (MOVDconst [0]) mem))
369 (Zero [12] ptr mem) =>
370 (MOVWstore [8] ptr (MOVDconst [0])
371 (MOVDstore ptr (MOVDconst [0]) mem))
372 (Zero [13] ptr mem) =>
373 (MOVDstore [5] ptr (MOVDconst [0])
374 (MOVDstore ptr (MOVDconst [0]) mem))
375 (Zero [14] ptr mem) =>
376 (MOVDstore [6] ptr (MOVDconst [0])
377 (MOVDstore ptr (MOVDconst [0]) mem))
378 (Zero [15] ptr mem) =>
379 (MOVDstore [7] ptr (MOVDconst [0])
380 (MOVDstore ptr (MOVDconst [0]) mem))
381 (Zero [16] ptr mem) =>
382 (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)
383
384 (Zero [s] ptr mem) && s > 16 && s < 192 => (LoweredZero [s] ptr mem)
385 (Zero [s] ptr mem) && s >= 192 => (LoweredZeroLoop [s] ptr mem)
386
387 // moves
388 (Move [0] _ _ mem) => mem
389 (Move [1] dst src mem) => (MOVBstore dst (MOVBUload src mem) mem)
390 (Move [2] dst src mem) => (MOVHstore dst (MOVHUload src mem) mem)
391 (Move [3] dst src mem) =>
392 (MOVBstore [2] dst (MOVBUload [2] src mem)
393 (MOVHstore dst (MOVHUload src mem) mem))
394 (Move [4] dst src mem) => (MOVWstore dst (MOVWUload src mem) mem)
395 (Move [5] dst src mem) =>
396 (MOVBstore [4] dst (MOVBUload [4] src mem)
397 (MOVWstore dst (MOVWUload src mem) mem))
398 (Move [6] dst src mem) =>
399 (MOVHstore [4] dst (MOVHUload [4] src mem)
400 (MOVWstore dst (MOVWUload src mem) mem))
401 (Move [7] dst src mem) =>
402 (MOVWstore [3] dst (MOVWUload [3] src mem)
403 (MOVWstore dst (MOVWUload src mem) mem))
404 (Move [8] dst src mem) => (MOVDstore dst (MOVDload src mem) mem)
405 (Move [9] dst src mem) =>
406 (MOVBstore [8] dst (MOVBUload [8] src mem)
407 (MOVDstore dst (MOVDload src mem) mem))
408 (Move [10] dst src mem) =>
409 (MOVHstore [8] dst (MOVHUload [8] src mem)
410 (MOVDstore dst (MOVDload src mem) mem))
411 (Move [11] dst src mem) =>
412 (MOVDstore [3] dst (MOVDload [3] src mem)
413 (MOVDstore dst (MOVDload src mem) mem))
414 (Move [12] dst src mem) =>
415 (MOVWstore [8] dst (MOVWUload [8] src mem)
416 (MOVDstore dst (MOVDload src mem) mem))
417 (Move [13] dst src mem) =>
418 (MOVDstore [5] dst (MOVDload [5] src mem)
419 (MOVDstore dst (MOVDload src mem) mem))
420 (Move [14] dst src mem) =>
421 (MOVDstore [6] dst (MOVDload [6] src mem)
422 (MOVDstore dst (MOVDload src mem) mem))
423 (Move [15] dst src mem) =>
424 (MOVDstore [7] dst (MOVDload [7] src mem)
425 (MOVDstore dst (MOVDload src mem) mem))
426 (Move [16] dst src mem) => (FMOVQstore dst (FMOVQload src mem) mem)
427
428 (Move [s] dst src mem) && s > 16 && s <= 24 =>
429 (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem)
430 (FMOVQstore dst (FMOVQload src mem) mem))
431 (Move [s] dst src mem) && s > 24 && s < 32 =>
432 (FMOVQstore [int32(s-16)] dst (FMOVQload [int32(s-16)] src mem)
433 (FMOVQstore dst (FMOVQload src mem) mem))
434 (Move [32] dst src mem) =>
435 (FSTPQ dst (Select0 <typ.Vec128> (FLDPQ src mem)) (Select1 <typ.Vec128> (FLDPQ src mem)) mem)
436 (Move [s] dst src mem) && s > 32 && s <= 40 =>
437 (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem)
438 (FSTPQ dst (Select0 <typ.Vec128> (FLDPQ src mem)) (Select1 <typ.Vec128> (FLDPQ src mem)) mem))
439 (Move [s] dst src mem) && s > 40 && s <= 48 =>
440 (FMOVQstore [int32(s-16)] dst (FMOVQload [int32(s-16)] src mem)
441 (FSTPQ dst (Select0 <typ.Vec128> (FLDPQ src mem)) (Select1 <typ.Vec128> (FLDPQ src mem)) mem))
442 (Move [s] dst src mem) && s > 48 && s <= 64 =>
443 (FSTPQ [int32(s-32)] dst (Select0 <typ.Vec128> (FLDPQ [int32(s-32)] src mem)) (Select1 <typ.Vec128> (FLDPQ [int32(s-32)] src mem))
444 (FSTPQ dst (Select0 <typ.Vec128> (FLDPQ src mem)) (Select1 <typ.Vec128> (FLDPQ src mem)) mem))
445
446 (Move [s] dst src mem) && s > 64 && s < 192 && ssa.LogLargeCopyValue(v, s) => (LoweredMove [s] dst src mem)
447 (Move [s] dst src mem) && s >= 192 && ssa.LogLargeCopyValue(v, s) => (LoweredMoveLoop [s] dst src mem)
448
449 // calls
450 (StaticCall ...) => (CALLstatic ...)
451 (ClosureCall ...) => (CALLclosure ...)
452 (InterCall ...) => (CALLinter ...)
453 (TailCall ...) => (CALLtail ...)
454 (TailCallInter ...) => (CALLtailinter ...)
455
456 // checks
457 (NilCheck ...) => (LoweredNilCheck ...)
458 (IsNonNil ptr) => (NotEqual (CMPconst [0] ptr))
459 (IsInBounds idx len) => (LessThanU (CMP idx len))
460 (IsSliceInBounds idx len) => (LessEqualU (CMP idx len))
461
462 // pseudo-ops
463 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
464 (GetCallerSP ...) => (LoweredGetCallerSP ...)
465 (GetCallerPC ...) => (LoweredGetCallerPC ...)
466 (MemEq ...) => (LoweredMemEq ...)
467
468 // Absorb pseudo-ops into blocks.
469 (If (Equal cc) yes no) => (EQ cc yes no)
470 (If (NotEqual cc) yes no) => (NE cc yes no)
471 (If (LessThan cc) yes no) => (LT cc yes no)
472 (If (LessThanU cc) yes no) => (ULT cc yes no)
473 (If (LessEqual cc) yes no) => (LE cc yes no)
474 (If (LessEqualU cc) yes no) => (ULE cc yes no)
475 (If (GreaterThan cc) yes no) => (GT cc yes no)
476 (If (GreaterThanU cc) yes no) => (UGT cc yes no)
477 (If (GreaterEqual cc) yes no) => (GE cc yes no)
478 (If (GreaterEqualU cc) yes no) => (UGE cc yes no)
479 (If (LessThanF cc) yes no) => (FLT cc yes no)
480 (If (LessEqualF cc) yes no) => (FLE cc yes no)
481 (If (GreaterThanF cc) yes no) => (FGT cc yes no)
482 (If (GreaterEqualF cc) yes no) => (FGE cc yes no)
483
484 (If cond yes no) => (TBNZ [0] cond yes no)
485
486 (JumpTable idx) => (JUMPTABLE {ssa.MakeJumpTableSym(b)} idx (MOVDaddr <typ.Uintptr> {ssa.MakeJumpTableSym(b)} (SB)))
487
488 // atomic intrinsics
489 // Note: these ops do not accept offset.
490 (AtomicLoad8 ...) => (LDARB ...)
491 (AtomicLoad32 ...) => (LDARW ...)
492 (AtomicLoad64 ...) => (LDAR ...)
493 (AtomicLoadPtr ...) => (LDAR ...)
494
495 (AtomicStore8 ...) => (STLRB ...)
496 (AtomicStore32 ...) => (STLRW ...)
497 (AtomicStore64 ...) => (STLR ...)
498 (AtomicStorePtrNoWB ...) => (STLR ...)
499
500 (AtomicExchange(8|32|64) ...) => (LoweredAtomicExchange(8|32|64) ...)
501 (AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
502 (AtomicCompareAndSwap(32|64) ...) => (LoweredAtomicCas(32|64) ...)
503
504 (AtomicAdd(32|64)Variant ...) => (LoweredAtomicAdd(32|64)Variant ...)
505 (AtomicExchange(8|32|64)Variant ...) => (LoweredAtomicExchange(8|32|64)Variant ...)
506 (AtomicCompareAndSwap(32|64)Variant ...) => (LoweredAtomicCas(32|64)Variant ...)
507
508 // Return old contents.
509 (AtomicAnd(64|32|8)value ...) => (LoweredAtomicAnd(64|32|8) ...)
510 (AtomicOr(64|32|8)value ...) => (LoweredAtomicOr(64|32|8) ...)
511 (AtomicAnd(64|32|8)valueVariant ...) => (LoweredAtomicAnd(64|32|8)Variant ...)
512 (AtomicOr(64|32|8)valueVariant ...) => (LoweredAtomicOr(64|32|8)Variant ...)
513
514 // Write barrier.
515 (WB ...) => (LoweredWB ...)
516
517 // Publication barrier (0xe is ST option)
518 (PubBarrier mem) => (DMB [0xe] mem)
519
520 (PanicBounds ...) => (LoweredPanicBoundsRR ...)
521 (LoweredPanicBoundsRR [kind] x (MOVDconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {ssa.PanicBoundsC{C:c}} mem)
522 (LoweredPanicBoundsRR [kind] (MOVDconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {ssa.PanicBoundsC{C:c}} y mem)
523 (LoweredPanicBoundsRC [kind] {p} (MOVDconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:c, Cy:p.C}} mem)
524 (LoweredPanicBoundsCR [kind] {p} (MOVDconst [c]) mem) => (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:p.C, Cy:c}} mem)
525
526 // Optimizations
527
528 // Replace widen -> wide_unop -> narrow with narrow_unop when one exists.
529 (FCVTDS (F(ABS|SQRT|RINTP|RINTM|RINTA|RINTN|RINTZ)D (FCVTSD x))) =>
530 (F(ABS|SQRT|RINTP|RINTM|RINTA|RINTN|RINTZ)S x)
531
532
533 // Absorb boolean tests into block
534 (NZ (Equal cc) yes no) => (EQ cc yes no)
535 (NZ (NotEqual cc) yes no) => (NE cc yes no)
536 (NZ (LessThan cc) yes no) => (LT cc yes no)
537 (NZ (LessThanU cc) yes no) => (ULT cc yes no)
538 (NZ (LessEqual cc) yes no) => (LE cc yes no)
539 (NZ (LessEqualU cc) yes no) => (ULE cc yes no)
540 (NZ (GreaterThan cc) yes no) => (GT cc yes no)
541 (NZ (GreaterThanU cc) yes no) => (UGT cc yes no)
542 (NZ (GreaterEqual cc) yes no) => (GE cc yes no)
543 (NZ (GreaterEqualU cc) yes no) => (UGE cc yes no)
544 (NZ (LessThanF cc) yes no) => (FLT cc yes no)
545 (NZ (LessEqualF cc) yes no) => (FLE cc yes no)
546 (NZ (GreaterThanF cc) yes no) => (FGT cc yes no)
547 (NZ (GreaterEqualF cc) yes no) => (FGE cc yes no)
548
549 (TBNZ [0] (Equal cc) yes no) => (EQ cc yes no)
550 (TBNZ [0] (NotEqual cc) yes no) => (NE cc yes no)
551 (TBNZ [0] (LessThan cc) yes no) => (LT cc yes no)
552 (TBNZ [0] (LessThanU cc) yes no) => (ULT cc yes no)
553 (TBNZ [0] (LessEqual cc) yes no) => (LE cc yes no)
554 (TBNZ [0] (LessEqualU cc) yes no) => (ULE cc yes no)
555 (TBNZ [0] (GreaterThan cc) yes no) => (GT cc yes no)
556 (TBNZ [0] (GreaterThanU cc) yes no) => (UGT cc yes no)
557 (TBNZ [0] (GreaterEqual cc) yes no) => (GE cc yes no)
558 (TBNZ [0] (GreaterEqualU cc) yes no) => (UGE cc yes no)
559 (TBNZ [0] (LessThanF cc) yes no) => (FLT cc yes no)
560 (TBNZ [0] (LessEqualF cc) yes no) => (FLE cc yes no)
561 (TBNZ [0] (GreaterThanF cc) yes no) => (FGT cc yes no)
562 (TBNZ [0] (GreaterEqualF cc) yes no) => (FGE cc yes no)
563
564 (TB(Z|NZ) [0] (XORconst [1] x) yes no) => (TB(NZ|Z) [0] x yes no)
565
566 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TST x y) yes no)
567 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] x:(ANDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTconst [c] y) yes no)
568 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTW x y) yes no)
569 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] x:(ANDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTWconst [int32(c)] y) yes no)
570
571 // For conditional instructions such as CSET, CSEL.
572 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPconst [0] z:(AND x y))) && z.Uses == 1 =>
573 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TST x y))
574 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPWconst [0] x:(ANDconst [c] y))) && x.Uses == 1 =>
575 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTWconst [int32(c)] y))
576 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPWconst [0] z:(AND x y))) && z.Uses == 1 =>
577 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTW x y))
578 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPconst [0] x:(ANDconst [c] y))) && x.Uses == 1 =>
579 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTconst [c] y))
580
581 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] x:(ADDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNconst [c] y) yes no)
582 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] x:(ADDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNWconst [int32(c)] y) yes no)
583 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(ADD x y)) yes no) && z.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMN x y) yes no)
584 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(ADD x y)) yes no) && z.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNW x y) yes no)
585
586 // CMP(x,-y) -> CMN(x,y) is only valid for unordered comparison, if y can be -1<<63
587 ((EQ|NE) (CMP x z:(NEG y)) yes no) && z.Uses == 1 => ((EQ|NE) (CMN x y) yes no)
588 ((Equal|NotEqual) (CMP x z:(NEG y))) && z.Uses == 1 => ((Equal|NotEqual) (CMN x y))
589
590 // CMPW(x,-y) -> CMNW(x,y) is only valid for unordered comparison, if y can be -1<<31
591 ((EQ|NE) (CMPW x z:(NEG y)) yes no) && z.Uses == 1 => ((EQ|NE) (CMNW x y) yes no)
592 ((Equal|NotEqual) (CMPW x z:(NEG y))) && z.Uses == 1 => ((Equal|NotEqual) (CMNW x y))
593
594 // For conditional instructions such as CSET, CSEL.
595 // TODO: add support for LE, GT, overflow needs to be considered.
596 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] x:(ADDconst [c] y))) && x.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNconst [c] y))
597 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] x:(ADDconst [c] y))) && x.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNWconst [int32(c)] y))
598 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] z:(ADD x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMN x y))
599 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] z:(ADD x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNW x y))
600 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] z:(MADD a x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMN a (MUL <x.Type> x y)))
601 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] z:(MADDW a x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNW a (MULW <x.Type> x y)))
602
603 // Skip LessThan/GreaterEqual in the following rewrites.
604 // MSUB[W] a x y is a-x*y, which folds to a CMP.
605 // That can end up being reversed into InvertFlags.
606 // But absorbing InvertFlags into a no-overflow comparison flips < and >,
607 // which is wrong when the difference is the minimum int.
608 ((Equal|NotEqual) (CMPconst [0] z:(MSUB a x y))) && z.Uses == 1 => ((Equal|NotEqual) (CMP a (MUL <x.Type> x y)))
609 ((Equal|NotEqual) (CMPWconst [0] z:(MSUBW a x y))) && z.Uses == 1 => ((Equal|NotEqual) (CMPW a (MULW <x.Type> x y)))
610
611 ((CMPconst|CMNconst) [c] y) && c < 0 && c != -1<<63 => ((CMNconst|CMPconst) [-c] y)
612 ((CMPWconst|CMNWconst) [c] y) && c < 0 && c != -1<<31 => ((CMNWconst|CMPWconst) [-c] y)
613
614 ((EQ|NE) (CMPconst [0] x) yes no) => ((Z|NZ) x yes no)
615 ((EQ|NE) (CMPWconst [0] x) yes no) => ((ZW|NZW) x yes no)
616
617 ((ULE|UGT) (CMPconst [0] x)) => ((EQ|NE) (CMPconst [0] x))
618 ((ULE|UGT) (CMPWconst [0] x)) => ((EQ|NE) (CMPWconst [0] x))
619
620 ((Z|NZ) sub:(SUB x y)) && sub.Uses == 1 => ((EQ|NE) (CMP x y))
621 ((ZW|NZW) sub:(SUB x y)) && sub.Uses == 1 => ((EQ|NE) (CMPW x y))
622 ((Z|NZ) sub:(SUBconst [c] y)) && sub.Uses == 1 => ((EQ|NE) (CMPconst [c] y))
623 ((ZW|NZW) sub:(SUBconst [c] y)) && sub.Uses == 1 => ((EQ|NE) (CMPWconst [int32(c)] y))
624
625 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(MADD a x y)) yes no) && z.Uses==1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMN a (MUL <x.Type> x y)) yes no)
626 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(MADDW a x y)) yes no) && z.Uses==1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNW a (MULW <x.Type> x y)) yes no)
627 // No ordering ops here; see comments above about MSUB[W].
628 ((EQ|NE) (CMPconst [0] z:(MSUB a x y)) yes no) && z.Uses==1 => ((EQ|NE) (CMP a (MUL <x.Type> x y)) yes no)
629 ((EQ|NE) (CMPWconst [0] z:(MSUBW a x y)) yes no) && z.Uses==1 => ((EQ|NE) (CMPW a (MULW <x.Type> x y)) yes no)
630
631 // Absorb bit-tests into block
632 (Z (ANDconst [c] x) yes no) && ssa.OneBit(c) => (TBZ [int64(ssa.Ntz64(c))] x yes no)
633 (NZ (ANDconst [c] x) yes no) && ssa.OneBit(c) => (TBNZ [int64(ssa.Ntz64(c))] x yes no)
634 (ZW (ANDconst [c] x) yes no) && ssa.OneBit(int64(uint32(c))) => (TBZ [int64(ssa.Ntz64(int64(uint32(c))))] x yes no)
635 (NZW (ANDconst [c] x) yes no) && ssa.OneBit(int64(uint32(c))) => (TBNZ [int64(ssa.Ntz64(int64(uint32(c))))] x yes no)
636 (EQ (TSTconst [c] x) yes no) && ssa.OneBit(c) => (TBZ [int64(ssa.Ntz64(c))] x yes no)
637 (NE (TSTconst [c] x) yes no) && ssa.OneBit(c) => (TBNZ [int64(ssa.Ntz64(c))] x yes no)
638 (EQ (TSTWconst [c] x) yes no) && ssa.OneBit(int64(uint32(c))) => (TBZ [int64(ssa.Ntz64(int64(uint32(c))))] x yes no)
639 (NE (TSTWconst [c] x) yes no) && ssa.OneBit(int64(uint32(c))) => (TBNZ [int64(ssa.Ntz64(int64(uint32(c))))] x yes no)
640
641 ((Z|NZ) s:(SRLconst [63] x) yes no) && s.Uses == 1 => (TB(Z|NZ) [63] x yes no)
642 ((Z|NZ) s:(SRAconst [63] x) yes no) && s.Uses == 1 => (TB(Z|NZ) [63] x yes no)
643
644 // Merge more operations into TBZ & TBNZ
645 (TB(Z|NZ) [t] sv:(SRLconst [s] x) yes no) && t+s < 64 && sv.Uses == 1 => (TB(Z|NZ) [t+s] x yes no )
646 (TBZ [t] (SRLconst [s] x) yes no) && t+s >= 64 => (First yes no )
647 (TBNZ [t] (SRLconst [s] x) yes no) && t+s >= 64 => (First no yes)
648
649 (TB(Z|NZ) [t] sv:(SLLconst [s] x) yes no) && t-s >= 0 && sv.Uses == 1 => (TB(Z|NZ) [t-s] x yes no )
650 (TBZ [t] (SLLconst [s] x) yes no) && t-s < 0 => (First yes no )
651 (TBNZ [t] (SLLconst [s] x) yes no) && t-s < 0 => (First no yes)
652
653 (TB(Z|NZ) [t] rv:(RORconst [r] x) yes no) && rv.Uses == 1 => (TB(Z|NZ) [int64(uint64(t+r)%64)] x yes no)
654
655 (TB(Z|NZ) [t] sv:(SRAconst [s] x) yes no) && t+s < 64 && sv.Uses == 1 => (TB(Z|NZ) [t+s] x yes no)
656 (TB(Z|NZ) [t] sv:(SRAconst [s] x) yes no) && t+s >= 64 && sv.Uses == 1 => (TB(Z|NZ) [63 ] x yes no)
657
658 // Test sign-bit for signed comparisons against zero
659 (GE (CMPWconst [0] x) yes no) => (TBZ [31] x yes no)
660 (GE (CMPconst [0] x) yes no) => (TBZ [63] x yes no)
661 (LT (CMPWconst [0] x) yes no) => (TBNZ [31] x yes no)
662 (LT (CMPconst [0] x) yes no) => (TBNZ [63] x yes no)
663
664 // A byte value (a zero-extended-byte op, so provably in [0,255]) compared
665 // against 128 (=2^7) is a bit-7 test, for both compare widths and both
666 // signednesses: with the value in [0,255] the signed and unsigned orderings
667 // against 128 coincide.
668 ((UGE|ULT) (CMPWconst [128] x) yes no) && ssa.ZeroUpper56Bits(x) => ((TBNZ|TBZ) [7] x yes no)
669 ((UGE|ULT) (CMPconst [128] x) yes no) && ssa.ZeroUpper56Bits(x) => ((TBNZ|TBZ) [7] x yes no)
670 ((GE|LT) (CMPWconst [128] x) yes no) && ssa.ZeroUpper56Bits(x) => ((TBNZ|TBZ) [7] x yes no)
671 ((GE|LT) (CMPconst [128] x) yes no) && ssa.ZeroUpper56Bits(x) => ((TBNZ|TBZ) [7] x yes no)
672
673 // fold offset into address
674 (ADDconst [off1] (MOVDaddr [off2] {sym} ptr)) && ssa.Is32Bit(off1+int64(off2)) =>
675 (MOVDaddr [int32(off1)+off2] {sym} ptr)
676
677 // fold address into load/store.
678 // Do not fold global variable access in -dynlink mode, where it will
679 // be rewritten to use the GOT via REGTMP, which currently cannot handle
680 // large offset.
681 (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
682 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
683 (MOVBload [off1+int32(off2)] {sym} ptr mem)
684 (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
685 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
686 (MOVBUload [off1+int32(off2)] {sym} ptr mem)
687 (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
688 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
689 (MOVHload [off1+int32(off2)] {sym} ptr mem)
690 (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
691 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
692 (MOVHUload [off1+int32(off2)] {sym} ptr mem)
693 (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
694 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
695 (MOVWload [off1+int32(off2)] {sym} ptr mem)
696 (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
697 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
698 (MOVWUload [off1+int32(off2)] {sym} ptr mem)
699 (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
700 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
701 (MOVDload [off1+int32(off2)] {sym} ptr mem)
702 (LDP [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
703 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
704 (LDP [off1+int32(off2)] {sym} ptr mem)
705 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
706 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
707 (FMOVSload [off1+int32(off2)] {sym} ptr mem)
708 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
709 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
710 (FMOVDload [off1+int32(off2)] {sym} ptr mem)
711 (FMOVQload [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
712 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
713 (FMOVQload [off1+int32(off2)] {sym} ptr mem)
714 (FLDPQ [off1] {sym} (ADDconst [off2] ptr) mem) && ssa.Is32Bit(int64(off1)+off2)
715 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
716 (FLDPQ [off1+int32(off2)] {sym} ptr mem)
717
718 // register indexed load
719 (MOVDload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr idx mem)
720 (MOVWUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem)
721 (MOVWload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr idx mem)
722 (MOVHUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr idx mem)
723 (MOVHload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr idx mem)
724 (MOVBUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr idx mem)
725 (MOVBload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr idx mem)
726 (FMOVSload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (FMOVSloadidx ptr idx mem)
727 (FMOVDload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (FMOVDloadidx ptr idx mem)
728
729 (MOVDloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (MOVDload [int32(c)] ptr mem)
730 (MOVDloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (MOVDload [int32(c)] ptr mem)
731 (MOVWUloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (MOVWUload [int32(c)] ptr mem)
732 (MOVWUloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (MOVWUload [int32(c)] ptr mem)
733 (MOVWloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (MOVWload [int32(c)] ptr mem)
734 (MOVWloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (MOVWload [int32(c)] ptr mem)
735 (MOVHUloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (MOVHUload [int32(c)] ptr mem)
736 (MOVHUloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (MOVHUload [int32(c)] ptr mem)
737 (MOVHloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (MOVHload [int32(c)] ptr mem)
738 (MOVHloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (MOVHload [int32(c)] ptr mem)
739 (MOVBUloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (MOVBUload [int32(c)] ptr mem)
740 (MOVBUloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (MOVBUload [int32(c)] ptr mem)
741 (MOVBloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (MOVBload [int32(c)] ptr mem)
742 (MOVBloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (MOVBload [int32(c)] ptr mem)
743 (FMOVSloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (FMOVSload [int32(c)] ptr mem)
744 (FMOVSloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (FMOVSload [int32(c)] ptr mem)
745 (FMOVDloadidx ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c) => (FMOVDload [int32(c)] ptr mem)
746 (FMOVDloadidx (MOVDconst [c]) ptr mem) && ssa.Is32Bit(c) => (FMOVDload [int32(c)] ptr mem)
747
748 // shifted register indexed load
749 (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx8 ptr idx mem)
750 (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx4 ptr idx mem)
751 (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx4 ptr idx mem)
752 (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx2 ptr idx mem)
753 (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx2 ptr idx mem)
754 (MOVDloadidx ptr (SLLconst [3] idx) mem) => (MOVDloadidx8 ptr idx mem)
755 (MOVWloadidx ptr (SLLconst [2] idx) mem) => (MOVWloadidx4 ptr idx mem)
756 (MOVWUloadidx ptr (SLLconst [2] idx) mem) => (MOVWUloadidx4 ptr idx mem)
757 (MOVHloadidx ptr (SLLconst [1] idx) mem) => (MOVHloadidx2 ptr idx mem)
758 (MOVHUloadidx ptr (SLLconst [1] idx) mem) => (MOVHUloadidx2 ptr idx mem)
759 (MOVHloadidx ptr (ADD idx idx) mem) => (MOVHloadidx2 ptr idx mem)
760 (MOVHUloadidx ptr (ADD idx idx) mem) => (MOVHUloadidx2 ptr idx mem)
761 (MOVDloadidx (SLLconst [3] idx) ptr mem) => (MOVDloadidx8 ptr idx mem)
762 (MOVWloadidx (SLLconst [2] idx) ptr mem) => (MOVWloadidx4 ptr idx mem)
763 (MOVWUloadidx (SLLconst [2] idx) ptr mem) => (MOVWUloadidx4 ptr idx mem)
764 (MOVHloadidx (ADD idx idx) ptr mem) => (MOVHloadidx2 ptr idx mem)
765 (MOVHUloadidx (ADD idx idx) ptr mem) => (MOVHUloadidx2 ptr idx mem)
766 (MOVDloadidx8 ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c<<3) => (MOVDload [int32(c)<<3] ptr mem)
767 (MOVWUloadidx4 ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c<<2) => (MOVWUload [int32(c)<<2] ptr mem)
768 (MOVWloadidx4 ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c<<2) => (MOVWload [int32(c)<<2] ptr mem)
769 (MOVHUloadidx2 ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c<<1) => (MOVHUload [int32(c)<<1] ptr mem)
770 (MOVHloadidx2 ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c<<1) => (MOVHload [int32(c)<<1] ptr mem)
771
772 (FMOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) && off == 0 && sym == nil => (FMOVDloadidx8 ptr idx mem)
773 (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (FMOVSloadidx4 ptr idx mem)
774 (FMOVDloadidx ptr (SLLconst [3] idx) mem) => (FMOVDloadidx8 ptr idx mem)
775 (FMOVSloadidx ptr (SLLconst [2] idx) mem) => (FMOVSloadidx4 ptr idx mem)
776 (FMOVDloadidx (SLLconst [3] idx) ptr mem) => (FMOVDloadidx8 ptr idx mem)
777 (FMOVSloadidx (SLLconst [2] idx) ptr mem) => (FMOVSloadidx4 ptr idx mem)
778 (FMOVDloadidx8 ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c<<3) => (FMOVDload ptr [int32(c)<<3] mem)
779 (FMOVSloadidx4 ptr (MOVDconst [c]) mem) && ssa.Is32Bit(c<<2) => (FMOVSload ptr [int32(c)<<2] mem)
780
781 (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
782 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
783 (MOVBstore [off1+int32(off2)] {sym} ptr val mem)
784 (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
785 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
786 (MOVHstore [off1+int32(off2)] {sym} ptr val mem)
787 (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
788 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
789 (MOVWstore [off1+int32(off2)] {sym} ptr val mem)
790 (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
791 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
792 (MOVDstore [off1+int32(off2)] {sym} ptr val mem)
793 (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && ssa.Is32Bit(int64(off1)+off2)
794 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
795 (STP [off1+int32(off2)] {sym} ptr val1 val2 mem)
796 (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
797 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
798 (FMOVSstore [off1+int32(off2)] {sym} ptr val mem)
799 (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
800 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
801 (FMOVDstore [off1+int32(off2)] {sym} ptr val mem)
802 (FMOVQstore [off1] {sym} (ADDconst [off2] ptr) val mem) && ssa.Is32Bit(int64(off1)+off2)
803 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
804 (FMOVQstore [off1+int32(off2)] {sym} ptr val mem)
805 (FSTPQ [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && ssa.Is32Bit(int64(off1)+off2)
806 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
807 (FSTPQ [off1+int32(off2)] {sym} ptr val1 val2 mem)
808
809 // register indexed store
810 (MOVDstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem)
811 (MOVWstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr idx val mem)
812 (MOVHstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr idx val mem)
813 (MOVBstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr idx val mem)
814 (FMOVDstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (FMOVDstoreidx ptr idx val mem)
815 (FMOVSstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (FMOVSstoreidx ptr idx val mem)
816 (MOVDstoreidx ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c) => (MOVDstore [int32(c)] ptr val mem)
817 (MOVDstoreidx (MOVDconst [c]) idx val mem) && ssa.Is32Bit(c) => (MOVDstore [int32(c)] idx val mem)
818 (MOVWstoreidx ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c) => (MOVWstore [int32(c)] ptr val mem)
819 (MOVWstoreidx (MOVDconst [c]) idx val mem) && ssa.Is32Bit(c) => (MOVWstore [int32(c)] idx val mem)
820 (MOVHstoreidx ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c) => (MOVHstore [int32(c)] ptr val mem)
821 (MOVHstoreidx (MOVDconst [c]) idx val mem) && ssa.Is32Bit(c) => (MOVHstore [int32(c)] idx val mem)
822 (MOVBstoreidx ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c) => (MOVBstore [int32(c)] ptr val mem)
823 (MOVBstoreidx (MOVDconst [c]) idx val mem) && ssa.Is32Bit(c) => (MOVBstore [int32(c)] idx val mem)
824 (FMOVDstoreidx ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c) => (FMOVDstore [int32(c)] ptr val mem)
825 (FMOVDstoreidx (MOVDconst [c]) idx val mem) && ssa.Is32Bit(c) => (FMOVDstore [int32(c)] idx val mem)
826 (FMOVSstoreidx ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c) => (FMOVSstore [int32(c)] ptr val mem)
827 (FMOVSstoreidx (MOVDconst [c]) idx val mem) && ssa.Is32Bit(c) => (FMOVSstore [int32(c)] idx val mem)
828
829 // shifted register indexed store
830 (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx8 ptr idx val mem)
831 (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx4 ptr idx val mem)
832 (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx2 ptr idx val mem)
833 (MOVDstoreidx ptr (SLLconst [3] idx) val mem) => (MOVDstoreidx8 ptr idx val mem)
834 (MOVWstoreidx ptr (SLLconst [2] idx) val mem) => (MOVWstoreidx4 ptr idx val mem)
835 (MOVHstoreidx ptr (SLLconst [1] idx) val mem) => (MOVHstoreidx2 ptr idx val mem)
836 (MOVHstoreidx ptr (ADD idx idx) val mem) => (MOVHstoreidx2 ptr idx val mem)
837 (MOVDstoreidx (SLLconst [3] idx) ptr val mem) => (MOVDstoreidx8 ptr idx val mem)
838 (MOVWstoreidx (SLLconst [2] idx) ptr val mem) => (MOVWstoreidx4 ptr idx val mem)
839 (MOVHstoreidx (SLLconst [1] idx) ptr val mem) => (MOVHstoreidx2 ptr idx val mem)
840 (MOVHstoreidx (ADD idx idx) ptr val mem) => (MOVHstoreidx2 ptr idx val mem)
841 (MOVDstoreidx8 ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c<<3) => (MOVDstore [int32(c)<<3] ptr val mem)
842 (MOVWstoreidx4 ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c<<2) => (MOVWstore [int32(c)<<2] ptr val mem)
843 (MOVHstoreidx2 ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c<<1) => (MOVHstore [int32(c)<<1] ptr val mem)
844
845 (FMOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) && off == 0 && sym == nil => (FMOVDstoreidx8 ptr idx val mem)
846 (FMOVSstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) && off == 0 && sym == nil => (FMOVSstoreidx4 ptr idx val mem)
847 (FMOVDstoreidx ptr (SLLconst [3] idx) val mem) => (FMOVDstoreidx8 ptr idx val mem)
848 (FMOVSstoreidx ptr (SLLconst [2] idx) val mem) => (FMOVSstoreidx4 ptr idx val mem)
849 (FMOVDstoreidx (SLLconst [3] idx) ptr val mem) => (FMOVDstoreidx8 ptr idx val mem)
850 (FMOVSstoreidx (SLLconst [2] idx) ptr val mem) => (FMOVSstoreidx4 ptr idx val mem)
851 (FMOVDstoreidx8 ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c<<3) => (FMOVDstore [int32(c)<<3] ptr val mem)
852 (FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) && ssa.Is32Bit(c<<2) => (FMOVSstore [int32(c)<<2] ptr val mem)
853
854 (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
855 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
856 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
857 (MOVBload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
858 (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
859 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
860 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
861 (MOVBUload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
862 (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
863 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
864 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
865 (MOVHload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
866 (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
867 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
868 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
869 (MOVHUload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
870 (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
871 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
872 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
873 (MOVWload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
874 (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
875 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
876 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
877 (MOVWUload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
878 (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
879 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
880 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
881 (MOVDload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
882 (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
883 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
884 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
885 (LDP [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
886 (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
887 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
888 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
889 (FMOVSload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
890 (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
891 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
892 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
893 (FMOVDload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
894 (FMOVQload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
895 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
896 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
897 (FMOVQload [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
898 (FLDPQ [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
899 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
900 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
901 (FLDPQ [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr mem)
902
903 (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
904 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
905 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
906 (MOVBstore [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val mem)
907 (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
908 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
909 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
910 (MOVHstore [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val mem)
911 (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
912 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
913 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
914 (MOVWstore [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val mem)
915 (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
916 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
917 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
918 (MOVDstore [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val mem)
919 (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem)
920 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
921 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
922 (STP [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val1 val2 mem)
923 (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
924 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
925 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
926 (FMOVSstore [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val mem)
927 (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
928 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
929 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
930 (FMOVDstore [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val mem)
931 (FMOVQstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
932 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
933 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
934 (FMOVQstore [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val mem)
935 (FSTPQ [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem)
936 && ssa.CanMergeSym(sym1,sym2) && ssa.Is32Bit(int64(off1)+int64(off2))
937 && (ptr.Op != ssaop.OpSB || !config.Ctxt.Flag_dynlink) =>
938 (FSTPQ [off1+off2] {ssa.MergeSym(sym1,sym2)} ptr val1 val2 mem)
939
940 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
941 // these seem to have bad interaction with other rules, resulting in slower code
942 //(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> (MOVBreg x)
943 //(MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> (MOVBUreg x)
944 //(MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> (MOVHreg x)
945 //(MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> (MOVHUreg x)
946 //(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> (MOVWreg x)
947 //(MOVWUload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> (MOVWUreg x)
948 //(MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> x
949 //(FMOVSload [off] {sym} ptr (FMOVSstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> x
950 //(FMOVDload [off] {sym} ptr (FMOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> x
951 //(LDP [off] {sym} ptr (STP [off2] {sym2} ptr2 x y _)) && sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2) -> x y
952
953 // don't extend before store
954 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
955 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
956 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
957 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
958 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
959 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
960 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
961 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
962 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
963 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
964 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
965 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
966 (MOVBstoreidx ptr idx (MOVBreg x) mem) => (MOVBstoreidx ptr idx x mem)
967 (MOVBstoreidx ptr idx (MOVBUreg x) mem) => (MOVBstoreidx ptr idx x mem)
968 (MOVBstoreidx ptr idx (MOVHreg x) mem) => (MOVBstoreidx ptr idx x mem)
969 (MOVBstoreidx ptr idx (MOVHUreg x) mem) => (MOVBstoreidx ptr idx x mem)
970 (MOVBstoreidx ptr idx (MOVWreg x) mem) => (MOVBstoreidx ptr idx x mem)
971 (MOVBstoreidx ptr idx (MOVWUreg x) mem) => (MOVBstoreidx ptr idx x mem)
972 (MOVHstoreidx ptr idx (MOVHreg x) mem) => (MOVHstoreidx ptr idx x mem)
973 (MOVHstoreidx ptr idx (MOVHUreg x) mem) => (MOVHstoreidx ptr idx x mem)
974 (MOVHstoreidx ptr idx (MOVWreg x) mem) => (MOVHstoreidx ptr idx x mem)
975 (MOVHstoreidx ptr idx (MOVWUreg x) mem) => (MOVHstoreidx ptr idx x mem)
976 (MOVWstoreidx ptr idx (MOVWreg x) mem) => (MOVWstoreidx ptr idx x mem)
977 (MOVWstoreidx ptr idx (MOVWUreg x) mem) => (MOVWstoreidx ptr idx x mem)
978 (MOVHstoreidx2 ptr idx (MOVHreg x) mem) => (MOVHstoreidx2 ptr idx x mem)
979 (MOVHstoreidx2 ptr idx (MOVHUreg x) mem) => (MOVHstoreidx2 ptr idx x mem)
980 (MOVHstoreidx2 ptr idx (MOVWreg x) mem) => (MOVHstoreidx2 ptr idx x mem)
981 (MOVHstoreidx2 ptr idx (MOVWUreg x) mem) => (MOVHstoreidx2 ptr idx x mem)
982 (MOVWstoreidx4 ptr idx (MOVWreg x) mem) => (MOVWstoreidx4 ptr idx x mem)
983 (MOVWstoreidx4 ptr idx (MOVWUreg x) mem) => (MOVWstoreidx4 ptr idx x mem)
984
985 // if a register move has only 1 use, just use the same register without emitting instruction
986 // MOVDnop doesn't emit instruction, only for ensuring the type.
987 (MOVDreg x) && x.Uses == 1 => (MOVDnop x)
988
989 // TODO: we should be able to get rid of MOVDnop all together.
990 // But for now, this is enough to get rid of lots of them.
991 (MOVDnop (MOVDconst [c])) => (MOVDconst [c])
992
993 // fold constant into arithmetic ops
994 (ADD x (MOVDconst <t> [c])) && !t.IsPtr() => (ADDconst [c] x)
995 (SUB x (MOVDconst [c])) => (SUBconst [c] x)
996 (AND x (MOVDconst [c])) => (ANDconst [c] x)
997 (OR x (MOVDconst [c])) => (ORconst [c] x)
998 (XOR x (MOVDconst [c])) => (XORconst [c] x)
999 (TST x (MOVDconst [c])) => (TSTconst [c] x)
1000 (TSTW x (MOVDconst [c])) => (TSTWconst [int32(c)] x)
1001 (CMN x (MOVDconst [c])) => (CMNconst [c] x)
1002 (CMNW x (MOVDconst [c])) => (CMNWconst [int32(c)] x)
1003 (BIC x (MOVDconst [c])) => (ANDconst [^c] x)
1004 (EON x (MOVDconst [c])) => (XORconst [^c] x)
1005 (ORN x (MOVDconst [c])) => (ORconst [^c] x)
1006
1007 (SLL x (MOVDconst [c])) => (SLLconst x [c&63])
1008 (SRL x (MOVDconst [c])) => (SRLconst x [c&63])
1009 (SRA x (MOVDconst [c])) => (SRAconst x [c&63])
1010 (SLL x (ANDconst [63] y)) => (SLL x y)
1011 (SRL x (ANDconst [63] y)) => (SRL x y)
1012 (SRA x (ANDconst [63] y)) => (SRA x y)
1013
1014 (CMP x (MOVDconst [c])) => (CMPconst [c] x)
1015 (CMP (MOVDconst [c]) x) => (InvertFlags (CMPconst [c] x))
1016 (CMPW x (MOVDconst [c])) => (CMPWconst [int32(c)] x)
1017 (CMPW (MOVDconst [c]) x) => (InvertFlags (CMPWconst [int32(c)] x))
1018
1019 (ROR x (MOVDconst [c])) => (RORconst x [c&63])
1020 (RORW x (MOVDconst [c])) => (RORWconst x [c&31])
1021
1022 (ADDSflags x (MOVDconst [c])) => (ADDSconstflags [c] x)
1023
1024 (ADDconst [c] y) && c < 0 => (SUBconst [-c] y)
1025
1026 // Canonicalize the order of arguments to comparisons - helps with CSE.
1027 ((CMP|CMPW) x y) && ssa.CanonLessThan(x,y) => (InvertFlags ((CMP|CMPW) y x))
1028
1029 // mul-neg => mneg
1030 (NEG (MUL x y)) => (MNEG x y)
1031 (NEG (MULW x y)) && v.Type.Size() <= 4 => (MNEGW x y)
1032 (MUL (NEG x) y) => (MNEG x y)
1033 (MULW (NEG x) y) => (MNEGW x y)
1034
1035 // madd/msub
1036 (ADD a l:(MUL x y)) && l.Uses==1 && ssa.Clobber(l) => (MADD a x y)
1037 (SUB a l:(MUL x y)) && l.Uses==1 && ssa.Clobber(l) => (MSUB a x y)
1038 (ADD a l:(MNEG x y)) && l.Uses==1 && ssa.Clobber(l) => (MSUB a x y)
1039 (SUB a l:(MNEG x y)) && l.Uses==1 && ssa.Clobber(l) => (MADD a x y)
1040
1041 (ADD a l:(MULW x y)) && v.Type.Size() <= 4 && l.Uses==1 && ssa.Clobber(l) => (MADDW a x y)
1042 (SUB a l:(MULW x y)) && v.Type.Size() <= 4 && l.Uses==1 && ssa.Clobber(l) => (MSUBW a x y)
1043 (ADD a l:(MNEGW x y)) && v.Type.Size() <= 4 && l.Uses==1 && ssa.Clobber(l) => (MSUBW a x y)
1044 (SUB a l:(MNEGW x y)) && v.Type.Size() <= 4 && l.Uses==1 && ssa.Clobber(l) => (MADDW a x y)
1045
1046 // madd/msub can't take constant arguments, so do a bit of reordering if a non-constant is available.
1047 // Note: don't reorder arithmetic concerning pointers, as we must ensure that
1048 // no intermediate computations are invalid pointers.
1049 (ADD <t> a p:(ADDconst [c] m:((MUL|MULW|MNEG|MNEGW) _ _))) && p.Uses==1 && m.Uses==1 && !t.IsPtrShaped() => (ADDconst [c] (ADD <v.Type> a m))
1050 (ADD <t> a p:(SUBconst [c] m:((MUL|MULW|MNEG|MNEGW) _ _))) && p.Uses==1 && m.Uses==1 && !t.IsPtrShaped() => (SUBconst [c] (ADD <v.Type> a m))
1051 (SUB <t> a p:(ADDconst [c] m:((MUL|MULW|MNEG|MNEGW) _ _))) && p.Uses==1 && m.Uses==1 && !t.IsPtrShaped() => (SUBconst [c] (SUB <v.Type> a m))
1052 (SUB <t> a p:(SUBconst [c] m:((MUL|MULW|MNEG|MNEGW) _ _))) && p.Uses==1 && m.Uses==1 && !t.IsPtrShaped() => (ADDconst [c] (SUB <v.Type> a m))
1053
1054 // optimize ADCSflags, SBCSflags and friends
1055 (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (ADCzerocarry <typ.UInt64> c)))) => (ADCSflags x y c)
1056 (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (MOVDconst [0])))) => (ADDSflags x y)
1057 (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags (NEG <typ.UInt64> (NGCzerocarry <typ.UInt64> bo))))) => (SBCSflags x y bo)
1058 (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags (MOVDconst [0])))) => (SUBSflags x y)
1059
1060 // mul by constant
1061 (MUL _ (MOVDconst [0])) => (MOVDconst [0])
1062 (MUL x (MOVDconst [1])) => x
1063
1064 (MULW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0])
1065 (MULW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg x)
1066
1067 (MUL x (MOVDconst [c])) && ssa.CanMulStrengthReduce(config, c) => {ssa.MulStrengthReduce(v, x, c)}
1068 (MULW x (MOVDconst [c])) && v.Type.Size() <= 4 && ssa.CanMulStrengthReduce32(config, int32(c)) => {ssa.MulStrengthReduce32(v, x, int32(c))}
1069
1070 // mneg by constant
1071 (MNEG x (MOVDconst [-1])) => x
1072 (MNEG _ (MOVDconst [0])) => (MOVDconst [0])
1073 (MNEG x (MOVDconst [1])) => (NEG x)
1074 (MNEG x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) => (NEG (SLLconst <x.Type> [ssa.Log64(c)] x))
1075 (MNEG x (MOVDconst [c])) && ssa.IsPowerOfTwo(c-1) && c >= 3 => (NEG (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)]))
1076 (MNEG x (MOVDconst [c])) && ssa.IsPowerOfTwo(c+1) && c >= 7 => (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [ssa.Log64(c+1)]))
1077 (MNEG x (MOVDconst [c])) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) => (SLLconst <x.Type> [ssa.Log64(c/3)] (SUBshiftLL <x.Type> x x [2]))
1078 (MNEG x (MOVDconst [c])) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) => (NEG (SLLconst <x.Type> [ssa.Log64(c/5)] (ADDshiftLL <x.Type> x x [2])))
1079 (MNEG x (MOVDconst [c])) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) => (SLLconst <x.Type> [ssa.Log64(c/7)] (SUBshiftLL <x.Type> x x [3]))
1080 (MNEG x (MOVDconst [c])) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) => (NEG (SLLconst <x.Type> [ssa.Log64(c/9)] (ADDshiftLL <x.Type> x x [3])))
1081
1082
1083 (MNEGW x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg x)
1084 (MNEGW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0])
1085 (MNEGW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (NEG <x.Type> x))
1086 (MNEGW x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) => (NEG (SLLconst <x.Type> [ssa.Log64(c)] x))
1087 (MNEGW x (MOVDconst [c])) && ssa.IsPowerOfTwo(c-1) && int32(c) >= 3 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)])))
1088 (MNEGW x (MOVDconst [c])) && ssa.IsPowerOfTwo(c+1) && int32(c) >= 7 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> (NEG <x.Type> x) x [ssa.Log64(c+1)])))
1089 (MNEGW x (MOVDconst [c])) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) && ssa.Is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [ssa.Log64(c/3)] (SUBshiftLL <x.Type> x x [2])))
1090 (MNEGW x (MOVDconst [c])) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) && ssa.Is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [ssa.Log64(c/5)] (ADDshiftLL <x.Type> x x [2]))))
1091 (MNEGW x (MOVDconst [c])) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) && ssa.Is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [ssa.Log64(c/7)] (SUBshiftLL <x.Type> x x [3])))
1092 (MNEGW x (MOVDconst [c])) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) && ssa.Is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [ssa.Log64(c/9)] (ADDshiftLL <x.Type> x x [3]))))
1093
1094
1095 (MADD a x (MOVDconst [-1])) => (SUB a x)
1096 (MADD a _ (MOVDconst [0])) => a
1097 (MADD a x (MOVDconst [1])) => (ADD a x)
1098 (MADD a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) => (ADDshiftLL a x [ssa.Log64(c)])
1099 (MADD a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)]))
1100 (MADD a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [ssa.Log64(c+1)]))
1101 (MADD a x (MOVDconst [c])) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [ssa.Log64(c/3)])
1102 (MADD a x (MOVDconst [c])) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [ssa.Log64(c/5)])
1103 (MADD a x (MOVDconst [c])) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [ssa.Log64(c/7)])
1104 (MADD a x (MOVDconst [c])) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [ssa.Log64(c/9)])
1105
1106 (MADD a (MOVDconst [-1]) x) => (SUB a x)
1107 (MADD a (MOVDconst [0]) _) => a
1108 (MADD a (MOVDconst [1]) x) => (ADD a x)
1109 (MADD a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c) => (ADDshiftLL a x [ssa.Log64(c)])
1110 (MADD a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)]))
1111 (MADD a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [ssa.Log64(c+1)]))
1112 (MADD a (MOVDconst [c]) x) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [ssa.Log64(c/3)])
1113 (MADD a (MOVDconst [c]) x) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [ssa.Log64(c/5)])
1114 (MADD a (MOVDconst [c]) x) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [ssa.Log64(c/7)])
1115 (MADD a (MOVDconst [c]) x) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [ssa.Log64(c/9)])
1116
1117 (MADDW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x))
1118 (MADDW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a)
1119 (MADDW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x))
1120 (MADDW a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [ssa.Log64(c)]))
1121 (MADDW a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)])))
1122 (MADDW a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [ssa.Log64(c+1)])))
1123 (MADDW a x (MOVDconst [c])) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) && ssa.Is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [ssa.Log64(c/3)]))
1124 (MADDW a x (MOVDconst [c])) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) && ssa.Is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [ssa.Log64(c/5)]))
1125 (MADDW a x (MOVDconst [c])) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) && ssa.Is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [ssa.Log64(c/7)]))
1126 (MADDW a x (MOVDconst [c])) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) && ssa.Is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [ssa.Log64(c/9)]))
1127
1128 (MADDW a (MOVDconst [c]) x) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x))
1129 (MADDW a (MOVDconst [c]) _) && int32(c)==0 => (MOVWUreg a)
1130 (MADDW a (MOVDconst [c]) x) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x))
1131 (MADDW a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [ssa.Log64(c)]))
1132 (MADDW a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)])))
1133 (MADDW a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [ssa.Log64(c+1)])))
1134 (MADDW a (MOVDconst [c]) x) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) && ssa.Is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [ssa.Log64(c/3)]))
1135 (MADDW a (MOVDconst [c]) x) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) && ssa.Is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [ssa.Log64(c/5)]))
1136 (MADDW a (MOVDconst [c]) x) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) && ssa.Is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [ssa.Log64(c/7)]))
1137 (MADDW a (MOVDconst [c]) x) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) && ssa.Is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [ssa.Log64(c/9)]))
1138
1139 (MSUB a x (MOVDconst [-1])) => (ADD a x)
1140 (MSUB a _ (MOVDconst [0])) => a
1141 (MSUB a x (MOVDconst [1])) => (SUB a x)
1142 (MSUB a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) => (SUBshiftLL a x [ssa.Log64(c)])
1143 (MSUB a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)]))
1144 (MSUB a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [ssa.Log64(c+1)]))
1145 (MSUB a x (MOVDconst [c])) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [ssa.Log64(c/3)])
1146 (MSUB a x (MOVDconst [c])) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [ssa.Log64(c/5)])
1147 (MSUB a x (MOVDconst [c])) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [ssa.Log64(c/7)])
1148 (MSUB a x (MOVDconst [c])) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [ssa.Log64(c/9)])
1149
1150 (MSUB a (MOVDconst [-1]) x) => (ADD a x)
1151 (MSUB a (MOVDconst [0]) _) => a
1152 (MSUB a (MOVDconst [1]) x) => (SUB a x)
1153 (MSUB a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c) => (SUBshiftLL a x [ssa.Log64(c)])
1154 (MSUB a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)]))
1155 (MSUB a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [ssa.Log64(c+1)]))
1156 (MSUB a (MOVDconst [c]) x) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [ssa.Log64(c/3)])
1157 (MSUB a (MOVDconst [c]) x) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [ssa.Log64(c/5)])
1158 (MSUB a (MOVDconst [c]) x) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [ssa.Log64(c/7)])
1159 (MSUB a (MOVDconst [c]) x) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [ssa.Log64(c/9)])
1160
1161 (MSUBW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x))
1162 (MSUBW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a)
1163 (MSUBW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x))
1164 (MSUBW a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [ssa.Log64(c)]))
1165 (MSUBW a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)])))
1166 (MSUBW a x (MOVDconst [c])) && ssa.IsPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [ssa.Log64(c+1)])))
1167 (MSUBW a x (MOVDconst [c])) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) && ssa.Is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [ssa.Log64(c/3)]))
1168 (MSUBW a x (MOVDconst [c])) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) && ssa.Is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [ssa.Log64(c/5)]))
1169 (MSUBW a x (MOVDconst [c])) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) && ssa.Is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [ssa.Log64(c/7)]))
1170 (MSUBW a x (MOVDconst [c])) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) && ssa.Is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [ssa.Log64(c/9)]))
1171
1172 (MSUBW a (MOVDconst [c]) x) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x))
1173 (MSUBW a (MOVDconst [c]) _) && int32(c)==0 => (MOVWUreg a)
1174 (MSUBW a (MOVDconst [c]) x) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x))
1175 (MSUBW a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [ssa.Log64(c)]))
1176 (MSUBW a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [ssa.Log64(c-1)])))
1177 (MSUBW a (MOVDconst [c]) x) && ssa.IsPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [ssa.Log64(c+1)])))
1178 (MSUBW a (MOVDconst [c]) x) && c%3 == 0 && ssa.IsPowerOfTwo(c/3) && ssa.Is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [ssa.Log64(c/3)]))
1179 (MSUBW a (MOVDconst [c]) x) && c%5 == 0 && ssa.IsPowerOfTwo(c/5) && ssa.Is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [ssa.Log64(c/5)]))
1180 (MSUBW a (MOVDconst [c]) x) && c%7 == 0 && ssa.IsPowerOfTwo(c/7) && ssa.Is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [ssa.Log64(c/7)]))
1181 (MSUBW a (MOVDconst [c]) x) && c%9 == 0 && ssa.IsPowerOfTwo(c/9) && ssa.Is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [ssa.Log64(c/9)]))
1182
1183 // div by constant
1184 (UDIV x (MOVDconst [1])) => x
1185 (UDIV x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) => (SRLconst [ssa.Log64(c)] x)
1186 (UDIVW x (MOVDconst [c])) && uint32(c)==1 => (MOVWUreg x)
1187 (UDIVW x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) && ssa.Is32Bit(c) => (SRLconst [ssa.Log64(c)] (MOVWUreg <v.Type> x))
1188 (UMOD _ (MOVDconst [1])) => (MOVDconst [0])
1189 (UMOD x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) => (ANDconst [c-1] x)
1190 (UMODW _ (MOVDconst [c])) && uint32(c)==1 => (MOVDconst [0])
1191 (UMODW x (MOVDconst [c])) && ssa.IsPowerOfTwo(c) && ssa.Is32Bit(c) => (ANDconst [c-1] x)
1192
1193 // generic simplifications
1194 (ADD x (NEG y)) => (SUB x y)
1195 (SUB x (NEG y)) => (ADD x y)
1196 (SUB x x) => (MOVDconst [0])
1197 (AND x x) => x
1198 (OR x x) => x
1199 (XOR x x) => (MOVDconst [0])
1200 (BIC x x) => (MOVDconst [0])
1201 (EON x x) => (MOVDconst [-1])
1202 (ORN x x) => (MOVDconst [-1])
1203 (AND x (MVN y)) => (BIC x y)
1204 (XOR x (MVN y)) => (EON x y)
1205 (OR x (MVN y)) => (ORN x y)
1206 (MVN (XOR x y)) => (EON x y)
1207 (NEG (SUB x y)) => (SUB y x)
1208 (NEG (NEG x)) => x
1209
1210 (CSEL [cc] (MOVDconst [-1]) (MOVDconst [0]) flag) => (CSETM [cc] flag)
1211 (CSEL [cc] (MOVDconst [0]) (MOVDconst [-1]) flag) => (CSETM [arm64Negate(cc)] flag)
1212 (CSEL [cc] x (MOVDconst [0]) flag) => (CSEL0 [cc] x flag)
1213 (CSEL [cc] (MOVDconst [0]) y flag) => (CSEL0 [arm64Negate(cc)] y flag)
1214 (CSEL [cc] x (ADDconst [1] a) flag) => (CSINC [cc] x a flag)
1215 (CSEL [cc] (ADDconst [1] a) x flag) => (CSINC [arm64Negate(cc)] x a flag)
1216 (CSEL [cc] x (MVN a) flag) => (CSINV [cc] x a flag)
1217 (CSEL [cc] (MVN a) x flag) => (CSINV [arm64Negate(cc)] x a flag)
1218 (CSEL [cc] x (NEG a) flag) => (CSNEG [cc] x a flag)
1219 (CSEL [cc] (NEG a) x flag) => (CSNEG [arm64Negate(cc)] x a flag)
1220
1221 (SUB x (SUB y z)) => (SUB (ADD <v.Type> x z) y)
1222 (SUB (SUB x y) z) => (SUB x (ADD <y.Type> y z))
1223
1224 // remove redundant *const ops
1225 (ADDconst [0] x) => x
1226 (SUBconst [0] x) => x
1227 (ANDconst [0] _) => (MOVDconst [0])
1228 (ANDconst [-1] x) => x
1229 (ORconst [0] x) => x
1230 (ORconst [-1] _) => (MOVDconst [-1])
1231 (XORconst [0] x) => x
1232 (XORconst [-1] x) => (MVN x)
1233
1234 // generic constant folding
1235 (ADDconst [c] (MOVDconst [d])) => (MOVDconst [c+d])
1236 (ADDconst [c] (ADDconst [d] x)) => (ADDconst [c+d] x)
1237 (ADDconst [c] (SUBconst [d] x)) => (ADDconst [c-d] x)
1238 (SUBconst [c] (MOVDconst [d])) => (MOVDconst [d-c])
1239 (SUBconst [c] (SUBconst [d] x)) => (ADDconst [-c-d] x)
1240 (SUBconst [c] (ADDconst [d] x)) => (ADDconst [-c+d] x)
1241 (SLLconst [c] (MOVDconst [d])) => (MOVDconst [d<<uint64(c)])
1242 (SRLconst [c] (MOVDconst [d])) => (MOVDconst [int64(uint64(d)>>uint64(c))])
1243 (SRAconst [c] (MOVDconst [d])) => (MOVDconst [d>>uint64(c)])
1244 (MUL (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c*d])
1245 (MNEG (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [-c*d])
1246 (MULW (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [int64(uint32(c*d))])
1247 (MNEGW (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [int64(uint32(-c*d))])
1248 (MADD (MOVDconst [c]) x y) => (ADDconst [c] (MUL <x.Type> x y))
1249 (MSUB (MOVDconst [c]) x y) => (ADDconst [c] (MNEG <x.Type> x y))
1250 (MADD a (MOVDconst [c]) (MOVDconst [d])) => (ADDconst [c*d] a)
1251 (MSUB a (MOVDconst [c]) (MOVDconst [d])) => (SUBconst [c*d] a)
1252 (MADDW (MOVDconst [c]) x y) => (MOVWUreg (ADDconst <x.Type> [c] (MULW <x.Type> x y)))
1253 (MSUBW (MOVDconst [c]) x y) => (MOVWUreg (ADDconst <x.Type> [c] (MNEGW <x.Type> x y)))
1254 (MADDW a (MOVDconst [c]) (MOVDconst [d])) => (MOVWUreg (ADDconst <a.Type> [c*d] a))
1255 (MSUBW a (MOVDconst [c]) (MOVDconst [d])) => (MOVWUreg (SUBconst <a.Type> [c*d] a))
1256 (DIV (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [c/d])
1257 (UDIV (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint64(c)/uint64(d))])
1258 (DIVW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(int32(c)/int32(d)))])
1259 (UDIVW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(c)/uint32(d))])
1260 (MOD (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [c%d])
1261 (UMOD (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint64(c)%uint64(d))])
1262 (MODW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(int32(c)%int32(d)))])
1263 (UMODW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(c)%uint32(d))])
1264 (ANDconst [c] (MOVDconst [d])) => (MOVDconst [c&d])
1265 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
1266 (ANDconst [c] (MOVWUreg x)) => (ANDconst [c&(1<<32-1)] x)
1267 (ANDconst [c] (MOVHUreg x)) => (ANDconst [c&(1<<16-1)] x)
1268 (ANDconst [c] (MOVBUreg x)) => (ANDconst [c&(1<<8-1)] x)
1269 (MOVWUreg (ANDconst [c] x)) => (ANDconst [c&(1<<32-1)] x)
1270 (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&(1<<16-1)] x)
1271 (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&(1<<8-1)] x)
1272 (ORconst [c] (MOVDconst [d])) => (MOVDconst [c|d])
1273 (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x)
1274 (XORconst [c] (MOVDconst [d])) => (MOVDconst [c^d])
1275 (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x)
1276 (MVN (MOVDconst [c])) => (MOVDconst [^c])
1277 (NEG (MOVDconst [c])) => (MOVDconst [-c])
1278 (MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))])
1279 (MOVBUreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))])
1280 (MOVHreg (MOVDconst [c])) => (MOVDconst [int64(int16(c))])
1281 (MOVHUreg (MOVDconst [c])) => (MOVDconst [int64(uint16(c))])
1282 (MOVWreg (MOVDconst [c])) => (MOVDconst [int64(int32(c))])
1283 (MOVWUreg (MOVDconst [c])) => (MOVDconst [int64(uint32(c))])
1284 (MOVDreg (MOVDconst [c])) => (MOVDconst [c])
1285
1286 // constant comparisons
1287 (CMPconst (MOVDconst [x]) [y]) => (FlagConstant [ssa.SubFlags64(x,y)])
1288 (CMPWconst (MOVDconst [x]) [y]) => (FlagConstant [ssa.SubFlags32(int32(x),y)])
1289 (TSTconst (MOVDconst [x]) [y]) => (FlagConstant [ssa.LogicFlags64(x&y)])
1290 (TSTWconst (MOVDconst [x]) [y]) => (FlagConstant [ssa.LogicFlags32(int32(x)&y)])
1291 (CMNconst (MOVDconst [x]) [y]) => (FlagConstant [ssa.AddFlags64(x,y)])
1292 (CMNWconst (MOVDconst [x]) [y]) => (FlagConstant [ssa.AddFlags32(int32(x),y)])
1293
1294 // other known comparisons
1295 (CMPconst (MOVBUreg _) [c]) && 0xff < c => (FlagConstant [ssa.SubFlags64(0,1)])
1296 (CMPconst (MOVHUreg _) [c]) && 0xffff < c => (FlagConstant [ssa.SubFlags64(0,1)])
1297 (CMPconst (MOVWUreg _) [c]) && 0xffffffff < c => (FlagConstant [ssa.SubFlags64(0,1)])
1298 (CMPconst (ANDconst _ [m]) [n]) && 0 <= m && m < n => (FlagConstant [ssa.SubFlags64(0,1)])
1299 (CMPconst (SRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 63 && (1<<uint64(64-c)) <= uint64(n) => (FlagConstant [ssa.SubFlags64(0,1)])
1300 (CMPWconst (MOVBUreg _) [c]) && 0xff < c => (FlagConstant [ssa.SubFlags64(0,1)])
1301 (CMPWconst (MOVHUreg _) [c]) && 0xffff < c => (FlagConstant [ssa.SubFlags64(0,1)])
1302
1303 // absorb flag constants into branches
1304 (EQ (FlagConstant [fc]) yes no) && fc.Eq() => (First yes no)
1305 (EQ (FlagConstant [fc]) yes no) && !fc.Eq() => (First no yes)
1306
1307 (NE (FlagConstant [fc]) yes no) && fc.Ne() => (First yes no)
1308 (NE (FlagConstant [fc]) yes no) && !fc.Ne() => (First no yes)
1309
1310 (LT (FlagConstant [fc]) yes no) && fc.Lt() => (First yes no)
1311 (LT (FlagConstant [fc]) yes no) && !fc.Lt() => (First no yes)
1312
1313 (LE (FlagConstant [fc]) yes no) && fc.Le() => (First yes no)
1314 (LE (FlagConstant [fc]) yes no) && !fc.Le() => (First no yes)
1315
1316 (GT (FlagConstant [fc]) yes no) && fc.Gt() => (First yes no)
1317 (GT (FlagConstant [fc]) yes no) && !fc.Gt() => (First no yes)
1318
1319 (GE (FlagConstant [fc]) yes no) && fc.Ge() => (First yes no)
1320 (GE (FlagConstant [fc]) yes no) && !fc.Ge() => (First no yes)
1321
1322 (ULT (FlagConstant [fc]) yes no) && fc.Ult() => (First yes no)
1323 (ULT (FlagConstant [fc]) yes no) && !fc.Ult() => (First no yes)
1324
1325 (ULE (FlagConstant [fc]) yes no) && fc.Ule() => (First yes no)
1326 (ULE (FlagConstant [fc]) yes no) && !fc.Ule() => (First no yes)
1327
1328 (UGT (FlagConstant [fc]) yes no) && fc.Ugt() => (First yes no)
1329 (UGT (FlagConstant [fc]) yes no) && !fc.Ugt() => (First no yes)
1330
1331 (UGE (FlagConstant [fc]) yes no) && fc.Uge() => (First yes no)
1332 (UGE (FlagConstant [fc]) yes no) && !fc.Uge() => (First no yes)
1333
1334 (LTnoov (FlagConstant [fc]) yes no) && fc.LtNoov() => (First yes no)
1335 (LTnoov (FlagConstant [fc]) yes no) && !fc.LtNoov() => (First no yes)
1336
1337 (LEnoov (FlagConstant [fc]) yes no) && fc.LeNoov() => (First yes no)
1338 (LEnoov (FlagConstant [fc]) yes no) && !fc.LeNoov() => (First no yes)
1339
1340 (GTnoov (FlagConstant [fc]) yes no) && fc.GtNoov() => (First yes no)
1341 (GTnoov (FlagConstant [fc]) yes no) && !fc.GtNoov() => (First no yes)
1342
1343 (GEnoov (FlagConstant [fc]) yes no) && fc.GeNoov() => (First yes no)
1344 (GEnoov (FlagConstant [fc]) yes no) && !fc.GeNoov() => (First no yes)
1345
1346 (Z (MOVDconst [0]) yes no) => (First yes no)
1347 (Z (MOVDconst [c]) yes no) && c != 0 => (First no yes)
1348 (NZ (MOVDconst [0]) yes no) => (First no yes)
1349 (NZ (MOVDconst [c]) yes no) && c != 0 => (First yes no)
1350 (ZW (MOVDconst [c]) yes no) && int32(c) == 0 => (First yes no)
1351 (ZW (MOVDconst [c]) yes no) && int32(c) != 0 => (First no yes)
1352 (NZW (MOVDconst [c]) yes no) && int32(c) == 0 => (First no yes)
1353 (NZW (MOVDconst [c]) yes no) && int32(c) != 0 => (First yes no)
1354
1355 // absorb InvertFlags into branches
1356 (LT (InvertFlags cmp) yes no) => (GT cmp yes no)
1357 (GT (InvertFlags cmp) yes no) => (LT cmp yes no)
1358 (LE (InvertFlags cmp) yes no) => (GE cmp yes no)
1359 (GE (InvertFlags cmp) yes no) => (LE cmp yes no)
1360 (ULT (InvertFlags cmp) yes no) => (UGT cmp yes no)
1361 (UGT (InvertFlags cmp) yes no) => (ULT cmp yes no)
1362 (ULE (InvertFlags cmp) yes no) => (UGE cmp yes no)
1363 (UGE (InvertFlags cmp) yes no) => (ULE cmp yes no)
1364 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
1365 (NE (InvertFlags cmp) yes no) => (NE cmp yes no)
1366 (FLT (InvertFlags cmp) yes no) => (FGT cmp yes no)
1367 (FGT (InvertFlags cmp) yes no) => (FLT cmp yes no)
1368 (FLE (InvertFlags cmp) yes no) => (FGE cmp yes no)
1369 (FGE (InvertFlags cmp) yes no) => (FLE cmp yes no)
1370
1371 // absorb InvertFlags into conditional instructions
1372 (CSEL [cc] x y (InvertFlags cmp)) => (CSEL [arm64Invert(cc)] x y cmp)
1373 (CSEL0 [cc] x (InvertFlags cmp)) => (CSEL0 [arm64Invert(cc)] x cmp)
1374 (FCSELD [cc] x y (InvertFlags cmp)) => (FCSELD [arm64Invert(cc)] x y cmp)
1375 (FCSELS [cc] x y (InvertFlags cmp)) => (FCSELS [arm64Invert(cc)] x y cmp)
1376 (CSETM [cc] (InvertFlags cmp)) => (CSETM [arm64Invert(cc)] cmp)
1377 (CSINC [cc] x y (InvertFlags cmp)) => (CSINC [arm64Invert(cc)] x y cmp)
1378 (CSINV [cc] x y (InvertFlags cmp)) => (CSINV [arm64Invert(cc)] x y cmp)
1379 (CSNEG [cc] x y (InvertFlags cmp)) => (CSNEG [arm64Invert(cc)] x y cmp)
1380
1381 // absorb flag constants into boolean values
1382 (Equal (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Eq())])
1383 (NotEqual (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Ne())])
1384 (LessThan (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Lt())])
1385 (LessThanU (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Ult())])
1386 (LessEqual (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Le())])
1387 (LessEqualU (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Ule())])
1388 (GreaterThan (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Gt())])
1389 (GreaterThanU (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Ugt())])
1390 (GreaterEqual (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Ge())])
1391 (GreaterEqualU (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.Uge())])
1392 (LessThanNoov (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.LtNoov())])
1393 (GreaterEqualNoov (FlagConstant [fc])) => (MOVDconst [ssa.B2i(fc.GeNoov())])
1394
1395 // absorb InvertFlags into boolean values
1396 (Equal (InvertFlags x)) => (Equal x)
1397 (NotEqual (InvertFlags x)) => (NotEqual x)
1398 (LessThan (InvertFlags x)) => (GreaterThan x)
1399 (LessThanU (InvertFlags x)) => (GreaterThanU x)
1400 (GreaterThan (InvertFlags x)) => (LessThan x)
1401 (GreaterThanU (InvertFlags x)) => (LessThanU x)
1402 (LessEqual (InvertFlags x)) => (GreaterEqual x)
1403 (LessEqualU (InvertFlags x)) => (GreaterEqualU x)
1404 (GreaterEqual (InvertFlags x)) => (LessEqual x)
1405 (GreaterEqualU (InvertFlags x)) => (LessEqualU x)
1406 (LessThanF (InvertFlags x)) => (GreaterThanF x)
1407 (LessEqualF (InvertFlags x)) => (GreaterEqualF x)
1408 (GreaterThanF (InvertFlags x)) => (LessThanF x)
1409 (GreaterEqualF (InvertFlags x)) => (LessEqualF x)
1410
1411 (GreaterEqual (CMPconst x [0])) => (XORconst [1] (SRLconst <v.Type> [63] x))
1412 (LessThan (CMPconst x [0])) => (SRLconst [63] x)
1413 (GreaterEqual (CMPWconst x [0])) => (XORconst [1] (UBFX <v.Type> [ssa.ArmBFAuxInt(31,1)] x))
1414 (LessThan (CMPWconst x [0])) => (UBFX [ssa.ArmBFAuxInt(31,1)] x)
1415
1416 // Don't bother extending if we're not using the higher bits.
1417 (MOV(B|BU)reg x) && v.Type.Size() <= 1 => x
1418 (MOV(H|HU)reg x) && v.Type.Size() <= 2 => x
1419 (MOV(W|WU)reg x) && v.Type.Size() <= 4 => x
1420
1421 // omit sign extension
1422 (MOVWreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffff80000000) == 0 => (ANDconst <t> x [c])
1423 (MOVHreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffff8000) == 0 => (ANDconst <t> x [c])
1424 (MOVBreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffffff80) == 0 => (ANDconst <t> x [c])
1425
1426 // absorb flag constants into conditional instructions
1427 (CSEL [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
1428 (CSEL [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => y
1429 (CSEL0 [cc] x flag) && ccARM64Eval(cc, flag) > 0 => x
1430 (CSEL0 [cc] _ flag) && ccARM64Eval(cc, flag) < 0 => (MOVDconst [0])
1431 (CSNEG [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
1432 (CSNEG [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (NEG y)
1433 (CSINV [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
1434 (CSINV [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (Not y)
1435 (CSINC [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
1436 (CSINC [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (ADDconst [1] y)
1437 (CSETM [cc] flag) && ccARM64Eval(cc, flag) > 0 => (MOVDconst [-1])
1438 (CSETM [cc] flag) && ccARM64Eval(cc, flag) < 0 => (MOVDconst [0])
1439
1440 // absorb flags back into boolean CSEL
1441 (CSEL [cc] x y (CMPWconst [0] boolval)) && cc == ssaop.OpARM64NotEqual && ssa.FlagArg(boolval) != nil =>
1442 (CSEL [boolval.Op] x y ssa.FlagArg(boolval))
1443 (CSEL [cc] x y (CMPWconst [0] boolval)) && cc == ssaop.OpARM64Equal && ssa.FlagArg(boolval) != nil =>
1444 (CSEL [arm64Negate(boolval.Op)] x y ssa.FlagArg(boolval))
1445 (CSEL0 [cc] x (CMPWconst [0] boolval)) && cc == ssaop.OpARM64NotEqual && ssa.FlagArg(boolval) != nil =>
1446 (CSEL0 [boolval.Op] x ssa.FlagArg(boolval))
1447 (CSEL0 [cc] x (CMPWconst [0] boolval)) && cc == ssaop.OpARM64Equal && ssa.FlagArg(boolval) != nil =>
1448 (CSEL0 [arm64Negate(boolval.Op)] x ssa.FlagArg(boolval))
1449
1450 // absorb shifts into ops
1451 (NEG x:(SLLconst [c] y)) && ssa.ClobberIfDead(x) => (NEGshiftLL [c] y)
1452 (NEG x:(SRLconst [c] y)) && ssa.ClobberIfDead(x) => (NEGshiftRL [c] y)
1453 (NEG x:(SRAconst [c] y)) && ssa.ClobberIfDead(x) => (NEGshiftRA [c] y)
1454 (MVN x:(SLLconst [c] y)) && ssa.ClobberIfDead(x) => (MVNshiftLL [c] y)
1455 (MVN x:(SRLconst [c] y)) && ssa.ClobberIfDead(x) => (MVNshiftRL [c] y)
1456 (MVN x:(SRAconst [c] y)) && ssa.ClobberIfDead(x) => (MVNshiftRA [c] y)
1457 (MVN x:(RORconst [c] y)) && ssa.ClobberIfDead(x) => (MVNshiftRO [c] y)
1458 (ADD x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (ADDshiftLL x0 y [c])
1459 (ADD x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (ADDshiftRL x0 y [c])
1460 (ADD x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (ADDshiftRA x0 y [c])
1461 (SUB x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (SUBshiftLL x0 y [c])
1462 (SUB x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (SUBshiftRL x0 y [c])
1463 (SUB x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (SUBshiftRA x0 y [c])
1464 (AND x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (ANDshiftLL x0 y [c])
1465 (AND x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (ANDshiftRL x0 y [c])
1466 (AND x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (ANDshiftRA x0 y [c])
1467 (AND x0 x1:(RORconst [c] y)) && ssa.ClobberIfDead(x1) => (ANDshiftRO x0 y [c])
1468 (OR x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (ORshiftLL x0 y [c]) // useful for combined load
1469 (OR x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (ORshiftRL x0 y [c])
1470 (OR x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (ORshiftRA x0 y [c])
1471 (OR x0 x1:(RORconst [c] y)) && ssa.ClobberIfDead(x1) => (ORshiftRO x0 y [c])
1472 (XOR x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (XORshiftLL x0 y [c])
1473 (XOR x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (XORshiftRL x0 y [c])
1474 (XOR x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (XORshiftRA x0 y [c])
1475 (XOR x0 x1:(RORconst [c] y)) && ssa.ClobberIfDead(x1) => (XORshiftRO x0 y [c])
1476 (BIC x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (BICshiftLL x0 y [c])
1477 (BIC x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (BICshiftRL x0 y [c])
1478 (BIC x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (BICshiftRA x0 y [c])
1479 (BIC x0 x1:(RORconst [c] y)) && ssa.ClobberIfDead(x1) => (BICshiftRO x0 y [c])
1480 (ORN x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (ORNshiftLL x0 y [c])
1481 (ORN x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (ORNshiftRL x0 y [c])
1482 (ORN x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (ORNshiftRA x0 y [c])
1483 (ORN x0 x1:(RORconst [c] y)) && ssa.ClobberIfDead(x1) => (ORNshiftRO x0 y [c])
1484 (EON x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (EONshiftLL x0 y [c])
1485 (EON x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (EONshiftRL x0 y [c])
1486 (EON x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (EONshiftRA x0 y [c])
1487 (EON x0 x1:(RORconst [c] y)) && ssa.ClobberIfDead(x1) => (EONshiftRO x0 y [c])
1488 (CMP x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (CMPshiftLL x0 y [c])
1489 (CMP x0:(SLLconst [c] y) x1) && ssa.ClobberIfDead(x0) => (InvertFlags (CMPshiftLL x1 y [c]))
1490 (CMP x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (CMPshiftRL x0 y [c])
1491 (CMP x0:(SRLconst [c] y) x1) && ssa.ClobberIfDead(x0) => (InvertFlags (CMPshiftRL x1 y [c]))
1492 (CMP x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (CMPshiftRA x0 y [c])
1493 (CMP x0:(SRAconst [c] y) x1) && ssa.ClobberIfDead(x0) => (InvertFlags (CMPshiftRA x1 y [c]))
1494 (CMN x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (CMNshiftLL x0 y [c])
1495 (CMN x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (CMNshiftRL x0 y [c])
1496 (CMN x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (CMNshiftRA x0 y [c])
1497 (TST x0 x1:(SLLconst [c] y)) && ssa.ClobberIfDead(x1) => (TSTshiftLL x0 y [c])
1498 (TST x0 x1:(SRLconst [c] y)) && ssa.ClobberIfDead(x1) => (TSTshiftRL x0 y [c])
1499 (TST x0 x1:(SRAconst [c] y)) && ssa.ClobberIfDead(x1) => (TSTshiftRA x0 y [c])
1500 (TST x0 x1:(RORconst [c] y)) && ssa.ClobberIfDead(x1) => (TSTshiftRO x0 y [c])
1501
1502 // prefer *const ops to *shift ops
1503 (ADDshiftLL (MOVDconst [c]) x [d]) => (ADDconst [c] (SLLconst <x.Type> x [d]))
1504 (ADDshiftRL (MOVDconst [c]) x [d]) => (ADDconst [c] (SRLconst <x.Type> x [d]))
1505 (ADDshiftRA (MOVDconst [c]) x [d]) => (ADDconst [c] (SRAconst <x.Type> x [d]))
1506 (ANDshiftLL (MOVDconst [c]) x [d]) => (ANDconst [c] (SLLconst <x.Type> x [d]))
1507 (ANDshiftRL (MOVDconst [c]) x [d]) => (ANDconst [c] (SRLconst <x.Type> x [d]))
1508 (ANDshiftRA (MOVDconst [c]) x [d]) => (ANDconst [c] (SRAconst <x.Type> x [d]))
1509 (ANDshiftRO (MOVDconst [c]) x [d]) => (ANDconst [c] (RORconst <x.Type> x [d]))
1510 (ORshiftLL (MOVDconst [c]) x [d]) => (ORconst [c] (SLLconst <x.Type> x [d]))
1511 (ORshiftRL (MOVDconst [c]) x [d]) => (ORconst [c] (SRLconst <x.Type> x [d]))
1512 (ORshiftRA (MOVDconst [c]) x [d]) => (ORconst [c] (SRAconst <x.Type> x [d]))
1513 (ORshiftRO (MOVDconst [c]) x [d]) => (ORconst [c] (RORconst <x.Type> x [d]))
1514 (XORshiftLL (MOVDconst [c]) x [d]) => (XORconst [c] (SLLconst <x.Type> x [d]))
1515 (XORshiftRL (MOVDconst [c]) x [d]) => (XORconst [c] (SRLconst <x.Type> x [d]))
1516 (XORshiftRA (MOVDconst [c]) x [d]) => (XORconst [c] (SRAconst <x.Type> x [d]))
1517 (XORshiftRO (MOVDconst [c]) x [d]) => (XORconst [c] (RORconst <x.Type> x [d]))
1518 (CMPshiftLL (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SLLconst <x.Type> x [d])))
1519 (CMPshiftRL (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SRLconst <x.Type> x [d])))
1520 (CMPshiftRA (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SRAconst <x.Type> x [d])))
1521 (CMNshiftLL (MOVDconst [c]) x [d]) => (CMNconst [c] (SLLconst <x.Type> x [d]))
1522 (CMNshiftRL (MOVDconst [c]) x [d]) => (CMNconst [c] (SRLconst <x.Type> x [d]))
1523 (CMNshiftRA (MOVDconst [c]) x [d]) => (CMNconst [c] (SRAconst <x.Type> x [d]))
1524 (TSTshiftLL (MOVDconst [c]) x [d]) => (TSTconst [c] (SLLconst <x.Type> x [d]))
1525 (TSTshiftRL (MOVDconst [c]) x [d]) => (TSTconst [c] (SRLconst <x.Type> x [d]))
1526 (TSTshiftRA (MOVDconst [c]) x [d]) => (TSTconst [c] (SRAconst <x.Type> x [d]))
1527 (TSTshiftRO (MOVDconst [c]) x [d]) => (TSTconst [c] (RORconst <x.Type> x [d]))
1528
1529 // constant folding in *shift ops
1530 (MVNshiftLL (MOVDconst [c]) [d]) => (MOVDconst [^int64(uint64(c)<<uint64(d))])
1531 (MVNshiftRL (MOVDconst [c]) [d]) => (MOVDconst [^int64(uint64(c)>>uint64(d))])
1532 (MVNshiftRA (MOVDconst [c]) [d]) => (MOVDconst [^(c>>uint64(d))])
1533 (MVNshiftRO (MOVDconst [c]) [d]) => (MOVDconst [^rotateRight64(c, d)])
1534 (NEGshiftLL (MOVDconst [c]) [d]) => (MOVDconst [-int64(uint64(c)<<uint64(d))])
1535 (NEGshiftRL (MOVDconst [c]) [d]) => (MOVDconst [-int64(uint64(c)>>uint64(d))])
1536 (NEGshiftRA (MOVDconst [c]) [d]) => (MOVDconst [-(c>>uint64(d))])
1537 (ADDshiftLL x (MOVDconst [c]) [d]) => (ADDconst x [int64(uint64(c)<<uint64(d))])
1538 (ADDshiftRL x (MOVDconst [c]) [d]) => (ADDconst x [int64(uint64(c)>>uint64(d))])
1539 (ADDshiftRA x (MOVDconst [c]) [d]) => (ADDconst x [c>>uint64(d)])
1540 (SUBshiftLL x (MOVDconst [c]) [d]) => (SUBconst x [int64(uint64(c)<<uint64(d))])
1541 (SUBshiftRL x (MOVDconst [c]) [d]) => (SUBconst x [int64(uint64(c)>>uint64(d))])
1542 (SUBshiftRA x (MOVDconst [c]) [d]) => (SUBconst x [c>>uint64(d)])
1543 (ANDshiftLL x (MOVDconst [c]) [d]) => (ANDconst x [int64(uint64(c)<<uint64(d))])
1544 (ANDshiftRL x (MOVDconst [c]) [d]) => (ANDconst x [int64(uint64(c)>>uint64(d))])
1545 (ANDshiftRA x (MOVDconst [c]) [d]) => (ANDconst x [c>>uint64(d)])
1546 (ANDshiftRO x (MOVDconst [c]) [d]) => (ANDconst x [rotateRight64(c, d)])
1547 (ORshiftLL x (MOVDconst [c]) [d]) => (ORconst x [int64(uint64(c)<<uint64(d))])
1548 (ORshiftRL x (MOVDconst [c]) [d]) => (ORconst x [int64(uint64(c)>>uint64(d))])
1549 (ORshiftRA x (MOVDconst [c]) [d]) => (ORconst x [c>>uint64(d)])
1550 (ORshiftRO x (MOVDconst [c]) [d]) => (ORconst x [rotateRight64(c, d)])
1551 (XORshiftLL x (MOVDconst [c]) [d]) => (XORconst x [int64(uint64(c)<<uint64(d))])
1552 (XORshiftRL x (MOVDconst [c]) [d]) => (XORconst x [int64(uint64(c)>>uint64(d))])
1553 (XORshiftRA x (MOVDconst [c]) [d]) => (XORconst x [c>>uint64(d)])
1554 (XORshiftRO x (MOVDconst [c]) [d]) => (XORconst x [rotateRight64(c, d)])
1555 (BICshiftLL x (MOVDconst [c]) [d]) => (ANDconst x [^int64(uint64(c)<<uint64(d))])
1556 (BICshiftRL x (MOVDconst [c]) [d]) => (ANDconst x [^int64(uint64(c)>>uint64(d))])
1557 (BICshiftRA x (MOVDconst [c]) [d]) => (ANDconst x [^(c>>uint64(d))])
1558 (BICshiftRO x (MOVDconst [c]) [d]) => (ANDconst x [^rotateRight64(c, d)])
1559 (ORNshiftLL x (MOVDconst [c]) [d]) => (ORconst x [^int64(uint64(c)<<uint64(d))])
1560 (ORNshiftRL x (MOVDconst [c]) [d]) => (ORconst x [^int64(uint64(c)>>uint64(d))])
1561 (ORNshiftRA x (MOVDconst [c]) [d]) => (ORconst x [^(c>>uint64(d))])
1562 (ORNshiftRO x (MOVDconst [c]) [d]) => (ORconst x [^rotateRight64(c, d)])
1563 (EONshiftLL x (MOVDconst [c]) [d]) => (XORconst x [^int64(uint64(c)<<uint64(d))])
1564 (EONshiftRL x (MOVDconst [c]) [d]) => (XORconst x [^int64(uint64(c)>>uint64(d))])
1565 (EONshiftRA x (MOVDconst [c]) [d]) => (XORconst x [^(c>>uint64(d))])
1566 (EONshiftRO x (MOVDconst [c]) [d]) => (XORconst x [^rotateRight64(c, d)])
1567 (CMPshiftLL x (MOVDconst [c]) [d]) => (CMPconst x [int64(uint64(c)<<uint64(d))])
1568 (CMPshiftRL x (MOVDconst [c]) [d]) => (CMPconst x [int64(uint64(c)>>uint64(d))])
1569 (CMPshiftRA x (MOVDconst [c]) [d]) => (CMPconst x [c>>uint64(d)])
1570 (CMNshiftLL x (MOVDconst [c]) [d]) => (CMNconst x [int64(uint64(c)<<uint64(d))])
1571 (CMNshiftRL x (MOVDconst [c]) [d]) => (CMNconst x [int64(uint64(c)>>uint64(d))])
1572 (CMNshiftRA x (MOVDconst [c]) [d]) => (CMNconst x [c>>uint64(d)])
1573 (TSTshiftLL x (MOVDconst [c]) [d]) => (TSTconst x [int64(uint64(c)<<uint64(d))])
1574 (TSTshiftRL x (MOVDconst [c]) [d]) => (TSTconst x [int64(uint64(c)>>uint64(d))])
1575 (TSTshiftRA x (MOVDconst [c]) [d]) => (TSTconst x [c>>uint64(d)])
1576 (TSTshiftRO x (MOVDconst [c]) [d]) => (TSTconst x [rotateRight64(c, d)])
1577
1578 // simplification with *shift ops
1579 (SUBshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0])
1580 (SUBshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0])
1581 (SUBshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0])
1582 (ANDshiftLL y:(SLLconst x [c]) x [c]) => y
1583 (ANDshiftRL y:(SRLconst x [c]) x [c]) => y
1584 (ANDshiftRA y:(SRAconst x [c]) x [c]) => y
1585 (ANDshiftRO y:(RORconst x [c]) x [c]) => y
1586 (ORshiftLL y:(SLLconst x [c]) x [c]) => y
1587 (ORshiftRL y:(SRLconst x [c]) x [c]) => y
1588 (ORshiftRA y:(SRAconst x [c]) x [c]) => y
1589 (ORshiftRO y:(RORconst x [c]) x [c]) => y
1590 (XORshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0])
1591 (XORshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0])
1592 (XORshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0])
1593 (XORshiftRO (RORconst x [c]) x [c]) => (MOVDconst [0])
1594 (BICshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0])
1595 (BICshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0])
1596 (BICshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0])
1597 (BICshiftRO (RORconst x [c]) x [c]) => (MOVDconst [0])
1598 (EONshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [-1])
1599 (EONshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [-1])
1600 (EONshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [-1])
1601 (EONshiftRO (RORconst x [c]) x [c]) => (MOVDconst [-1])
1602 (ORNshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [-1])
1603 (ORNshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [-1])
1604 (ORNshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [-1])
1605 (ORNshiftRO (RORconst x [c]) x [c]) => (MOVDconst [-1])
1606
1607 // rev16w | rev16
1608 // ((x>>8) | (x<<8)) => (REV16W x), the type of x is uint16, "|" can also be "^" or "+".
1609 ((ADDshiftLL|ORshiftLL|XORshiftLL) <typ.UInt16> [8] (UBFX <typ.UInt16> [ssa.ArmBFAuxInt(8, 8)] x) x) => (REV16W x)
1610
1611 // ((x & 0xff00ff00)>>8) | ((x & 0x00ff00ff)<<8), "|" can also be "^" or "+".
1612 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (UBFX [ssa.ArmBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x))
1613 && uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff
1614 => (REV16W x)
1615
1616 // ((x & 0xff00ff00ff00ff00)>>8) | ((x & 0x00ff00ff00ff00ff)<<8), "|" can also be "^" or "+".
1617 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x))
1618 && (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff)
1619 => (REV16 x)
1620
1621 // ((x & 0xff00ff00)>>8) | ((x & 0x00ff00ff)<<8), "|" can also be "^" or "+".
1622 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x))
1623 && (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff)
1624 => (REV16 (ANDconst <x.Type> [0xffffffff] x))
1625
1626 (REV16 (MOVWUreg x)) => (REV16W x)
1627
1628 // Extract from reg pair
1629 (ADDshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x)
1630 ( ORshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x)
1631 (XORshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x)
1632
1633 (ADDshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == ssa.ArmBFAuxInt(32-c, c)
1634 => (EXTRWconst [32-c] x2 x)
1635 ( ORshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == ssa.ArmBFAuxInt(32-c, c)
1636 => (EXTRWconst [32-c] x2 x)
1637 (XORshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == ssa.ArmBFAuxInt(32-c, c)
1638 => (EXTRWconst [32-c] x2 x)
1639
1640 // Rewrite special pairs of shifts to AND.
1641 // On ARM64 the bitmask can fit into an instruction.
1642 (SRLconst [c] (SLLconst [c] x)) && 0 < c && c < 64 => (ANDconst [1<<uint(64-c)-1] x) // mask out high bits
1643 (SLLconst [c] (SRLconst [c] x)) && 0 < c && c < 64 => (ANDconst [^(1<<uint(c)-1)] x) // mask out low bits
1644
1645 // Special case setting bit as 1. An example is math.Copysign(c,-1)
1646 (ORconst [c1] (ANDconst [c2] x)) && c2|c1 == ^0 => (ORconst [c1] x)
1647
1648 // If the shift amount is larger than the datasize(32, 16, 8), we can optimize to constant 0.
1649 (MOVWUreg (SLLconst [lc] x)) && lc >= 32 => (MOVDconst [0])
1650 (MOVHUreg (SLLconst [lc] x)) && lc >= 16 => (MOVDconst [0])
1651 (MOVBUreg (SLLconst [lc] x)) && lc >= 8 => (MOVDconst [0])
1652
1653 // After zero extension, the upper (64-datasize(32|16|8)) bits are zero, we can optimiza to constant 0.
1654 (SRLconst [rc] (MOVWUreg x)) && rc >= 32 => (MOVDconst [0])
1655 (SRLconst [rc] (MOVHUreg x)) && rc >= 16 => (MOVDconst [0])
1656 (SRLconst [rc] (MOVBUreg x)) && rc >= 8 => (MOVDconst [0])
1657
1658 // Special cases for slice operations
1659 (ADD x0 x1:(ANDshiftRA x2:(SLLconst [sl] y) z [63])) && x1.Uses == 1 && x2.Uses == 1 => (ADDshiftLL x0 (ANDshiftRA <y.Type> y z [63]) [sl])
1660 (ADD x0 x1:(ANDshiftLL x2:(SRAconst [63] z) y [sl])) && x1.Uses == 1 && x2.Uses == 1 => (ADDshiftLL x0 (ANDshiftRA <y.Type> y z [63]) [sl])
1661
1662 // bitfield ops
1663
1664 // sbfiz
1665 // (x << lc) >> rc
1666 (SRAconst [rc] (SLLconst [lc] x)) && lc > rc => (SBFIZ [ssa.ArmBFAuxInt(lc-rc, 64-lc)] x)
1667 // int64(x << lc)
1668 (MOVWreg (SLLconst [lc] x)) && lc < 32 => (SBFIZ [ssa.ArmBFAuxInt(lc, 32-lc)] x)
1669 (MOVHreg (SLLconst [lc] x)) && lc < 16 => (SBFIZ [ssa.ArmBFAuxInt(lc, 16-lc)] x)
1670 (MOVBreg (SLLconst [lc] x)) && lc < 8 => (SBFIZ [ssa.ArmBFAuxInt(lc, 8-lc)] x)
1671 // int64(x) << lc
1672 (SLLconst [lc] (MOVWreg x)) => (SBFIZ [ssa.ArmBFAuxInt(lc, min(32, 64-lc))] x)
1673 (SLLconst [lc] (MOVHreg x)) => (SBFIZ [ssa.ArmBFAuxInt(lc, min(16, 64-lc))] x)
1674 (SLLconst [lc] (MOVBreg x)) => (SBFIZ [ssa.ArmBFAuxInt(lc, min(8, 64-lc))] x)
1675
1676 // sbfx
1677 // (x << lc) >> rc
1678 (SRAconst [rc] (SLLconst [lc] x)) && lc <= rc => (SBFX [ssa.ArmBFAuxInt(rc-lc, 64-rc)] x)
1679 // int64(x) >> rc
1680 (SRAconst [rc] (MOVWreg x)) && rc < 32 => (SBFX [ssa.ArmBFAuxInt(rc, 32-rc)] x)
1681 (SRAconst [rc] (MOVHreg x)) && rc < 16 => (SBFX [ssa.ArmBFAuxInt(rc, 16-rc)] x)
1682 (SRAconst [rc] (MOVBreg x)) && rc < 8 => (SBFX [ssa.ArmBFAuxInt(rc, 8-rc)] x)
1683 // merge sbfx and sign-extension into sbfx
1684 (MOVWreg (SBFX [bfc] x)) && bfc.Width() <= 32 => (SBFX [bfc] x)
1685 (MOVHreg (SBFX [bfc] x)) && bfc.Width() <= 16 => (SBFX [bfc] x)
1686 (MOVBreg (SBFX [bfc] x)) && bfc.Width() <= 8 => (SBFX [bfc] x)
1687
1688 // sbfiz/sbfx combinations: merge shifts into bitfield ops
1689 (SRAconst [sc] (SBFIZ [bfc] x)) && sc < bfc.Lsb()
1690 => (SBFIZ [ssa.ArmBFAuxInt(bfc.Lsb()-sc, bfc.Width())] x)
1691 (SRAconst [sc] (SBFIZ [bfc] x)) && sc >= bfc.Lsb()
1692 && sc < bfc.Lsb()+bfc.Width()
1693 => (SBFX [ssa.ArmBFAuxInt(sc-bfc.Lsb(), bfc.Lsb()+bfc.Width()-sc)] x)
1694 (SBFX [bfc] s:(SLLconst [sc] x))
1695 && s.Uses == 1
1696 && sc <= bfc.Lsb()
1697 => (SBFX [ssa.ArmBFAuxInt(bfc.Lsb() - sc, bfc.Width())] x)
1698 (SBFX [bfc] s:(SLLconst [sc] x))
1699 && s.Uses == 1
1700 && sc > bfc.Lsb()
1701 && sc < bfc.Lsb()+bfc.Width()
1702 => (SBFIZ [ssa.ArmBFAuxInt(sc - bfc.Lsb(), bfc.Width() - (sc-bfc.Lsb()))] x)
1703
1704 // ubfiz
1705 // (x << lc) >> rc
1706 (SRLconst [rc] (SLLconst [lc] x)) && lc > rc => (UBFIZ [ssa.ArmBFAuxInt(lc-rc, 64-lc)] x)
1707 // uint64(x) << lc
1708 (SLLconst [lc] (MOVWUreg x)) => (UBFIZ [ssa.ArmBFAuxInt(lc, min(32, 64-lc))] x)
1709 (SLLconst [lc] (MOVHUreg x)) => (UBFIZ [ssa.ArmBFAuxInt(lc, min(16, 64-lc))] x)
1710 (SLLconst [lc] (MOVBUreg x)) => (UBFIZ [ssa.ArmBFAuxInt(lc, min(8, 64-lc))] x)
1711 // uint64(x << lc)
1712 (MOVWUreg (SLLconst [lc] x)) && lc < 32 => (UBFIZ [ssa.ArmBFAuxInt(lc, 32-lc)] x)
1713 (MOVHUreg (SLLconst [lc] x)) && lc < 16 => (UBFIZ [ssa.ArmBFAuxInt(lc, 16-lc)] x)
1714 (MOVBUreg (SLLconst [lc] x)) && lc < 8 => (UBFIZ [ssa.ArmBFAuxInt(lc, 8-lc)] x)
1715
1716 // merge ANDconst into ubfiz
1717 // (x & ac) << sc
1718 (SLLconst [sc] (ANDconst [ac] x)) && isARM64BFMask(sc, ac, 0)
1719 => (UBFIZ [ssa.ArmBFAuxInt(sc, arm64BFWidth(ac, 0))] x)
1720 // (x << sc) & ac
1721 (ANDconst [ac] (SLLconst [sc] x)) && isARM64BFMask(sc, ac, sc)
1722 => (UBFIZ [ssa.ArmBFAuxInt(sc, arm64BFWidth(ac, sc))] x)
1723
1724 // ubfx
1725 // (x << lc) >> rc
1726 (SRLconst [rc] (SLLconst [lc] x)) && lc < rc => (UBFX [ssa.ArmBFAuxInt(rc-lc, 64-rc)] x)
1727 // uint64(x) >> rc
1728 (SRLconst [rc] (MOVWUreg x)) && rc < 32 => (UBFX [ssa.ArmBFAuxInt(rc, 32-rc)] x)
1729 (SRLconst [rc] (MOVHUreg x)) && rc < 16 => (UBFX [ssa.ArmBFAuxInt(rc, 16-rc)] x)
1730 (SRLconst [rc] (MOVBUreg x)) && rc < 8 => (UBFX [ssa.ArmBFAuxInt(rc, 8-rc)] x)
1731 // uint64(x >> rc)
1732 (MOVWUreg (SRLconst [rc] x)) && rc < 32 => (UBFX [ssa.ArmBFAuxInt(rc, 32)] x)
1733 (MOVHUreg (SRLconst [rc] x)) && rc < 16 => (UBFX [ssa.ArmBFAuxInt(rc, 16)] x)
1734 (MOVBUreg (SRLconst [rc] x)) && rc < 8 => (UBFX [ssa.ArmBFAuxInt(rc, 8)] x)
1735 // merge ANDconst into ubfx
1736 // (x >> sc) & ac
1737 (ANDconst [ac] (SRLconst [sc] x)) && isARM64BFMask(sc, ac, 0)
1738 => (UBFX [ssa.ArmBFAuxInt(sc, arm64BFWidth(ac, 0))] x)
1739 // (x & ac) >> sc
1740 (SRLconst [sc] (ANDconst [ac] x)) && isARM64BFMask(sc, ac, sc)
1741 => (UBFX [ssa.ArmBFAuxInt(sc, arm64BFWidth(ac, sc))] x)
1742 // merge ANDconst and ubfx into ubfx
1743 (ANDconst [c] (UBFX [bfc] x)) && isARM64BFMask(0, c, 0) =>
1744 (UBFX [ssa.ArmBFAuxInt(bfc.Lsb(), min(bfc.Width(), arm64BFWidth(c, 0)))] x)
1745 (UBFX [bfc] (ANDconst [c] x)) && isARM64BFMask(0, c, 0) && bfc.Lsb() + bfc.Width() <= arm64BFWidth(c, 0) =>
1746 (UBFX [bfc] x)
1747 // merge ubfx and zero-extension into ubfx
1748 (MOVWUreg (UBFX [bfc] x)) && bfc.Width() <= 32 => (UBFX [bfc] x)
1749 (MOVHUreg (UBFX [bfc] x)) && bfc.Width() <= 16 => (UBFX [bfc] x)
1750 (MOVBUreg (UBFX [bfc] x)) && bfc.Width() <= 8 => (UBFX [bfc] x)
1751
1752 // Extracting bits from across a zero-extension boundary.
1753 (UBFX [bfc] e:(MOVWUreg x))
1754 && e.Uses == 1
1755 && bfc.Lsb() < 32
1756 => (UBFX [ssa.ArmBFAuxInt(bfc.Lsb(), min(bfc.Width(), 32-bfc.Lsb()))] x)
1757 (UBFX [bfc] e:(MOVHUreg x))
1758 && e.Uses == 1
1759 && bfc.Lsb() < 16
1760 => (UBFX [ssa.ArmBFAuxInt(bfc.Lsb(), min(bfc.Width(), 16-bfc.Lsb()))] x)
1761 (UBFX [bfc] e:(MOVBUreg x))
1762 && e.Uses == 1
1763 && bfc.Lsb() < 8
1764 => (UBFX [ssa.ArmBFAuxInt(bfc.Lsb(), min(bfc.Width(), 8-bfc.Lsb()))] x)
1765
1766 // ubfiz/ubfx combinations: merge shifts into bitfield ops
1767 (SRLconst [sc] (UBFX [bfc] x)) && sc < bfc.Width()
1768 => (UBFX [ssa.ArmBFAuxInt(bfc.Lsb()+sc, bfc.Width()-sc)] x)
1769 (UBFX [bfc] (SRLconst [sc] x)) && sc+bfc.Width()+bfc.Lsb() < 64
1770 => (UBFX [ssa.ArmBFAuxInt(bfc.Lsb()+sc, bfc.Width())] x)
1771 (SLLconst [sc] (UBFIZ [bfc] x)) && sc+bfc.Width()+bfc.Lsb() < 64
1772 => (UBFIZ [ssa.ArmBFAuxInt(bfc.Lsb()+sc, bfc.Width())] x)
1773 (UBFIZ [bfc] (SLLconst [sc] x)) && sc < bfc.Width()
1774 => (UBFIZ [ssa.ArmBFAuxInt(bfc.Lsb()+sc, bfc.Width()-sc)] x)
1775 // ((x << c1) >> c2) >> c3
1776 (SRLconst [sc] (UBFIZ [bfc] x)) && sc == bfc.Lsb()
1777 => (ANDconst [1<<uint(bfc.Width())-1] x)
1778 (SRLconst [sc] (UBFIZ [bfc] x)) && sc < bfc.Lsb()
1779 => (UBFIZ [ssa.ArmBFAuxInt(bfc.Lsb()-sc, bfc.Width())] x)
1780 (SRLconst [sc] (UBFIZ [bfc] x)) && sc > bfc.Lsb()
1781 && sc < bfc.Lsb()+bfc.Width()
1782 => (UBFX [ssa.ArmBFAuxInt(sc-bfc.Lsb(), bfc.Lsb()+bfc.Width()-sc)] x)
1783 // ((x << c1) << c2) >> c3
1784 (UBFX [bfc] (SLLconst [sc] x)) && sc == bfc.Lsb()
1785 => (ANDconst [1<<uint(bfc.Width())-1] x)
1786 (UBFX [bfc] (SLLconst [sc] x)) && sc < bfc.Lsb()
1787 => (UBFX [ssa.ArmBFAuxInt(bfc.Lsb()-sc, bfc.Width())] x)
1788 (UBFX [bfc] (SLLconst [sc] x)) && sc > bfc.Lsb()
1789 && sc < bfc.Lsb()+bfc.Width()
1790 => (UBFIZ [ssa.ArmBFAuxInt(sc-bfc.Lsb(), bfc.Lsb()+bfc.Width()-sc)] x)
1791
1792 // bfi
1793 (OR (UBFIZ [bfc] x) (ANDconst [ac] y))
1794 && ac == ^((1<<uint(bfc.Width())-1) << uint(bfc.Lsb()))
1795 => (BFI [bfc] y x)
1796 (ORshiftLL [s] (ANDconst [xc] x) (ANDconst [yc] y))
1797 && xc == ^(yc << s) // opposite masks
1798 && yc & (yc+1) == 0 // power of 2 minus 1
1799 && yc > 0 // not 0, not all 64 bits (there are better rewrites in that case)
1800 && s+ssa.Log64(yc+1) <= 64 // shifted mask doesn't overflow
1801 => (BFI [ssa.ArmBFAuxInt(s, ssa.Log64(yc+1))] x y)
1802 (ORshiftRL [rc] (ANDconst [ac] x) (SLLconst [lc] y))
1803 && lc > rc && ac == ^((1<<uint(64-lc)-1) << uint64(lc-rc))
1804 => (BFI [ssa.ArmBFAuxInt(lc-rc, 64-lc)] x y)
1805 // bfxil
1806 (OR (UBFX [bfc] x) (ANDconst [ac] y)) && ac == ^(1<<uint(bfc.Width())-1)
1807 => (BFXIL [bfc] y x)
1808 (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) && sc == bfc.Width()
1809 => (BFXIL [bfc] y x)
1810 (ORshiftRL [rc] (ANDconst [ac] y) (SLLconst [lc] x)) && lc < rc && ac == ^((1<<uint(64-rc)-1))
1811 => (BFXIL [ssa.ArmBFAuxInt(rc-lc, 64-rc)] y x)
1812
1813 // FP simplification
1814 (FNEGS (FMULS x y)) => (FNMULS x y)
1815 (FNEGD (FMULD x y)) => (FNMULD x y)
1816 (FMULS (FNEGS x) y) => (FNMULS x y)
1817 (FMULD (FNEGD x) y) => (FNMULD x y)
1818 (FNEGS (FNMULS x y)) => (FMULS x y)
1819 (FNEGD (FNMULD x y)) => (FMULD x y)
1820 (FNMULS (FNEGS x) y) => (FMULS x y)
1821 (FNMULD (FNEGD x) y) => (FMULD x y)
1822
1823 (FADDS a (FMULS x y)) && a.Block.Func.UseFMA(v) => (FMADDS a x y)
1824 (FADDD a (FMULD x y)) && a.Block.Func.UseFMA(v) => (FMADDD a x y)
1825 (FSUBS a (FMULS x y)) && a.Block.Func.UseFMA(v) => (FMSUBS a x y)
1826 (FSUBD a (FMULD x y)) && a.Block.Func.UseFMA(v) => (FMSUBD a x y)
1827 (FSUBS (FMULS x y) a) && a.Block.Func.UseFMA(v) => (FNMSUBS a x y)
1828 (FSUBD (FMULD x y) a) && a.Block.Func.UseFMA(v) => (FNMSUBD a x y)
1829 (FADDS a (FNMULS x y)) && a.Block.Func.UseFMA(v) => (FMSUBS a x y)
1830 (FADDD a (FNMULD x y)) && a.Block.Func.UseFMA(v) => (FMSUBD a x y)
1831 (FSUBS a (FNMULS x y)) && a.Block.Func.UseFMA(v) => (FMADDS a x y)
1832 (FSUBD a (FNMULD x y)) && a.Block.Func.UseFMA(v) => (FMADDD a x y)
1833 (FSUBS (FNMULS x y) a) && a.Block.Func.UseFMA(v) => (FNMADDS a x y)
1834 (FSUBD (FNMULD x y) a) && a.Block.Func.UseFMA(v) => (FNMADDD a x y)
1835
1836 (MOVBUload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVDconst [int64(ssa.Read8(sym, int64(off)))])
1837 (MOVHUload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVDconst [int64(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
1838 (MOVWUload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVDconst [int64(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
1839 (MOVDload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVDconst [int64(ssa.Read64(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
1840 (MOVBload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVDconst [int64(int8(ssa.Read8(sym, int64(off))))])
1841 (MOVHload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVDconst [int64(int16(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
1842 (MOVWload [off] {sym} (SB) _) && ssa.SymIsRO(sym) => (MOVDconst [int64(int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
1843
1844 // Prefetch instructions (aux is option: 0 - PLDL1KEEP; 1 - PLDL1STRM)
1845 (PrefetchCache addr mem) => (PRFM [0] addr mem)
1846 (PrefetchCacheStreamed addr mem) => (PRFM [1] addr mem)
1847
1848 // Arch-specific inlining for small or disjoint runtime.memmove
1849 (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem)))))
1850 && sz >= 0
1851 && ssa.IsSameCall(sym, "runtime.memmove")
1852 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
1853 && ssa.IsInlinableMemmove(dst, src, sz, config)
1854 && ssa.Clobber(s1, s2, s3, call)
1855 => (Move [sz] dst src mem)
1856
1857 // Match post-lowering calls, register version.
1858 (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem))
1859 && sz >= 0
1860 && ssa.IsSameCall(sym, "runtime.memmove")
1861 && call.Uses == 1
1862 && ssa.IsInlinableMemmove(dst, src, sz, config)
1863 && ssa.Clobber(call)
1864 => (Move [sz] dst src mem)
1865
1866 ((REV|REVW) ((REV|REVW) p)) => p
1867
1868 // internal/runtime/math.MulUintptr intrinsics
1869
1870 (Select0 (Mul64uover x y)) => (MUL x y)
1871 (Select1 (Mul64uover x y)) => (NotEqual (CMPconst (UMULH <typ.UInt64> x y) [0]))
1872
1873 // 32 mul 32 -> 64
1874 (MUL r:(MOVWUreg x) s:(MOVWUreg y)) && r.Uses == 1 && s.Uses == 1 => (UMULL x y)
1875 (MUL r:(MOVWreg x) s:(MOVWreg y)) && r.Uses == 1 && s.Uses == 1 => (MULL x y)
1876
1877 // ANDconst to zext
1878 (ANDconst [0xffffffff] x) => (MOVWUreg x)
1879 (ANDconst [0xffff ] x) => (MOVHUreg x)
1880 (ANDconst [0xff ] x) => (MOVBUreg x)
1881
1882 // SIMD zero
1883 (ZeroSIMD <t>) && t.Size() == 16 => (VMOVI16B [0] <t>)
1884
1885 // Neon peephole
1886 (VEOR16B x x) => (VMOVI16B [0])
1887 (VNOT16B (VCMEQ16B (VAND16B x y) (VMOVI16B [0]))) => (VCMTST16B x y)
1888 (VNOT16B (VCMEQ8H (VAND16B x y) (VMOVI16B [0]))) => (VCMTST8H x y)
1889 (VNOT16B (VCMEQ4S (VAND16B x y) (VMOVI16B [0]))) => (VCMTST4S x y)
1890 (VNOT16B (VCMEQ2D (VAND16B x y) (VMOVI16B [0]))) => (VCMTST2D x y)
1891 (ZeroSIMD <t>) && t.Size() == 32 && t.IsSIMD() => (ZDUPBconst [0])
1892
1893 // SVE scalable-vector load/store and runtime vector length.
1894 (Load <t> ptr mem) && t.Size() == 32 && t.IsSIMD() => (ZLDRload ptr mem)
1895 (Store {t} ptr val mem) && t.Size() == 32 && t.IsSIMD() => (ZSTRstore ptr val mem)
1896 // SVE predicate (mask) load/store. A predicate is 8 bytes at the SSA level
1897 // (types.TypeMask); it cannot move to a GP/FP register, so masks that cross a
1898 // call or spill round-trip through memory via PLDR/PSTR.
1899 (ZeroSIMD <t>) && t.Size() == 8 && t.IsSIMD() => (PPFALSEB)
1900 (Load <t> ptr mem) && t.Size() == 8 && t.IsSIMD() => (PLDRload ptr mem)
1901 (Store {t} ptr val mem) && t.Size() == 8 && t.IsSIMD() => (PSTRstore ptr val mem)
1902 (ScalableVectorLen) => (RDVL [1])
1903
1904 // SVE byte-granular predicated scalable load/store (LoadTs/Store slice APIs).
1905 // These are written by hand until the predicated ops are generated by simdgen
1906 // in the mask CL; at that point delete them and generate instead.
1907 (Count8s r) => (Select0 <types.TypeMask> (PWHILELTB (MOVDconst [0]) r))
1908
1909 // SVE per-element select, backing IfElse and Masked.
1910 (IfElseInt8s x mask y) => (ZSELB x y mask)
1911 (IfElseUint8s x mask y) => (ZSELB x y mask)
1912 (IfElseInt16s x mask y) => (ZSELH x y mask)
1913 (IfElseUint16s x mask y) => (ZSELH x y mask)
1914 (IfElseInt32s x mask y) => (ZSELS x y mask)
1915 (IfElseUint32s x mask y) => (ZSELS x y mask)
1916 (IfElseFloat32s x mask y) => (ZSELS x y mask)
1917 (IfElseInt64s x mask y) => (ZSELD x y mask)
1918 (IfElseUint64s x mask y) => (ZSELD x y mask)
1919 (IfElseFloat64s x mask y) => (ZSELD x y mask)
1920
1921 // SVE scalar-to-vector broadcast. Integers come from a general register. A
1922 // float scalar is held in element 0 of the vector register that shares its
1923 // number, so a float broadcast is a broadcast of that element.
1924 (BroadcastInt8s ...) => (ZDUPB ...)
1925 (BroadcastUint8s ...) => (ZDUPB ...)
1926 (BroadcastInt16s ...) => (ZDUPH ...)
1927 (BroadcastUint16s ...) => (ZDUPH ...)
1928 (BroadcastInt32s ...) => (ZDUPS ...)
1929 (BroadcastUint32s ...) => (ZDUPS ...)
1930 (BroadcastInt64s ...) => (ZDUPD ...)
1931 (BroadcastUint64s ...) => (ZDUPD ...)
1932 (BroadcastFloat32s x) => (ZDUPIS [0] x)
1933 (BroadcastFloat64s x) => (ZDUPID [0] x)
1934
1935 // A broadcast of a small constant needs no general register: DUP (immediate)
1936 // takes a signed 8-bit immediate.
1937 (ZDUPB (MOVDconst [c])) && c == int64(int8(c)) => (ZDUPBconst [int8(c)])
1938 (ZDUPH (MOVDconst [c])) && c == int64(int8(c)) => (ZDUPHconst [int8(c)])
1939 (ZDUPS (MOVDconst [c])) && c == int64(int8(c)) => (ZDUPSconst [int8(c)])
1940 (ZDUPD (MOVDconst [c])) && c == int64(int8(c)) => (ZDUPDconst [int8(c)])
1941
1942 (LoadMasked8 <t> ptr mask mem) && t.Size() == 32 => (ZLD1BPredload ptr mask mem)
1943 (StoreMasked8 {t} ptr mask val mem) && t.Size() == 32 => (ZST1BPredstore ptr val mask mem)
1944
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