1 // Copyright 2016 The Go Authors. All rights reserved.
2 // Use of this source code is governed by a BSD-style
3 // license that can be found in the LICENSE file.
4
5 (Add(Ptr|64|32|16|8) ...) => (ADD ...)
6 (Add(32|64)F ...) => (FADD(S|D) ...)
7
8 (Sub(Ptr|64|32|16|8) ...) => (SUB ...)
9 (Sub(32|64)F ...) => (FSUB(S|D) ...)
10
11 (Mul64 ...) => (MUL ...)
12 (Mul(32|16|8) ...) => (MULW ...)
13 (Mul(32|64)F ...) => (FMUL(S|D) ...)
14
15 (Hmul64 ...) => (MULH ...)
16 (Hmul64u ...) => (UMULH ...)
17 (Hmul32 x y) => (SRAconst (MULL <typ.Int64> x y) [32])
18 (Hmul32u x y) => (SRAconst (UMULL <typ.UInt64> x y) [32])
19 (Select0 (Mul64uhilo x y)) => (UMULH x y)
20 (Select1 (Mul64uhilo x y)) => (MUL x y)
21
22 (Div64 [false] x y) => (DIV x y)
23 (Div32 [false] x y) => (DIVW x y)
24 (Div16 [false] x y) => (DIVW (SignExt16to32 x) (SignExt16to32 y))
25 (Div16u x y) => (UDIVW (ZeroExt16to32 x) (ZeroExt16to32 y))
26 (Div8 x y) => (DIVW (SignExt8to32 x) (SignExt8to32 y))
27 (Div8u x y) => (UDIVW (ZeroExt8to32 x) (ZeroExt8to32 y))
28 (Div64u ...) => (UDIV ...)
29 (Div32u ...) => (UDIVW ...)
30 (Div32F ...) => (FDIVS ...)
31 (Div64F ...) => (FDIVD ...)
32
33 (Mod64 x y) => (MOD x y)
34 (Mod32 x y) => (MODW x y)
35 (Mod64u ...) => (UMOD ...)
36 (Mod32u ...) => (UMODW ...)
37 (Mod(16|8) x y) => (MODW (SignExt(16|8)to32 x) (SignExt(16|8)to32 y))
38 (Mod(16|8)u x y) => (UMODW (ZeroExt(16|8)to32 x) (ZeroExt(16|8)to32 y))
39
40 // (x + y) / 2 with x>=y => (x - y) / 2 + y
41 (Avg64u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y)
42
43 (And(64|32|16|8) ...) => (AND ...)
44 (Or(64|32|16|8) ...) => (OR ...)
45 (Xor(64|32|16|8) ...) => (XOR ...)
46
47 // unary ops
48 (Neg(64|32|16|8) ...) => (NEG ...)
49 (Neg(32|64)F ...) => (FNEG(S|D) ...)
50 (Com(64|32|16|8) ...) => (MVN ...)
51
52 // math package intrinsics
53 (Abs ...) => (FABSD ...)
54 (Sqrt ...) => (FSQRTD ...)
55 (Ceil ...) => (FRINTPD ...)
56 (Floor ...) => (FRINTMD ...)
57 (Round ...) => (FRINTAD ...)
58 (RoundToEven ...) => (FRINTND ...)
59 (Trunc ...) => (FRINTZD ...)
60 (FMA x y z) => (FMADDD z x y)
61
62 (Sqrt32 ...) => (FSQRTS ...)
63
64 (Min(64|32)F ...) => (FMIN(D|S) ...)
65 (Max(64|32)F ...) => (FMAX(D|S) ...)
66
67 // lowering rotates
68 // we do rotate detection in generic rules, if the following rules need to be changed, check generic rules first.
69 (RotateLeft8 <t> x (MOVDconst [c])) => (Or8 (Lsh8x64 <t> x (MOVDconst [c&7])) (Rsh8Ux64 <t> x (MOVDconst [-c&7])))
70 (RotateLeft8 <t> x y) => (OR <t> (SLL <t> x (ANDconst <typ.Int64> [7] y)) (SRL <t> (ZeroExt8to64 x) (ANDconst <typ.Int64> [7] (NEG <typ.Int64> y))))
71 (RotateLeft16 <t> x (MOVDconst [c])) => (Or16 (Lsh16x64 <t> x (MOVDconst [c&15])) (Rsh16Ux64 <t> x (MOVDconst [-c&15])))
72 (RotateLeft16 <t> x y) => (RORW <t> (ORshiftLL <typ.UInt32> (ZeroExt16to32 x) (ZeroExt16to32 x) [16]) (NEG <typ.Int64> y))
73 (RotateLeft32 x y) => (RORW x (NEG <y.Type> y))
74 (RotateLeft64 x y) => (ROR x (NEG <y.Type> y))
75
76 (Ctz(64|32|16|8)NonZero ...) => (Ctz(64|32|32|32) ...)
77
78 (Ctz64 <t> x) => (CLZ (RBIT <t> x))
79 (Ctz32 <t> x) => (CLZW (RBITW <t> x))
80 (Ctz16 <t> x) => (CLZW <t> (RBITW <typ.UInt32> (ORconst <typ.UInt32> [0x10000] x)))
81 (Ctz8 <t> x) => (CLZW <t> (RBITW <typ.UInt32> (ORconst <typ.UInt32> [0x100] x)))
82
83 (PopCount64 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> x))))
84 (PopCount32 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt32to64 x)))))
85 (PopCount16 <t> x) => (FMOVDfpgp <t> (VUADDLV <typ.Float64> (VCNT <typ.Float64> (FMOVDgpfp <typ.Float64> (ZeroExt16to64 x)))))
86
87 // Load args directly into the register class where it will be used.
88 (FMOVDgpfp <t> (Arg [off] {sym})) => @b.Func.Entry (Arg <t> [off] {sym})
89 (FMOVDfpgp <t> (Arg [off] {sym})) => @b.Func.Entry (Arg <t> [off] {sym})
90
91 // Similarly for stores, if we see a store after FPR <=> GPR move, then redirect store to use the other register set.
92 (MOVDstore [off] {sym} ptr (FMOVDfpgp val) mem) => (FMOVDstore [off] {sym} ptr val mem)
93 (FMOVDstore [off] {sym} ptr (FMOVDgpfp val) mem) => (MOVDstore [off] {sym} ptr val mem)
94 (MOVWstore [off] {sym} ptr (FMOVSfpgp val) mem) => (FMOVSstore [off] {sym} ptr val mem)
95 (FMOVSstore [off] {sym} ptr (FMOVSgpfp val) mem) => (MOVWstore [off] {sym} ptr val mem)
96
97 // float <=> int register moves, with no conversion.
98 // These come up when compiling math.{Float64bits, Float64frombits, Float32bits, Float32frombits}.
99 (MOVDload [off] {sym} ptr (FMOVDstore [off] {sym} ptr val _)) => (FMOVDfpgp val)
100 (FMOVDload [off] {sym} ptr (MOVDstore [off] {sym} ptr val _)) => (FMOVDgpfp val)
101 (MOVWUload [off] {sym} ptr (FMOVSstore [off] {sym} ptr val _)) => (FMOVSfpgp val)
102 (FMOVSload [off] {sym} ptr (MOVWstore [off] {sym} ptr val _)) => (FMOVSgpfp val)
103
104 (BitLen64 x) => (SUB (MOVDconst [64]) (CLZ <typ.Int> x))
105 (BitLen32 x) => (SUB (MOVDconst [32]) (CLZW <typ.Int> x))
106 (BitLen(16|8) x) => (BitLen64 (ZeroExt(16|8)to64 x))
107
108 (Bswap64 ...) => (REV ...)
109 (Bswap32 ...) => (REVW ...)
110 (Bswap16 ...) => (REV16W ...)
111
112 (BitRev64 ...) => (RBIT ...)
113 (BitRev32 ...) => (RBITW ...)
114 (BitRev16 x) => (SRLconst [48] (RBIT <typ.UInt64> x))
115 (BitRev8 x) => (SRLconst [56] (RBIT <typ.UInt64> x))
116
117 // In fact, UMOD will be translated into UREM instruction, and UREM is originally translated into
118 // UDIV and MSUB instructions. But if there is already an identical UDIV instruction just before or
119 // after UREM (case like quo, rem := z/y, z%y), then the second UDIV instruction becomes redundant.
120 // The purpose of this rule is to have this extra UDIV instruction removed in CSE pass.
121 (UMOD <typ.UInt64> x y) => (MSUB <typ.UInt64> x y (UDIV <typ.UInt64> x y))
122 (UMODW <typ.UInt32> x y) => (MSUBW <typ.UInt32> x y (UDIVW <typ.UInt32> x y))
123
124 // 64-bit addition with carry.
125 (Select0 (Add64carry x y c)) => (Select0 <typ.UInt64> (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] c))))
126 (Select1 (Add64carry x y c)) => (ADCzerocarry <typ.UInt64> (Select1 <types.TypeFlags> (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] c)))))
127
128 // 64-bit subtraction with borrowing.
129 (Select0 (Sub64borrow x y bo)) => (Select0 <typ.UInt64> (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags bo))))
130 (Select1 (Sub64borrow x y bo)) => (NEG <typ.UInt64> (NGCzerocarry <typ.UInt64> (Select1 <types.TypeFlags> (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags bo))))))
131
132 // boolean ops -- booleans are represented with 0=false, 1=true
133 (AndB ...) => (AND ...)
134 (OrB ...) => (OR ...)
135 (EqB x y) => (XOR (MOVDconst [1]) (XOR <typ.Bool> x y))
136 (NeqB ...) => (XOR ...)
137 (Not x) => (XOR (MOVDconst [1]) x)
138
139 // shifts
140 // hardware instruction uses only the low 6 bits of the shift
141 // we compare to 64 to ensure Go semantics for large shifts
142 // Rules about rotates with non-const shift are based on the following rules,
143 // if the following rules change, please also modify the rules based on them.
144
145 // check shiftIsBounded first, if shift value is proved to be valid then we
146 // can do the shift directly.
147 // left shift
148 (Lsh32x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...)
149 (Lsh16x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...)
150 (Lsh8x(64|32|16|8) ...) => (Lsh64x(64|32|16|8) ...)
151
152 (Lsh64x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SLL <t> x y)
153
154 // signed right shift
155 (Rsh32x(64|32|16|8) <t> [bounded] x y) => (Rsh64x(64|32|16|8) <t> [bounded] (SignExt32to64 x) y)
156 (Rsh16x(64|32|16|8) <t> [bounded] x y) => (Rsh64x(64|32|16|8) <t> [bounded] (SignExt16to64 x) y)
157 (Rsh8x(64|32|16|8) <t> [bounded] x y) => (Rsh64x(64|32|16|8) <t> [bounded] (SignExt8to64 x) y)
158
159 (Rsh64x(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRA <t> x y)
160
161 // unsigned right shift
162 (Rsh32Ux(64|32|16|8) <t> [bounded] x y) => (Rsh64Ux(64|32|16|8) <t> [bounded] (ZeroExt32to64 x) y)
163 (Rsh16Ux(64|32|16|8) <t> [bounded] x y) => (Rsh64Ux(64|32|16|8) <t> [bounded] (ZeroExt16to64 x) y)
164 (Rsh8Ux(64|32|16|8) <t> [bounded] x y) => (Rsh64Ux(64|32|16|8) <t> [bounded] (ZeroExt8to64 x) y)
165
166 (Rsh64Ux(64|32|16|8) <t> x y) && shiftIsBounded(v) => (SRL <t> x y)
167
168 // shift value may be out of range, use CMP + CSEL instead
169 (Lsh64x64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPconst [64] y))
170 (Lsh64x32 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SLL <t> x y) (Const64 <t> [0]) (CMPWconst [64] y))
171 (Lsh64x(16|8) <t> [bounded] x y) && !shiftIsBounded(v) => (Lsh64x32 <t> [bounded] x (ZeroExt(16|8)to32 y))
172
173 (Rsh64Ux64 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> x y) (Const64 <t> [0]) (CMPconst [64] y))
174 (Rsh64Ux32 <t> x y) && !shiftIsBounded(v) => (CSEL [OpARM64LessThanU] (SRL <t> x y) (Const64 <t> [0]) (CMPWconst [64] y))
175 (Rsh64Ux(16|8) <t> [bounded] x y) && !shiftIsBounded(v) => (Rsh64Ux32 <t> [bounded] x (ZeroExt(16|8)to32 y))
176
177 (Rsh64x64 <t> x y) && !shiftIsBounded(v) => (SRA x (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPconst [64] y)))
178 (Rsh64x32 <t> x y) && !shiftIsBounded(v) => (SRA x (CSEL [OpARM64LessThanU] <y.Type> y (Const64 <y.Type> [63]) (CMPWconst [64] y)))
179 (Rsh64x(16|8) <t> [bounded] x y) && !shiftIsBounded(v) => (Rsh64x32 <t> [bounded] x (ZeroExt(16|8)to32 y))
180
181 // constants
182 (Const(64|32|16|8) [val]) => (MOVDconst [int64(val)])
183 (Const(32|64)F [val]) => (FMOV(S|D)const [float64(val)])
184 (ConstNil) => (MOVDconst [0])
185 (ConstBool [t]) => (MOVDconst [b2i(t)])
186
187 (Slicemask <t> x) => (SRAconst (NEG <t> x) [63])
188
189 // truncations
190 // Because we ignore high parts of registers, truncates are just copies.
191 (Trunc16to8 ...) => (Copy ...)
192 (Trunc32to8 ...) => (Copy ...)
193 (Trunc32to16 ...) => (Copy ...)
194 (Trunc64to8 ...) => (Copy ...)
195 (Trunc64to16 ...) => (Copy ...)
196 (Trunc64to32 ...) => (Copy ...)
197
198 // Zero-/Sign-extensions
199 (ZeroExt8to16 ...) => (MOVBUreg ...)
200 (ZeroExt8to32 ...) => (MOVBUreg ...)
201 (ZeroExt16to32 ...) => (MOVHUreg ...)
202 (ZeroExt8to64 ...) => (MOVBUreg ...)
203 (ZeroExt16to64 ...) => (MOVHUreg ...)
204 (ZeroExt32to64 ...) => (MOVWUreg ...)
205
206 (SignExt8to16 ...) => (MOVBreg ...)
207 (SignExt8to32 ...) => (MOVBreg ...)
208 (SignExt16to32 ...) => (MOVHreg ...)
209 (SignExt8to64 ...) => (MOVBreg ...)
210 (SignExt16to64 ...) => (MOVHreg ...)
211 (SignExt32to64 ...) => (MOVWreg ...)
212
213 // float <=> int conversion
214 (Cvt32to32F ...) => (SCVTFWS ...)
215 (Cvt32to64F ...) => (SCVTFWD ...)
216 (Cvt64to32F ...) => (SCVTFS ...)
217 (Cvt64to64F ...) => (SCVTFD ...)
218 (Cvt32Uto32F ...) => (UCVTFWS ...)
219 (Cvt32Uto64F ...) => (UCVTFWD ...)
220 (Cvt64Uto32F ...) => (UCVTFS ...)
221 (Cvt64Uto64F ...) => (UCVTFD ...)
222 (Cvt32Fto32 ...) => (FCVTZSSW ...)
223 (Cvt64Fto32 ...) => (FCVTZSDW ...)
224 (Cvt32Fto64 ...) => (FCVTZSS ...)
225 (Cvt64Fto64 ...) => (FCVTZSD ...)
226 (Cvt32Fto32U ...) => (FCVTZUSW ...)
227 (Cvt64Fto32U ...) => (FCVTZUDW ...)
228 (Cvt32Fto64U ...) => (FCVTZUS ...)
229 (Cvt64Fto64U ...) => (FCVTZUD ...)
230 (Cvt32Fto64F ...) => (FCVTSD ...)
231 (Cvt64Fto32F ...) => (FCVTDS ...)
232
233 (CvtBoolToUint8 ...) => (Copy ...)
234
235 (Round32F ...) => (LoweredRound32F ...)
236 (Round64F ...) => (LoweredRound64F ...)
237
238 // comparisons
239 (Eq8 x y) => (Equal (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
240 (Eq16 x y) => (Equal (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
241 (Eq32 x y) => (Equal (CMPW x y))
242 (Eq64 x y) => (Equal (CMP x y))
243 (EqPtr x y) => (Equal (CMP x y))
244 (Eq32F x y) => (Equal (FCMPS x y))
245 (Eq64F x y) => (Equal (FCMPD x y))
246
247 (Neq8 x y) => (NotEqual (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
248 (Neq16 x y) => (NotEqual (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
249 (Neq32 x y) => (NotEqual (CMPW x y))
250 (Neq64 x y) => (NotEqual (CMP x y))
251 (NeqPtr x y) => (NotEqual (CMP x y))
252 (Neq(32|64)F x y) => (NotEqual (FCMP(S|D) x y))
253
254 (Less(8|16) x y) => (LessThan (CMPW (SignExt(8|16)to32 x) (SignExt(8|16)to32 y)))
255 (Less32 x y) => (LessThan (CMPW x y))
256 (Less64 x y) => (LessThan (CMP x y))
257
258 // Set condition flags for floating-point comparisons "x < y"
259 // and "x <= y". Because if either or both of the operands are
260 // NaNs, all three of (x < y), (x == y) and (x > y) are false,
261 // and ARM Manual says FCMP instruction sets PSTATE.<N,Z,C,V>
262 // of this case to (0, 0, 1, 1).
263 (Less32F x y) => (LessThanF (FCMPS x y))
264 (Less64F x y) => (LessThanF (FCMPD x y))
265
266 // For an unsigned integer x, the following rules are useful when combining branch
267 // 0 < x => x != 0
268 // x <= 0 => x == 0
269 // x < 1 => x == 0
270 // 1 <= x => x != 0
271 (Less(8U|16U|32U|64U) zero:(MOVDconst [0]) x) => (Neq(8|16|32|64) zero x)
272 (Leq(8U|16U|32U|64U) x zero:(MOVDconst [0])) => (Eq(8|16|32|64) x zero)
273 (Less(8U|16U|32U|64U) x (MOVDconst [1])) => (Eq(8|16|32|64) x (MOVDconst [0]))
274 (Leq(8U|16U|32U|64U) (MOVDconst [1]) x) => (Neq(8|16|32|64) (MOVDconst [0]) x)
275
276 (Less8U x y) => (LessThanU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
277 (Less16U x y) => (LessThanU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
278 (Less32U x y) => (LessThanU (CMPW x y))
279 (Less64U x y) => (LessThanU (CMP x y))
280
281 (Leq8 x y) => (LessEqual (CMPW (SignExt8to32 x) (SignExt8to32 y)))
282 (Leq16 x y) => (LessEqual (CMPW (SignExt16to32 x) (SignExt16to32 y)))
283 (Leq32 x y) => (LessEqual (CMPW x y))
284 (Leq64 x y) => (LessEqual (CMP x y))
285
286 // Refer to the comments for op Less64F above.
287 (Leq32F x y) => (LessEqualF (FCMPS x y))
288 (Leq64F x y) => (LessEqualF (FCMPD x y))
289
290 (Leq8U x y) => (LessEqualU (CMPW (ZeroExt8to32 x) (ZeroExt8to32 y)))
291 (Leq16U x y) => (LessEqualU (CMPW (ZeroExt16to32 x) (ZeroExt16to32 y)))
292 (Leq32U x y) => (LessEqualU (CMPW x y))
293 (Leq64U x y) => (LessEqualU (CMP x y))
294
295 // Optimize comparison between a floating-point value and 0.0 with "FCMP $(0.0), Fn"
296 (FCMPS x (FMOVSconst [0])) => (FCMPS0 x)
297 (FCMPS (FMOVSconst [0]) x) => (InvertFlags (FCMPS0 x))
298 (FCMPD x (FMOVDconst [0])) => (FCMPD0 x)
299 (FCMPD (FMOVDconst [0]) x) => (InvertFlags (FCMPD0 x))
300
301 // CSEL needs a flag-generating argument. Synthesize a TSTW if necessary.
302 (CondSelect x y boolval) && flagArg(boolval) != nil => (CSEL [boolval.Op] x y flagArg(boolval))
303 (CondSelect x y boolval) && flagArg(boolval) == nil => (CSEL [OpARM64NotEqual] x y (TSTWconst [1] boolval))
304
305 (OffPtr [off] ptr:(SP)) && is32Bit(off) => (MOVDaddr [int32(off)] ptr)
306 (OffPtr [off] ptr) => (ADDconst [off] ptr)
307
308 (Addr {sym} base) => (MOVDaddr {sym} base)
309 (LocalAddr <t> {sym} base mem) && t.Elem().HasPointers() => (MOVDaddr {sym} (SPanchored base mem))
310 (LocalAddr <t> {sym} base _) && !t.Elem().HasPointers() => (MOVDaddr {sym} base)
311
312 // loads
313 (Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem)
314 (Load <t> ptr mem) && (is8BitInt(t) && t.IsSigned()) => (MOVBload ptr mem)
315 (Load <t> ptr mem) && (is8BitInt(t) && !t.IsSigned()) => (MOVBUload ptr mem)
316 (Load <t> ptr mem) && (is16BitInt(t) && t.IsSigned()) => (MOVHload ptr mem)
317 (Load <t> ptr mem) && (is16BitInt(t) && !t.IsSigned()) => (MOVHUload ptr mem)
318 (Load <t> ptr mem) && (is32BitInt(t) && t.IsSigned()) => (MOVWload ptr mem)
319 (Load <t> ptr mem) && (is32BitInt(t) && !t.IsSigned()) => (MOVWUload ptr mem)
320 (Load <t> ptr mem) && (is64BitInt(t) || isPtr(t)) => (MOVDload ptr mem)
321 (Load <t> ptr mem) && is32BitFloat(t) => (FMOVSload ptr mem)
322 (Load <t> ptr mem) && is64BitFloat(t) => (FMOVDload ptr mem)
323 (Load <t> ptr mem) && t.Size() == 16 => (FMOVQload ptr mem)
324
325 // stores
326 (Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem)
327 (Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem)
328 (Store {t} ptr val mem) && t.Size() == 4 && !t.IsFloat() => (MOVWstore ptr val mem)
329 (Store {t} ptr val mem) && t.Size() == 8 && !t.IsFloat() => (MOVDstore ptr val mem)
330 (Store {t} ptr val mem) && t.Size() == 4 && t.IsFloat() => (FMOVSstore ptr val mem)
331 (Store {t} ptr val mem) && t.Size() == 8 && t.IsFloat() => (FMOVDstore ptr val mem)
332 (Store {t} ptr val mem) && t.Size() == 16 => (FMOVQstore ptr val mem)
333
334 // zeroing
335 (Zero [0] _ mem) => mem
336 (Zero [1] ptr mem) => (MOVBstore ptr (MOVDconst [0]) mem)
337 (Zero [2] ptr mem) => (MOVHstore ptr (MOVDconst [0]) mem)
338 (Zero [4] ptr mem) => (MOVWstore ptr (MOVDconst [0]) mem)
339 (Zero [3] ptr mem) =>
340 (MOVBstore [2] ptr (MOVDconst [0])
341 (MOVHstore ptr (MOVDconst [0]) mem))
342 (Zero [5] ptr mem) =>
343 (MOVBstore [4] ptr (MOVDconst [0])
344 (MOVWstore ptr (MOVDconst [0]) mem))
345 (Zero [6] ptr mem) =>
346 (MOVHstore [4] ptr (MOVDconst [0])
347 (MOVWstore ptr (MOVDconst [0]) mem))
348 (Zero [7] ptr mem) =>
349 (MOVWstore [3] ptr (MOVDconst [0])
350 (MOVWstore ptr (MOVDconst [0]) mem))
351 (Zero [8] ptr mem) => (MOVDstore ptr (MOVDconst [0]) mem)
352 (Zero [9] ptr mem) =>
353 (MOVBstore [8] ptr (MOVDconst [0])
354 (MOVDstore ptr (MOVDconst [0]) mem))
355 (Zero [10] ptr mem) =>
356 (MOVHstore [8] ptr (MOVDconst [0])
357 (MOVDstore ptr (MOVDconst [0]) mem))
358 (Zero [11] ptr mem) =>
359 (MOVDstore [3] ptr (MOVDconst [0])
360 (MOVDstore ptr (MOVDconst [0]) mem))
361 (Zero [12] ptr mem) =>
362 (MOVWstore [8] ptr (MOVDconst [0])
363 (MOVDstore ptr (MOVDconst [0]) mem))
364 (Zero [13] ptr mem) =>
365 (MOVDstore [5] ptr (MOVDconst [0])
366 (MOVDstore ptr (MOVDconst [0]) mem))
367 (Zero [14] ptr mem) =>
368 (MOVDstore [6] ptr (MOVDconst [0])
369 (MOVDstore ptr (MOVDconst [0]) mem))
370 (Zero [15] ptr mem) =>
371 (MOVDstore [7] ptr (MOVDconst [0])
372 (MOVDstore ptr (MOVDconst [0]) mem))
373 (Zero [16] ptr mem) =>
374 (STP [0] ptr (MOVDconst [0]) (MOVDconst [0]) mem)
375
376 (Zero [s] ptr mem) && s > 16 && s < 192 => (LoweredZero [s] ptr mem)
377 (Zero [s] ptr mem) && s >= 192 => (LoweredZeroLoop [s] ptr mem)
378
379 // moves
380 (Move [0] _ _ mem) => mem
381 (Move [1] dst src mem) => (MOVBstore dst (MOVBUload src mem) mem)
382 (Move [2] dst src mem) => (MOVHstore dst (MOVHUload src mem) mem)
383 (Move [3] dst src mem) =>
384 (MOVBstore [2] dst (MOVBUload [2] src mem)
385 (MOVHstore dst (MOVHUload src mem) mem))
386 (Move [4] dst src mem) => (MOVWstore dst (MOVWUload src mem) mem)
387 (Move [5] dst src mem) =>
388 (MOVBstore [4] dst (MOVBUload [4] src mem)
389 (MOVWstore dst (MOVWUload src mem) mem))
390 (Move [6] dst src mem) =>
391 (MOVHstore [4] dst (MOVHUload [4] src mem)
392 (MOVWstore dst (MOVWUload src mem) mem))
393 (Move [7] dst src mem) =>
394 (MOVWstore [3] dst (MOVWUload [3] src mem)
395 (MOVWstore dst (MOVWUload src mem) mem))
396 (Move [8] dst src mem) => (MOVDstore dst (MOVDload src mem) mem)
397 (Move [9] dst src mem) =>
398 (MOVBstore [8] dst (MOVBUload [8] src mem)
399 (MOVDstore dst (MOVDload src mem) mem))
400 (Move [10] dst src mem) =>
401 (MOVHstore [8] dst (MOVHUload [8] src mem)
402 (MOVDstore dst (MOVDload src mem) mem))
403 (Move [11] dst src mem) =>
404 (MOVDstore [3] dst (MOVDload [3] src mem)
405 (MOVDstore dst (MOVDload src mem) mem))
406 (Move [12] dst src mem) =>
407 (MOVWstore [8] dst (MOVWUload [8] src mem)
408 (MOVDstore dst (MOVDload src mem) mem))
409 (Move [13] dst src mem) =>
410 (MOVDstore [5] dst (MOVDload [5] src mem)
411 (MOVDstore dst (MOVDload src mem) mem))
412 (Move [14] dst src mem) =>
413 (MOVDstore [6] dst (MOVDload [6] src mem)
414 (MOVDstore dst (MOVDload src mem) mem))
415 (Move [15] dst src mem) =>
416 (MOVDstore [7] dst (MOVDload [7] src mem)
417 (MOVDstore dst (MOVDload src mem) mem))
418 (Move [16] dst src mem) => (FMOVQstore dst (FMOVQload src mem) mem)
419
420 (Move [s] dst src mem) && s > 16 && s <= 24 =>
421 (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem)
422 (FMOVQstore dst (FMOVQload src mem) mem))
423 (Move [s] dst src mem) && s > 24 && s < 32 =>
424 (FMOVQstore [int32(s-16)] dst (FMOVQload [int32(s-16)] src mem)
425 (FMOVQstore dst (FMOVQload src mem) mem))
426 (Move [32] dst src mem) =>
427 (FSTPQ dst (Select0 <typ.Vec128> (FLDPQ src mem)) (Select1 <typ.Vec128> (FLDPQ src mem)) mem)
428 (Move [s] dst src mem) && s > 32 && s <= 40 =>
429 (MOVDstore [int32(s-8)] dst (MOVDload [int32(s-8)] src mem)
430 (FSTPQ dst (Select0 <typ.Vec128> (FLDPQ src mem)) (Select1 <typ.Vec128> (FLDPQ src mem)) mem))
431 (Move [s] dst src mem) && s > 40 && s <= 48 =>
432 (FMOVQstore [int32(s-16)] dst (FMOVQload [int32(s-16)] src mem)
433 (FSTPQ dst (Select0 <typ.Vec128> (FLDPQ src mem)) (Select1 <typ.Vec128> (FLDPQ src mem)) mem))
434 (Move [s] dst src mem) && s > 48 && s <= 64 =>
435 (FSTPQ [int32(s-32)] dst (Select0 <typ.Vec128> (FLDPQ [int32(s-32)] src mem)) (Select1 <typ.Vec128> (FLDPQ [int32(s-32)] src mem))
436 (FSTPQ dst (Select0 <typ.Vec128> (FLDPQ src mem)) (Select1 <typ.Vec128> (FLDPQ src mem)) mem))
437
438 (Move [s] dst src mem) && s > 64 && s < 192 && logLargeCopy(v, s) => (LoweredMove [s] dst src mem)
439 (Move [s] dst src mem) && s >= 192 && logLargeCopy(v, s) => (LoweredMoveLoop [s] dst src mem)
440
441 // calls
442 (StaticCall ...) => (CALLstatic ...)
443 (ClosureCall ...) => (CALLclosure ...)
444 (InterCall ...) => (CALLinter ...)
445 (TailCall ...) => (CALLtail ...)
446 (TailCallInter ...) => (CALLtailinter ...)
447
448 // checks
449 (NilCheck ...) => (LoweredNilCheck ...)
450 (IsNonNil ptr) => (NotEqual (CMPconst [0] ptr))
451 (IsInBounds idx len) => (LessThanU (CMP idx len))
452 (IsSliceInBounds idx len) => (LessEqualU (CMP idx len))
453
454 // pseudo-ops
455 (GetClosurePtr ...) => (LoweredGetClosurePtr ...)
456 (GetCallerSP ...) => (LoweredGetCallerSP ...)
457 (GetCallerPC ...) => (LoweredGetCallerPC ...)
458 (MemEq ...) => (LoweredMemEq ...)
459
460 // Absorb pseudo-ops into blocks.
461 (If (Equal cc) yes no) => (EQ cc yes no)
462 (If (NotEqual cc) yes no) => (NE cc yes no)
463 (If (LessThan cc) yes no) => (LT cc yes no)
464 (If (LessThanU cc) yes no) => (ULT cc yes no)
465 (If (LessEqual cc) yes no) => (LE cc yes no)
466 (If (LessEqualU cc) yes no) => (ULE cc yes no)
467 (If (GreaterThan cc) yes no) => (GT cc yes no)
468 (If (GreaterThanU cc) yes no) => (UGT cc yes no)
469 (If (GreaterEqual cc) yes no) => (GE cc yes no)
470 (If (GreaterEqualU cc) yes no) => (UGE cc yes no)
471 (If (LessThanF cc) yes no) => (FLT cc yes no)
472 (If (LessEqualF cc) yes no) => (FLE cc yes no)
473 (If (GreaterThanF cc) yes no) => (FGT cc yes no)
474 (If (GreaterEqualF cc) yes no) => (FGE cc yes no)
475
476 (If cond yes no) => (TBNZ [0] cond yes no)
477
478 (JumpTable idx) => (JUMPTABLE {makeJumpTableSym(b)} idx (MOVDaddr <typ.Uintptr> {makeJumpTableSym(b)} (SB)))
479
480 // atomic intrinsics
481 // Note: these ops do not accept offset.
482 (AtomicLoad8 ...) => (LDARB ...)
483 (AtomicLoad32 ...) => (LDARW ...)
484 (AtomicLoad64 ...) => (LDAR ...)
485 (AtomicLoadPtr ...) => (LDAR ...)
486
487 (AtomicStore8 ...) => (STLRB ...)
488 (AtomicStore32 ...) => (STLRW ...)
489 (AtomicStore64 ...) => (STLR ...)
490 (AtomicStorePtrNoWB ...) => (STLR ...)
491
492 (AtomicExchange(8|32|64) ...) => (LoweredAtomicExchange(8|32|64) ...)
493 (AtomicAdd(32|64) ...) => (LoweredAtomicAdd(32|64) ...)
494 (AtomicCompareAndSwap(32|64) ...) => (LoweredAtomicCas(32|64) ...)
495
496 (AtomicAdd(32|64)Variant ...) => (LoweredAtomicAdd(32|64)Variant ...)
497 (AtomicExchange(8|32|64)Variant ...) => (LoweredAtomicExchange(8|32|64)Variant ...)
498 (AtomicCompareAndSwap(32|64)Variant ...) => (LoweredAtomicCas(32|64)Variant ...)
499
500 // Return old contents.
501 (AtomicAnd(64|32|8)value ...) => (LoweredAtomicAnd(64|32|8) ...)
502 (AtomicOr(64|32|8)value ...) => (LoweredAtomicOr(64|32|8) ...)
503 (AtomicAnd(64|32|8)valueVariant ...) => (LoweredAtomicAnd(64|32|8)Variant ...)
504 (AtomicOr(64|32|8)valueVariant ...) => (LoweredAtomicOr(64|32|8)Variant ...)
505
506 // Write barrier.
507 (WB ...) => (LoweredWB ...)
508
509 // Publication barrier (0xe is ST option)
510 (PubBarrier mem) => (DMB [0xe] mem)
511
512 (PanicBounds ...) => (LoweredPanicBoundsRR ...)
513 (LoweredPanicBoundsRR [kind] x (MOVDconst [c]) mem) => (LoweredPanicBoundsRC [kind] x {PanicBoundsC{C:c}} mem)
514 (LoweredPanicBoundsRR [kind] (MOVDconst [c]) y mem) => (LoweredPanicBoundsCR [kind] {PanicBoundsC{C:c}} y mem)
515 (LoweredPanicBoundsRC [kind] {p} (MOVDconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:c, Cy:p.C}} mem)
516 (LoweredPanicBoundsCR [kind] {p} (MOVDconst [c]) mem) => (LoweredPanicBoundsCC [kind] {PanicBoundsCC{Cx:p.C, Cy:c}} mem)
517
518 // Optimizations
519
520 // Replace widen -> wide_unop -> narrow with narrow_unop when one exists.
521 (FCVTDS (F(ABS|SQRT|RINTP|RINTM|RINTA|RINTN|RINTZ)D (FCVTSD x))) =>
522 (F(ABS|SQRT|RINTP|RINTM|RINTA|RINTN|RINTZ)S x)
523
524
525 // Absorb boolean tests into block
526 (NZ (Equal cc) yes no) => (EQ cc yes no)
527 (NZ (NotEqual cc) yes no) => (NE cc yes no)
528 (NZ (LessThan cc) yes no) => (LT cc yes no)
529 (NZ (LessThanU cc) yes no) => (ULT cc yes no)
530 (NZ (LessEqual cc) yes no) => (LE cc yes no)
531 (NZ (LessEqualU cc) yes no) => (ULE cc yes no)
532 (NZ (GreaterThan cc) yes no) => (GT cc yes no)
533 (NZ (GreaterThanU cc) yes no) => (UGT cc yes no)
534 (NZ (GreaterEqual cc) yes no) => (GE cc yes no)
535 (NZ (GreaterEqualU cc) yes no) => (UGE cc yes no)
536 (NZ (LessThanF cc) yes no) => (FLT cc yes no)
537 (NZ (LessEqualF cc) yes no) => (FLE cc yes no)
538 (NZ (GreaterThanF cc) yes no) => (FGT cc yes no)
539 (NZ (GreaterEqualF cc) yes no) => (FGE cc yes no)
540
541 (TBNZ [0] (Equal cc) yes no) => (EQ cc yes no)
542 (TBNZ [0] (NotEqual cc) yes no) => (NE cc yes no)
543 (TBNZ [0] (LessThan cc) yes no) => (LT cc yes no)
544 (TBNZ [0] (LessThanU cc) yes no) => (ULT cc yes no)
545 (TBNZ [0] (LessEqual cc) yes no) => (LE cc yes no)
546 (TBNZ [0] (LessEqualU cc) yes no) => (ULE cc yes no)
547 (TBNZ [0] (GreaterThan cc) yes no) => (GT cc yes no)
548 (TBNZ [0] (GreaterThanU cc) yes no) => (UGT cc yes no)
549 (TBNZ [0] (GreaterEqual cc) yes no) => (GE cc yes no)
550 (TBNZ [0] (GreaterEqualU cc) yes no) => (UGE cc yes no)
551 (TBNZ [0] (LessThanF cc) yes no) => (FLT cc yes no)
552 (TBNZ [0] (LessEqualF cc) yes no) => (FLE cc yes no)
553 (TBNZ [0] (GreaterThanF cc) yes no) => (FGT cc yes no)
554 (TBNZ [0] (GreaterEqualF cc) yes no) => (FGE cc yes no)
555
556 (TB(Z|NZ) [0] (XORconst [1] x) yes no) => (TB(NZ|Z) [0] x yes no)
557
558 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TST x y) yes no)
559 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] x:(ANDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTconst [c] y) yes no)
560 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(AND x y)) yes no) && z.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTW x y) yes no)
561 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] x:(ANDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LT|LE|GT|GE) (TSTWconst [int32(c)] y) yes no)
562
563 // For conditional instructions such as CSET, CSEL.
564 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPconst [0] z:(AND x y))) && z.Uses == 1 =>
565 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TST x y))
566 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPWconst [0] x:(ANDconst [c] y))) && x.Uses == 1 =>
567 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTWconst [int32(c)] y))
568 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPWconst [0] z:(AND x y))) && z.Uses == 1 =>
569 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTW x y))
570 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (CMPconst [0] x:(ANDconst [c] y))) && x.Uses == 1 =>
571 ((Equal|NotEqual|LessThan|LessEqual|GreaterThan|GreaterEqual) (TSTconst [c] y))
572
573 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] x:(ADDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNconst [c] y) yes no)
574 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] x:(ADDconst [c] y)) yes no) && x.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNWconst [int32(c)] y) yes no)
575 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(ADD x y)) yes no) && z.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMN x y) yes no)
576 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(ADD x y)) yes no) && z.Uses == 1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNW x y) yes no)
577
578 // CMP(x,-y) -> CMN(x,y) is only valid for unordered comparison, if y can be -1<<63
579 ((EQ|NE) (CMP x z:(NEG y)) yes no) && z.Uses == 1 => ((EQ|NE) (CMN x y) yes no)
580 ((Equal|NotEqual) (CMP x z:(NEG y))) && z.Uses == 1 => ((Equal|NotEqual) (CMN x y))
581
582 // CMPW(x,-y) -> CMNW(x,y) is only valid for unordered comparison, if y can be -1<<31
583 ((EQ|NE) (CMPW x z:(NEG y)) yes no) && z.Uses == 1 => ((EQ|NE) (CMNW x y) yes no)
584 ((Equal|NotEqual) (CMPW x z:(NEG y))) && z.Uses == 1 => ((Equal|NotEqual) (CMNW x y))
585
586 // For conditional instructions such as CSET, CSEL.
587 // TODO: add support for LE, GT, overflow needs to be considered.
588 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] x:(ADDconst [c] y))) && x.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNconst [c] y))
589 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] x:(ADDconst [c] y))) && x.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNWconst [int32(c)] y))
590 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] z:(ADD x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMN x y))
591 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] z:(ADD x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNW x y))
592 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPconst [0] z:(MADD a x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMN a (MUL <x.Type> x y)))
593 ((Equal|NotEqual|LessThan|GreaterEqual) (CMPWconst [0] z:(MADDW a x y))) && z.Uses == 1 => ((Equal|NotEqual|LessThanNoov|GreaterEqualNoov) (CMNW a (MULW <x.Type> x y)))
594
595 // Skip LessThan/GreaterEqual in the following rewrites.
596 // MSUB[W] a x y is a-x*y, which folds to a CMP.
597 // That can end up being reversed into InvertFlags.
598 // But absorbing InvertFlags into a no-overflow comparison flips < and >,
599 // which is wrong when the difference is the minimum int.
600 ((Equal|NotEqual) (CMPconst [0] z:(MSUB a x y))) && z.Uses == 1 => ((Equal|NotEqual) (CMP a (MUL <x.Type> x y)))
601 ((Equal|NotEqual) (CMPWconst [0] z:(MSUBW a x y))) && z.Uses == 1 => ((Equal|NotEqual) (CMPW a (MULW <x.Type> x y)))
602
603 ((CMPconst|CMNconst) [c] y) && c < 0 && c != -1<<63 => ((CMNconst|CMPconst) [-c] y)
604 ((CMPWconst|CMNWconst) [c] y) && c < 0 && c != -1<<31 => ((CMNWconst|CMPWconst) [-c] y)
605
606 ((EQ|NE) (CMPconst [0] x) yes no) => ((Z|NZ) x yes no)
607 ((EQ|NE) (CMPWconst [0] x) yes no) => ((ZW|NZW) x yes no)
608
609 ((ULE|UGT) (CMPconst [0] x)) => ((EQ|NE) (CMPconst [0] x))
610 ((ULE|UGT) (CMPWconst [0] x)) => ((EQ|NE) (CMPWconst [0] x))
611
612 ((Z|NZ) sub:(SUB x y)) && sub.Uses == 1 => ((EQ|NE) (CMP x y))
613 ((ZW|NZW) sub:(SUB x y)) && sub.Uses == 1 => ((EQ|NE) (CMPW x y))
614 ((Z|NZ) sub:(SUBconst [c] y)) && sub.Uses == 1 => ((EQ|NE) (CMPconst [c] y))
615 ((ZW|NZW) sub:(SUBconst [c] y)) && sub.Uses == 1 => ((EQ|NE) (CMPWconst [int32(c)] y))
616
617 ((EQ|NE|LT|LE|GT|GE) (CMPconst [0] z:(MADD a x y)) yes no) && z.Uses==1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMN a (MUL <x.Type> x y)) yes no)
618 ((EQ|NE|LT|LE|GT|GE) (CMPWconst [0] z:(MADDW a x y)) yes no) && z.Uses==1 => ((EQ|NE|LTnoov|LEnoov|GTnoov|GEnoov) (CMNW a (MULW <x.Type> x y)) yes no)
619 // No ordering ops here; see comments above about MSUB[W].
620 ((EQ|NE) (CMPconst [0] z:(MSUB a x y)) yes no) && z.Uses==1 => ((EQ|NE) (CMP a (MUL <x.Type> x y)) yes no)
621 ((EQ|NE) (CMPWconst [0] z:(MSUBW a x y)) yes no) && z.Uses==1 => ((EQ|NE) (CMPW a (MULW <x.Type> x y)) yes no)
622
623 // Absorb bit-tests into block
624 (Z (ANDconst [c] x) yes no) && oneBit(c) => (TBZ [int64(ntz64(c))] x yes no)
625 (NZ (ANDconst [c] x) yes no) && oneBit(c) => (TBNZ [int64(ntz64(c))] x yes no)
626 (ZW (ANDconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBZ [int64(ntz64(int64(uint32(c))))] x yes no)
627 (NZW (ANDconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no)
628 (EQ (TSTconst [c] x) yes no) && oneBit(c) => (TBZ [int64(ntz64(c))] x yes no)
629 (NE (TSTconst [c] x) yes no) && oneBit(c) => (TBNZ [int64(ntz64(c))] x yes no)
630 (EQ (TSTWconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBZ [int64(ntz64(int64(uint32(c))))] x yes no)
631 (NE (TSTWconst [c] x) yes no) && oneBit(int64(uint32(c))) => (TBNZ [int64(ntz64(int64(uint32(c))))] x yes no)
632
633 ((Z|NZ) s:(SRLconst [63] x) yes no) && s.Uses == 1 => (TB(Z|NZ) [63] x yes no)
634 ((Z|NZ) s:(SRAconst [63] x) yes no) && s.Uses == 1 => (TB(Z|NZ) [63] x yes no)
635
636 // Merge more operations into TBZ & TBNZ
637 (TB(Z|NZ) [t] sv:(SRLconst [s] x) yes no) && t+s < 64 && sv.Uses == 1 => (TB(Z|NZ) [t+s] x yes no )
638 (TBZ [t] (SRLconst [s] x) yes no) && t+s >= 64 => (First yes no )
639 (TBNZ [t] (SRLconst [s] x) yes no) && t+s >= 64 => (First no yes)
640
641 (TB(Z|NZ) [t] sv:(SLLconst [s] x) yes no) && t-s >= 0 && sv.Uses == 1 => (TB(Z|NZ) [t-s] x yes no )
642 (TBZ [t] (SLLconst [s] x) yes no) && t-s < 0 => (First yes no )
643 (TBNZ [t] (SLLconst [s] x) yes no) && t-s < 0 => (First no yes)
644
645 (TB(Z|NZ) [t] rv:(RORconst [r] x) yes no) && rv.Uses == 1 => (TB(Z|NZ) [int64(uint64(t+r)%64)] x yes no)
646
647 (TB(Z|NZ) [t] sv:(SRAconst [s] x) yes no) && t+s < 64 && sv.Uses == 1 => (TB(Z|NZ) [t+s] x yes no)
648 (TB(Z|NZ) [t] sv:(SRAconst [s] x) yes no) && t+s >= 64 && sv.Uses == 1 => (TB(Z|NZ) [63 ] x yes no)
649
650 // Test sign-bit for signed comparisons against zero
651 (GE (CMPWconst [0] x) yes no) => (TBZ [31] x yes no)
652 (GE (CMPconst [0] x) yes no) => (TBZ [63] x yes no)
653 (LT (CMPWconst [0] x) yes no) => (TBNZ [31] x yes no)
654 (LT (CMPconst [0] x) yes no) => (TBNZ [63] x yes no)
655
656 // A byte value (a zero-extended-byte op, so provably in [0,255]) compared
657 // against 128 (=2^7) is a bit-7 test, for both compare widths and both
658 // signednesses: with the value in [0,255] the signed and unsigned orderings
659 // against 128 coincide.
660 ((UGE|ULT) (CMPWconst [128] x) yes no) && ZeroUpper56Bits(x) => ((TBNZ|TBZ) [7] x yes no)
661 ((UGE|ULT) (CMPconst [128] x) yes no) && ZeroUpper56Bits(x) => ((TBNZ|TBZ) [7] x yes no)
662 ((GE|LT) (CMPWconst [128] x) yes no) && ZeroUpper56Bits(x) => ((TBNZ|TBZ) [7] x yes no)
663 ((GE|LT) (CMPconst [128] x) yes no) && ZeroUpper56Bits(x) => ((TBNZ|TBZ) [7] x yes no)
664
665 // fold offset into address
666 (ADDconst [off1] (MOVDaddr [off2] {sym} ptr)) && is32Bit(off1+int64(off2)) =>
667 (MOVDaddr [int32(off1)+off2] {sym} ptr)
668
669 // fold address into load/store.
670 // Do not fold global variable access in -dynlink mode, where it will
671 // be rewritten to use the GOT via REGTMP, which currently cannot handle
672 // large offset.
673 (MOVBload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
674 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
675 (MOVBload [off1+int32(off2)] {sym} ptr mem)
676 (MOVBUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
677 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
678 (MOVBUload [off1+int32(off2)] {sym} ptr mem)
679 (MOVHload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
680 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
681 (MOVHload [off1+int32(off2)] {sym} ptr mem)
682 (MOVHUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
683 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
684 (MOVHUload [off1+int32(off2)] {sym} ptr mem)
685 (MOVWload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
686 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
687 (MOVWload [off1+int32(off2)] {sym} ptr mem)
688 (MOVWUload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
689 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
690 (MOVWUload [off1+int32(off2)] {sym} ptr mem)
691 (MOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
692 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
693 (MOVDload [off1+int32(off2)] {sym} ptr mem)
694 (LDP [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
695 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
696 (LDP [off1+int32(off2)] {sym} ptr mem)
697 (FMOVSload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
698 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
699 (FMOVSload [off1+int32(off2)] {sym} ptr mem)
700 (FMOVDload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
701 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
702 (FMOVDload [off1+int32(off2)] {sym} ptr mem)
703 (FMOVQload [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
704 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
705 (FMOVQload [off1+int32(off2)] {sym} ptr mem)
706 (FLDPQ [off1] {sym} (ADDconst [off2] ptr) mem) && is32Bit(int64(off1)+off2)
707 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
708 (FLDPQ [off1+int32(off2)] {sym} ptr mem)
709
710 // register indexed load
711 (MOVDload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx ptr idx mem)
712 (MOVWUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx ptr idx mem)
713 (MOVWload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx ptr idx mem)
714 (MOVHUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx ptr idx mem)
715 (MOVHload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx ptr idx mem)
716 (MOVBUload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVBUloadidx ptr idx mem)
717 (MOVBload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (MOVBloadidx ptr idx mem)
718 (FMOVSload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (FMOVSloadidx ptr idx mem)
719 (FMOVDload [off] {sym} (ADD ptr idx) mem) && off == 0 && sym == nil => (FMOVDloadidx ptr idx mem)
720
721 (MOVDloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVDload [int32(c)] ptr mem)
722 (MOVDloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVDload [int32(c)] ptr mem)
723 (MOVWUloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVWUload [int32(c)] ptr mem)
724 (MOVWUloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVWUload [int32(c)] ptr mem)
725 (MOVWloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVWload [int32(c)] ptr mem)
726 (MOVWloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVWload [int32(c)] ptr mem)
727 (MOVHUloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVHUload [int32(c)] ptr mem)
728 (MOVHUloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVHUload [int32(c)] ptr mem)
729 (MOVHloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVHload [int32(c)] ptr mem)
730 (MOVHloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVHload [int32(c)] ptr mem)
731 (MOVBUloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVBUload [int32(c)] ptr mem)
732 (MOVBUloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVBUload [int32(c)] ptr mem)
733 (MOVBloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (MOVBload [int32(c)] ptr mem)
734 (MOVBloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (MOVBload [int32(c)] ptr mem)
735 (FMOVSloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (FMOVSload [int32(c)] ptr mem)
736 (FMOVSloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (FMOVSload [int32(c)] ptr mem)
737 (FMOVDloadidx ptr (MOVDconst [c]) mem) && is32Bit(c) => (FMOVDload [int32(c)] ptr mem)
738 (FMOVDloadidx (MOVDconst [c]) ptr mem) && is32Bit(c) => (FMOVDload [int32(c)] ptr mem)
739
740 // shifted register indexed load
741 (MOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) && off == 0 && sym == nil => (MOVDloadidx8 ptr idx mem)
742 (MOVWUload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (MOVWUloadidx4 ptr idx mem)
743 (MOVWload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (MOVWloadidx4 ptr idx mem)
744 (MOVHUload [off] {sym} (ADDshiftLL [1] ptr idx) mem) && off == 0 && sym == nil => (MOVHUloadidx2 ptr idx mem)
745 (MOVHload [off] {sym} (ADDshiftLL [1] ptr idx) mem) && off == 0 && sym == nil => (MOVHloadidx2 ptr idx mem)
746 (MOVDloadidx ptr (SLLconst [3] idx) mem) => (MOVDloadidx8 ptr idx mem)
747 (MOVWloadidx ptr (SLLconst [2] idx) mem) => (MOVWloadidx4 ptr idx mem)
748 (MOVWUloadidx ptr (SLLconst [2] idx) mem) => (MOVWUloadidx4 ptr idx mem)
749 (MOVHloadidx ptr (SLLconst [1] idx) mem) => (MOVHloadidx2 ptr idx mem)
750 (MOVHUloadidx ptr (SLLconst [1] idx) mem) => (MOVHUloadidx2 ptr idx mem)
751 (MOVHloadidx ptr (ADD idx idx) mem) => (MOVHloadidx2 ptr idx mem)
752 (MOVHUloadidx ptr (ADD idx idx) mem) => (MOVHUloadidx2 ptr idx mem)
753 (MOVDloadidx (SLLconst [3] idx) ptr mem) => (MOVDloadidx8 ptr idx mem)
754 (MOVWloadidx (SLLconst [2] idx) ptr mem) => (MOVWloadidx4 ptr idx mem)
755 (MOVWUloadidx (SLLconst [2] idx) ptr mem) => (MOVWUloadidx4 ptr idx mem)
756 (MOVHloadidx (ADD idx idx) ptr mem) => (MOVHloadidx2 ptr idx mem)
757 (MOVHUloadidx (ADD idx idx) ptr mem) => (MOVHUloadidx2 ptr idx mem)
758 (MOVDloadidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (MOVDload [int32(c)<<3] ptr mem)
759 (MOVWUloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (MOVWUload [int32(c)<<2] ptr mem)
760 (MOVWloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (MOVWload [int32(c)<<2] ptr mem)
761 (MOVHUloadidx2 ptr (MOVDconst [c]) mem) && is32Bit(c<<1) => (MOVHUload [int32(c)<<1] ptr mem)
762 (MOVHloadidx2 ptr (MOVDconst [c]) mem) && is32Bit(c<<1) => (MOVHload [int32(c)<<1] ptr mem)
763
764 (FMOVDload [off] {sym} (ADDshiftLL [3] ptr idx) mem) && off == 0 && sym == nil => (FMOVDloadidx8 ptr idx mem)
765 (FMOVSload [off] {sym} (ADDshiftLL [2] ptr idx) mem) && off == 0 && sym == nil => (FMOVSloadidx4 ptr idx mem)
766 (FMOVDloadidx ptr (SLLconst [3] idx) mem) => (FMOVDloadidx8 ptr idx mem)
767 (FMOVSloadidx ptr (SLLconst [2] idx) mem) => (FMOVSloadidx4 ptr idx mem)
768 (FMOVDloadidx (SLLconst [3] idx) ptr mem) => (FMOVDloadidx8 ptr idx mem)
769 (FMOVSloadidx (SLLconst [2] idx) ptr mem) => (FMOVSloadidx4 ptr idx mem)
770 (FMOVDloadidx8 ptr (MOVDconst [c]) mem) && is32Bit(c<<3) => (FMOVDload ptr [int32(c)<<3] mem)
771 (FMOVSloadidx4 ptr (MOVDconst [c]) mem) && is32Bit(c<<2) => (FMOVSload ptr [int32(c)<<2] mem)
772
773 (MOVBstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
774 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
775 (MOVBstore [off1+int32(off2)] {sym} ptr val mem)
776 (MOVHstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
777 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
778 (MOVHstore [off1+int32(off2)] {sym} ptr val mem)
779 (MOVWstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
780 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
781 (MOVWstore [off1+int32(off2)] {sym} ptr val mem)
782 (MOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
783 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
784 (MOVDstore [off1+int32(off2)] {sym} ptr val mem)
785 (STP [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && is32Bit(int64(off1)+off2)
786 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
787 (STP [off1+int32(off2)] {sym} ptr val1 val2 mem)
788 (FMOVSstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
789 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
790 (FMOVSstore [off1+int32(off2)] {sym} ptr val mem)
791 (FMOVDstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
792 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
793 (FMOVDstore [off1+int32(off2)] {sym} ptr val mem)
794 (FMOVQstore [off1] {sym} (ADDconst [off2] ptr) val mem) && is32Bit(int64(off1)+off2)
795 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
796 (FMOVQstore [off1+int32(off2)] {sym} ptr val mem)
797 (FSTPQ [off1] {sym} (ADDconst [off2] ptr) val1 val2 mem) && is32Bit(int64(off1)+off2)
798 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
799 (FSTPQ [off1+int32(off2)] {sym} ptr val1 val2 mem)
800
801 // register indexed store
802 (MOVDstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx ptr idx val mem)
803 (MOVWstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx ptr idx val mem)
804 (MOVHstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx ptr idx val mem)
805 (MOVBstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (MOVBstoreidx ptr idx val mem)
806 (FMOVDstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (FMOVDstoreidx ptr idx val mem)
807 (FMOVSstore [off] {sym} (ADD ptr idx) val mem) && off == 0 && sym == nil => (FMOVSstoreidx ptr idx val mem)
808 (MOVDstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (MOVDstore [int32(c)] ptr val mem)
809 (MOVDstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (MOVDstore [int32(c)] idx val mem)
810 (MOVWstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (MOVWstore [int32(c)] ptr val mem)
811 (MOVWstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (MOVWstore [int32(c)] idx val mem)
812 (MOVHstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (MOVHstore [int32(c)] ptr val mem)
813 (MOVHstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (MOVHstore [int32(c)] idx val mem)
814 (MOVBstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (MOVBstore [int32(c)] ptr val mem)
815 (MOVBstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (MOVBstore [int32(c)] idx val mem)
816 (FMOVDstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (FMOVDstore [int32(c)] ptr val mem)
817 (FMOVDstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (FMOVDstore [int32(c)] idx val mem)
818 (FMOVSstoreidx ptr (MOVDconst [c]) val mem) && is32Bit(c) => (FMOVSstore [int32(c)] ptr val mem)
819 (FMOVSstoreidx (MOVDconst [c]) idx val mem) && is32Bit(c) => (FMOVSstore [int32(c)] idx val mem)
820
821 // shifted register indexed store
822 (MOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) && off == 0 && sym == nil => (MOVDstoreidx8 ptr idx val mem)
823 (MOVWstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) && off == 0 && sym == nil => (MOVWstoreidx4 ptr idx val mem)
824 (MOVHstore [off] {sym} (ADDshiftLL [1] ptr idx) val mem) && off == 0 && sym == nil => (MOVHstoreidx2 ptr idx val mem)
825 (MOVDstoreidx ptr (SLLconst [3] idx) val mem) => (MOVDstoreidx8 ptr idx val mem)
826 (MOVWstoreidx ptr (SLLconst [2] idx) val mem) => (MOVWstoreidx4 ptr idx val mem)
827 (MOVHstoreidx ptr (SLLconst [1] idx) val mem) => (MOVHstoreidx2 ptr idx val mem)
828 (MOVHstoreidx ptr (ADD idx idx) val mem) => (MOVHstoreidx2 ptr idx val mem)
829 (MOVDstoreidx (SLLconst [3] idx) ptr val mem) => (MOVDstoreidx8 ptr idx val mem)
830 (MOVWstoreidx (SLLconst [2] idx) ptr val mem) => (MOVWstoreidx4 ptr idx val mem)
831 (MOVHstoreidx (SLLconst [1] idx) ptr val mem) => (MOVHstoreidx2 ptr idx val mem)
832 (MOVHstoreidx (ADD idx idx) ptr val mem) => (MOVHstoreidx2 ptr idx val mem)
833 (MOVDstoreidx8 ptr (MOVDconst [c]) val mem) && is32Bit(c<<3) => (MOVDstore [int32(c)<<3] ptr val mem)
834 (MOVWstoreidx4 ptr (MOVDconst [c]) val mem) && is32Bit(c<<2) => (MOVWstore [int32(c)<<2] ptr val mem)
835 (MOVHstoreidx2 ptr (MOVDconst [c]) val mem) && is32Bit(c<<1) => (MOVHstore [int32(c)<<1] ptr val mem)
836
837 (FMOVDstore [off] {sym} (ADDshiftLL [3] ptr idx) val mem) && off == 0 && sym == nil => (FMOVDstoreidx8 ptr idx val mem)
838 (FMOVSstore [off] {sym} (ADDshiftLL [2] ptr idx) val mem) && off == 0 && sym == nil => (FMOVSstoreidx4 ptr idx val mem)
839 (FMOVDstoreidx ptr (SLLconst [3] idx) val mem) => (FMOVDstoreidx8 ptr idx val mem)
840 (FMOVSstoreidx ptr (SLLconst [2] idx) val mem) => (FMOVSstoreidx4 ptr idx val mem)
841 (FMOVDstoreidx (SLLconst [3] idx) ptr val mem) => (FMOVDstoreidx8 ptr idx val mem)
842 (FMOVSstoreidx (SLLconst [2] idx) ptr val mem) => (FMOVSstoreidx4 ptr idx val mem)
843 (FMOVDstoreidx8 ptr (MOVDconst [c]) val mem) && is32Bit(c<<3) => (FMOVDstore [int32(c)<<3] ptr val mem)
844 (FMOVSstoreidx4 ptr (MOVDconst [c]) val mem) && is32Bit(c<<2) => (FMOVSstore [int32(c)<<2] ptr val mem)
845
846 (MOVBload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
847 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
848 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
849 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
850 (MOVBUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
851 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
852 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
853 (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
854 (MOVHload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
855 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
856 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
857 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
858 (MOVHUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
859 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
860 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
861 (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
862 (MOVWload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
863 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
864 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
865 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
866 (MOVWUload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
867 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
868 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
869 (MOVWUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
870 (MOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
871 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
872 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
873 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
874 (LDP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
875 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
876 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
877 (LDP [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
878 (FMOVSload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
879 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
880 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
881 (FMOVSload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
882 (FMOVDload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
883 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
884 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
885 (FMOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
886 (FMOVQload [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
887 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
888 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
889 (FMOVQload [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
890 (FLDPQ [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) mem)
891 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
892 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
893 (FLDPQ [off1+off2] {mergeSym(sym1,sym2)} ptr mem)
894
895 (MOVBstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
896 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
897 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
898 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
899 (MOVHstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
900 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
901 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
902 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
903 (MOVWstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
904 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
905 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
906 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
907 (MOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
908 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
909 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
910 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
911 (STP [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem)
912 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
913 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
914 (STP [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem)
915 (FMOVSstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
916 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
917 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
918 (FMOVSstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
919 (FMOVDstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
920 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
921 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
922 (FMOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
923 (FMOVQstore [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val mem)
924 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
925 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
926 (FMOVQstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem)
927 (FSTPQ [off1] {sym1} (MOVDaddr [off2] {sym2} ptr) val1 val2 mem)
928 && canMergeSym(sym1,sym2) && is32Bit(int64(off1)+int64(off2))
929 && (ptr.Op != OpSB || !config.ctxt.Flag_dynlink) =>
930 (FSTPQ [off1+off2] {mergeSym(sym1,sym2)} ptr val1 val2 mem)
931
932 // replace load from same location as preceding store with zero/sign extension (or copy in case of full width)
933 // these seem to have bad interaction with other rules, resulting in slower code
934 //(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVBreg x)
935 //(MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVBUreg x)
936 //(MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVHreg x)
937 //(MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVHUreg x)
938 //(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVWreg x)
939 //(MOVWUload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> (MOVWUreg x)
940 //(MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
941 //(FMOVSload [off] {sym} ptr (FMOVSstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
942 //(FMOVDload [off] {sym} ptr (FMOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x
943 //(LDP [off] {sym} ptr (STP [off2] {sym2} ptr2 x y _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) -> x y
944
945 // don't extend before store
946 (MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
947 (MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
948 (MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
949 (MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
950 (MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
951 (MOVBstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVBstore [off] {sym} ptr x mem)
952 (MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
953 (MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
954 (MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
955 (MOVHstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVHstore [off] {sym} ptr x mem)
956 (MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
957 (MOVWstore [off] {sym} ptr (MOVWUreg x) mem) => (MOVWstore [off] {sym} ptr x mem)
958 (MOVBstoreidx ptr idx (MOVBreg x) mem) => (MOVBstoreidx ptr idx x mem)
959 (MOVBstoreidx ptr idx (MOVBUreg x) mem) => (MOVBstoreidx ptr idx x mem)
960 (MOVBstoreidx ptr idx (MOVHreg x) mem) => (MOVBstoreidx ptr idx x mem)
961 (MOVBstoreidx ptr idx (MOVHUreg x) mem) => (MOVBstoreidx ptr idx x mem)
962 (MOVBstoreidx ptr idx (MOVWreg x) mem) => (MOVBstoreidx ptr idx x mem)
963 (MOVBstoreidx ptr idx (MOVWUreg x) mem) => (MOVBstoreidx ptr idx x mem)
964 (MOVHstoreidx ptr idx (MOVHreg x) mem) => (MOVHstoreidx ptr idx x mem)
965 (MOVHstoreidx ptr idx (MOVHUreg x) mem) => (MOVHstoreidx ptr idx x mem)
966 (MOVHstoreidx ptr idx (MOVWreg x) mem) => (MOVHstoreidx ptr idx x mem)
967 (MOVHstoreidx ptr idx (MOVWUreg x) mem) => (MOVHstoreidx ptr idx x mem)
968 (MOVWstoreidx ptr idx (MOVWreg x) mem) => (MOVWstoreidx ptr idx x mem)
969 (MOVWstoreidx ptr idx (MOVWUreg x) mem) => (MOVWstoreidx ptr idx x mem)
970 (MOVHstoreidx2 ptr idx (MOVHreg x) mem) => (MOVHstoreidx2 ptr idx x mem)
971 (MOVHstoreidx2 ptr idx (MOVHUreg x) mem) => (MOVHstoreidx2 ptr idx x mem)
972 (MOVHstoreidx2 ptr idx (MOVWreg x) mem) => (MOVHstoreidx2 ptr idx x mem)
973 (MOVHstoreidx2 ptr idx (MOVWUreg x) mem) => (MOVHstoreidx2 ptr idx x mem)
974 (MOVWstoreidx4 ptr idx (MOVWreg x) mem) => (MOVWstoreidx4 ptr idx x mem)
975 (MOVWstoreidx4 ptr idx (MOVWUreg x) mem) => (MOVWstoreidx4 ptr idx x mem)
976
977 // if a register move has only 1 use, just use the same register without emitting instruction
978 // MOVDnop doesn't emit instruction, only for ensuring the type.
979 (MOVDreg x) && x.Uses == 1 => (MOVDnop x)
980
981 // TODO: we should be able to get rid of MOVDnop all together.
982 // But for now, this is enough to get rid of lots of them.
983 (MOVDnop (MOVDconst [c])) => (MOVDconst [c])
984
985 // fold constant into arithmetic ops
986 (ADD x (MOVDconst <t> [c])) && !t.IsPtr() => (ADDconst [c] x)
987 (SUB x (MOVDconst [c])) => (SUBconst [c] x)
988 (AND x (MOVDconst [c])) => (ANDconst [c] x)
989 (OR x (MOVDconst [c])) => (ORconst [c] x)
990 (XOR x (MOVDconst [c])) => (XORconst [c] x)
991 (TST x (MOVDconst [c])) => (TSTconst [c] x)
992 (TSTW x (MOVDconst [c])) => (TSTWconst [int32(c)] x)
993 (CMN x (MOVDconst [c])) => (CMNconst [c] x)
994 (CMNW x (MOVDconst [c])) => (CMNWconst [int32(c)] x)
995 (BIC x (MOVDconst [c])) => (ANDconst [^c] x)
996 (EON x (MOVDconst [c])) => (XORconst [^c] x)
997 (ORN x (MOVDconst [c])) => (ORconst [^c] x)
998
999 (SLL x (MOVDconst [c])) => (SLLconst x [c&63])
1000 (SRL x (MOVDconst [c])) => (SRLconst x [c&63])
1001 (SRA x (MOVDconst [c])) => (SRAconst x [c&63])
1002 (SLL x (ANDconst [63] y)) => (SLL x y)
1003 (SRL x (ANDconst [63] y)) => (SRL x y)
1004 (SRA x (ANDconst [63] y)) => (SRA x y)
1005
1006 (CMP x (MOVDconst [c])) => (CMPconst [c] x)
1007 (CMP (MOVDconst [c]) x) => (InvertFlags (CMPconst [c] x))
1008 (CMPW x (MOVDconst [c])) => (CMPWconst [int32(c)] x)
1009 (CMPW (MOVDconst [c]) x) => (InvertFlags (CMPWconst [int32(c)] x))
1010
1011 (ROR x (MOVDconst [c])) => (RORconst x [c&63])
1012 (RORW x (MOVDconst [c])) => (RORWconst x [c&31])
1013
1014 (ADDSflags x (MOVDconst [c])) => (ADDSconstflags [c] x)
1015
1016 (ADDconst [c] y) && c < 0 => (SUBconst [-c] y)
1017
1018 // Canonicalize the order of arguments to comparisons - helps with CSE.
1019 ((CMP|CMPW) x y) && canonLessThan(x,y) => (InvertFlags ((CMP|CMPW) y x))
1020
1021 // mul-neg => mneg
1022 (NEG (MUL x y)) => (MNEG x y)
1023 (NEG (MULW x y)) && v.Type.Size() <= 4 => (MNEGW x y)
1024 (MUL (NEG x) y) => (MNEG x y)
1025 (MULW (NEG x) y) => (MNEGW x y)
1026
1027 // madd/msub
1028 (ADD a l:(MUL x y)) && l.Uses==1 && clobber(l) => (MADD a x y)
1029 (SUB a l:(MUL x y)) && l.Uses==1 && clobber(l) => (MSUB a x y)
1030 (ADD a l:(MNEG x y)) && l.Uses==1 && clobber(l) => (MSUB a x y)
1031 (SUB a l:(MNEG x y)) && l.Uses==1 && clobber(l) => (MADD a x y)
1032
1033 (ADD a l:(MULW x y)) && v.Type.Size() <= 4 && l.Uses==1 && clobber(l) => (MADDW a x y)
1034 (SUB a l:(MULW x y)) && v.Type.Size() <= 4 && l.Uses==1 && clobber(l) => (MSUBW a x y)
1035 (ADD a l:(MNEGW x y)) && v.Type.Size() <= 4 && l.Uses==1 && clobber(l) => (MSUBW a x y)
1036 (SUB a l:(MNEGW x y)) && v.Type.Size() <= 4 && l.Uses==1 && clobber(l) => (MADDW a x y)
1037
1038 // madd/msub can't take constant arguments, so do a bit of reordering if a non-constant is available.
1039 // Note: don't reorder arithmetic concerning pointers, as we must ensure that
1040 // no intermediate computations are invalid pointers.
1041 (ADD <t> a p:(ADDconst [c] m:((MUL|MULW|MNEG|MNEGW) _ _))) && p.Uses==1 && m.Uses==1 && !t.IsPtrShaped() => (ADDconst [c] (ADD <v.Type> a m))
1042 (ADD <t> a p:(SUBconst [c] m:((MUL|MULW|MNEG|MNEGW) _ _))) && p.Uses==1 && m.Uses==1 && !t.IsPtrShaped() => (SUBconst [c] (ADD <v.Type> a m))
1043 (SUB <t> a p:(ADDconst [c] m:((MUL|MULW|MNEG|MNEGW) _ _))) && p.Uses==1 && m.Uses==1 && !t.IsPtrShaped() => (SUBconst [c] (SUB <v.Type> a m))
1044 (SUB <t> a p:(SUBconst [c] m:((MUL|MULW|MNEG|MNEGW) _ _))) && p.Uses==1 && m.Uses==1 && !t.IsPtrShaped() => (ADDconst [c] (SUB <v.Type> a m))
1045
1046 // optimize ADCSflags, SBCSflags and friends
1047 (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (ADCzerocarry <typ.UInt64> c)))) => (ADCSflags x y c)
1048 (ADCSflags x y (Select1 <types.TypeFlags> (ADDSconstflags [-1] (MOVDconst [0])))) => (ADDSflags x y)
1049 (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags (NEG <typ.UInt64> (NGCzerocarry <typ.UInt64> bo))))) => (SBCSflags x y bo)
1050 (SBCSflags x y (Select1 <types.TypeFlags> (NEGSflags (MOVDconst [0])))) => (SUBSflags x y)
1051
1052 // mul by constant
1053 (MUL _ (MOVDconst [0])) => (MOVDconst [0])
1054 (MUL x (MOVDconst [1])) => x
1055
1056 (MULW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0])
1057 (MULW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg x)
1058
1059 (MUL x (MOVDconst [c])) && canMulStrengthReduce(config, c) => {mulStrengthReduce(v, x, c)}
1060 (MULW x (MOVDconst [c])) && v.Type.Size() <= 4 && canMulStrengthReduce32(config, int32(c)) => {mulStrengthReduce32(v, x, int32(c))}
1061
1062 // mneg by constant
1063 (MNEG x (MOVDconst [-1])) => x
1064 (MNEG _ (MOVDconst [0])) => (MOVDconst [0])
1065 (MNEG x (MOVDconst [1])) => (NEG x)
1066 (MNEG x (MOVDconst [c])) && isPowerOfTwo(c) => (NEG (SLLconst <x.Type> [log64(c)] x))
1067 (MNEG x (MOVDconst [c])) && isPowerOfTwo(c-1) && c >= 3 => (NEG (ADDshiftLL <x.Type> x x [log64(c-1)]))
1068 (MNEG x (MOVDconst [c])) && isPowerOfTwo(c+1) && c >= 7 => (NEG (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)]))
1069 (MNEG x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) => (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2]))
1070 (MNEG x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) => (NEG (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2])))
1071 (MNEG x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) => (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3]))
1072 (MNEG x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) => (NEG (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3])))
1073
1074
1075 (MNEGW x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg x)
1076 (MNEGW _ (MOVDconst [c])) && int32(c)==0 => (MOVDconst [0])
1077 (MNEGW x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (NEG <x.Type> x))
1078 (MNEGW x (MOVDconst [c])) && isPowerOfTwo(c) => (NEG (SLLconst <x.Type> [log64(c)] x))
1079 (MNEGW x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c) >= 3 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> x x [log64(c-1)])))
1080 (MNEGW x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c) >= 7 => (MOVWUreg (NEG <x.Type> (ADDshiftLL <x.Type> (NEG <x.Type> x) x [log64(c+1)])))
1081 (MNEGW x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/3)] (SUBshiftLL <x.Type> x x [2])))
1082 (MNEGW x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/5)] (ADDshiftLL <x.Type> x x [2]))))
1083 (MNEGW x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (SLLconst <x.Type> [log64(c/7)] (SUBshiftLL <x.Type> x x [3])))
1084 (MNEGW x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (NEG <x.Type> (SLLconst <x.Type> [log64(c/9)] (ADDshiftLL <x.Type> x x [3]))))
1085
1086
1087 (MADD a x (MOVDconst [-1])) => (SUB a x)
1088 (MADD a _ (MOVDconst [0])) => a
1089 (MADD a x (MOVDconst [1])) => (ADD a x)
1090 (MADD a x (MOVDconst [c])) && isPowerOfTwo(c) => (ADDshiftLL a x [log64(c)])
1091 (MADD a x (MOVDconst [c])) && isPowerOfTwo(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
1092 (MADD a x (MOVDconst [c])) && isPowerOfTwo(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
1093 (MADD a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
1094 (MADD a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
1095 (MADD a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
1096 (MADD a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
1097
1098 (MADD a (MOVDconst [-1]) x) => (SUB a x)
1099 (MADD a (MOVDconst [0]) _) => a
1100 (MADD a (MOVDconst [1]) x) => (ADD a x)
1101 (MADD a (MOVDconst [c]) x) && isPowerOfTwo(c) => (ADDshiftLL a x [log64(c)])
1102 (MADD a (MOVDconst [c]) x) && isPowerOfTwo(c-1) && c>=3 => (ADD a (ADDshiftLL <x.Type> x x [log64(c-1)]))
1103 (MADD a (MOVDconst [c]) x) && isPowerOfTwo(c+1) && c>=7 => (SUB a (SUBshiftLL <x.Type> x x [log64(c+1)]))
1104 (MADD a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
1105 (MADD a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
1106 (MADD a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) => (SUBshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
1107 (MADD a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) => (ADDshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
1108
1109 (MADDW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x))
1110 (MADDW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a)
1111 (MADDW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x))
1112 (MADDW a x (MOVDconst [c])) && isPowerOfTwo(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)]))
1113 (MADDW a x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
1114 (MADDW a x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
1115 (MADDW a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
1116 (MADDW a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
1117 (MADDW a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
1118 (MADDW a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
1119
1120 (MADDW a (MOVDconst [c]) x) && int32(c)==-1 => (MOVWUreg (SUB <a.Type> a x))
1121 (MADDW a (MOVDconst [c]) _) && int32(c)==0 => (MOVWUreg a)
1122 (MADDW a (MOVDconst [c]) x) && int32(c)==1 => (MOVWUreg (ADD <a.Type> a x))
1123 (MADDW a (MOVDconst [c]) x) && isPowerOfTwo(c) => (MOVWUreg (ADDshiftLL <a.Type> a x [log64(c)]))
1124 (MADDW a (MOVDconst [c]) x) && isPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (ADD <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
1125 (MADDW a (MOVDconst [c]) x) && isPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (SUB <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
1126 (MADDW a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
1127 (MADDW a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
1128 (MADDW a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
1129 (MADDW a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
1130
1131 (MSUB a x (MOVDconst [-1])) => (ADD a x)
1132 (MSUB a _ (MOVDconst [0])) => a
1133 (MSUB a x (MOVDconst [1])) => (SUB a x)
1134 (MSUB a x (MOVDconst [c])) && isPowerOfTwo(c) => (SUBshiftLL a x [log64(c)])
1135 (MSUB a x (MOVDconst [c])) && isPowerOfTwo(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)]))
1136 (MSUB a x (MOVDconst [c])) && isPowerOfTwo(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)]))
1137 (MSUB a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
1138 (MSUB a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
1139 (MSUB a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
1140 (MSUB a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
1141
1142 (MSUB a (MOVDconst [-1]) x) => (ADD a x)
1143 (MSUB a (MOVDconst [0]) _) => a
1144 (MSUB a (MOVDconst [1]) x) => (SUB a x)
1145 (MSUB a (MOVDconst [c]) x) && isPowerOfTwo(c) => (SUBshiftLL a x [log64(c)])
1146 (MSUB a (MOVDconst [c]) x) && isPowerOfTwo(c-1) && c>=3 => (SUB a (ADDshiftLL <x.Type> x x [log64(c-1)]))
1147 (MSUB a (MOVDconst [c]) x) && isPowerOfTwo(c+1) && c>=7 => (ADD a (SUBshiftLL <x.Type> x x [log64(c+1)]))
1148 (MSUB a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)])
1149 (MSUB a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)])
1150 (MSUB a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) => (ADDshiftLL a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)])
1151 (MSUB a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) => (SUBshiftLL a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)])
1152
1153 (MSUBW a x (MOVDconst [c])) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x))
1154 (MSUBW a _ (MOVDconst [c])) && int32(c)==0 => (MOVWUreg a)
1155 (MSUBW a x (MOVDconst [c])) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x))
1156 (MSUBW a x (MOVDconst [c])) && isPowerOfTwo(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))
1157 (MSUBW a x (MOVDconst [c])) && isPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
1158 (MSUBW a x (MOVDconst [c])) && isPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
1159 (MSUBW a x (MOVDconst [c])) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
1160 (MSUBW a x (MOVDconst [c])) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
1161 (MSUBW a x (MOVDconst [c])) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
1162 (MSUBW a x (MOVDconst [c])) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
1163
1164 (MSUBW a (MOVDconst [c]) x) && int32(c)==-1 => (MOVWUreg (ADD <a.Type> a x))
1165 (MSUBW a (MOVDconst [c]) _) && int32(c)==0 => (MOVWUreg a)
1166 (MSUBW a (MOVDconst [c]) x) && int32(c)==1 => (MOVWUreg (SUB <a.Type> a x))
1167 (MSUBW a (MOVDconst [c]) x) && isPowerOfTwo(c) => (MOVWUreg (SUBshiftLL <a.Type> a x [log64(c)]))
1168 (MSUBW a (MOVDconst [c]) x) && isPowerOfTwo(c-1) && int32(c)>=3 => (MOVWUreg (SUB <a.Type> a (ADDshiftLL <x.Type> x x [log64(c-1)])))
1169 (MSUBW a (MOVDconst [c]) x) && isPowerOfTwo(c+1) && int32(c)>=7 => (MOVWUreg (ADD <a.Type> a (SUBshiftLL <x.Type> x x [log64(c+1)])))
1170 (MSUBW a (MOVDconst [c]) x) && c%3 == 0 && isPowerOfTwo(c/3) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [2]) [log64(c/3)]))
1171 (MSUBW a (MOVDconst [c]) x) && c%5 == 0 && isPowerOfTwo(c/5) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [2]) [log64(c/5)]))
1172 (MSUBW a (MOVDconst [c]) x) && c%7 == 0 && isPowerOfTwo(c/7) && is32Bit(c) => (MOVWUreg (ADDshiftLL <a.Type> a (SUBshiftLL <x.Type> x x [3]) [log64(c/7)]))
1173 (MSUBW a (MOVDconst [c]) x) && c%9 == 0 && isPowerOfTwo(c/9) && is32Bit(c) => (MOVWUreg (SUBshiftLL <a.Type> a (ADDshiftLL <x.Type> x x [3]) [log64(c/9)]))
1174
1175 // div by constant
1176 (UDIV x (MOVDconst [1])) => x
1177 (UDIV x (MOVDconst [c])) && isPowerOfTwo(c) => (SRLconst [log64(c)] x)
1178 (UDIVW x (MOVDconst [c])) && uint32(c)==1 => (MOVWUreg x)
1179 (UDIVW x (MOVDconst [c])) && isPowerOfTwo(c) && is32Bit(c) => (SRLconst [log64(c)] (MOVWUreg <v.Type> x))
1180 (UMOD _ (MOVDconst [1])) => (MOVDconst [0])
1181 (UMOD x (MOVDconst [c])) && isPowerOfTwo(c) => (ANDconst [c-1] x)
1182 (UMODW _ (MOVDconst [c])) && uint32(c)==1 => (MOVDconst [0])
1183 (UMODW x (MOVDconst [c])) && isPowerOfTwo(c) && is32Bit(c) => (ANDconst [c-1] x)
1184
1185 // generic simplifications
1186 (ADD x (NEG y)) => (SUB x y)
1187 (SUB x (NEG y)) => (ADD x y)
1188 (SUB x x) => (MOVDconst [0])
1189 (AND x x) => x
1190 (OR x x) => x
1191 (XOR x x) => (MOVDconst [0])
1192 (BIC x x) => (MOVDconst [0])
1193 (EON x x) => (MOVDconst [-1])
1194 (ORN x x) => (MOVDconst [-1])
1195 (AND x (MVN y)) => (BIC x y)
1196 (XOR x (MVN y)) => (EON x y)
1197 (OR x (MVN y)) => (ORN x y)
1198 (MVN (XOR x y)) => (EON x y)
1199 (NEG (SUB x y)) => (SUB y x)
1200 (NEG (NEG x)) => x
1201
1202 (CSEL [cc] (MOVDconst [-1]) (MOVDconst [0]) flag) => (CSETM [cc] flag)
1203 (CSEL [cc] (MOVDconst [0]) (MOVDconst [-1]) flag) => (CSETM [arm64Negate(cc)] flag)
1204 (CSEL [cc] x (MOVDconst [0]) flag) => (CSEL0 [cc] x flag)
1205 (CSEL [cc] (MOVDconst [0]) y flag) => (CSEL0 [arm64Negate(cc)] y flag)
1206 (CSEL [cc] x (ADDconst [1] a) flag) => (CSINC [cc] x a flag)
1207 (CSEL [cc] (ADDconst [1] a) x flag) => (CSINC [arm64Negate(cc)] x a flag)
1208 (CSEL [cc] x (MVN a) flag) => (CSINV [cc] x a flag)
1209 (CSEL [cc] (MVN a) x flag) => (CSINV [arm64Negate(cc)] x a flag)
1210 (CSEL [cc] x (NEG a) flag) => (CSNEG [cc] x a flag)
1211 (CSEL [cc] (NEG a) x flag) => (CSNEG [arm64Negate(cc)] x a flag)
1212
1213 (SUB x (SUB y z)) => (SUB (ADD <v.Type> x z) y)
1214 (SUB (SUB x y) z) => (SUB x (ADD <y.Type> y z))
1215
1216 // remove redundant *const ops
1217 (ADDconst [0] x) => x
1218 (SUBconst [0] x) => x
1219 (ANDconst [0] _) => (MOVDconst [0])
1220 (ANDconst [-1] x) => x
1221 (ORconst [0] x) => x
1222 (ORconst [-1] _) => (MOVDconst [-1])
1223 (XORconst [0] x) => x
1224 (XORconst [-1] x) => (MVN x)
1225
1226 // generic constant folding
1227 (ADDconst [c] (MOVDconst [d])) => (MOVDconst [c+d])
1228 (ADDconst [c] (ADDconst [d] x)) => (ADDconst [c+d] x)
1229 (ADDconst [c] (SUBconst [d] x)) => (ADDconst [c-d] x)
1230 (SUBconst [c] (MOVDconst [d])) => (MOVDconst [d-c])
1231 (SUBconst [c] (SUBconst [d] x)) => (ADDconst [-c-d] x)
1232 (SUBconst [c] (ADDconst [d] x)) => (ADDconst [-c+d] x)
1233 (SLLconst [c] (MOVDconst [d])) => (MOVDconst [d<<uint64(c)])
1234 (SRLconst [c] (MOVDconst [d])) => (MOVDconst [int64(uint64(d)>>uint64(c))])
1235 (SRAconst [c] (MOVDconst [d])) => (MOVDconst [d>>uint64(c)])
1236 (MUL (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [c*d])
1237 (MNEG (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [-c*d])
1238 (MULW (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [int64(uint32(c*d))])
1239 (MNEGW (MOVDconst [c]) (MOVDconst [d])) => (MOVDconst [int64(uint32(-c*d))])
1240 (MADD (MOVDconst [c]) x y) => (ADDconst [c] (MUL <x.Type> x y))
1241 (MSUB (MOVDconst [c]) x y) => (ADDconst [c] (MNEG <x.Type> x y))
1242 (MADD a (MOVDconst [c]) (MOVDconst [d])) => (ADDconst [c*d] a)
1243 (MSUB a (MOVDconst [c]) (MOVDconst [d])) => (SUBconst [c*d] a)
1244 (MADDW (MOVDconst [c]) x y) => (MOVWUreg (ADDconst <x.Type> [c] (MULW <x.Type> x y)))
1245 (MSUBW (MOVDconst [c]) x y) => (MOVWUreg (ADDconst <x.Type> [c] (MNEGW <x.Type> x y)))
1246 (MADDW a (MOVDconst [c]) (MOVDconst [d])) => (MOVWUreg (ADDconst <a.Type> [c*d] a))
1247 (MSUBW a (MOVDconst [c]) (MOVDconst [d])) => (MOVWUreg (SUBconst <a.Type> [c*d] a))
1248 (DIV (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [c/d])
1249 (UDIV (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint64(c)/uint64(d))])
1250 (DIVW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(int32(c)/int32(d)))])
1251 (UDIVW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(c)/uint32(d))])
1252 (MOD (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [c%d])
1253 (UMOD (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint64(c)%uint64(d))])
1254 (MODW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(int32(c)%int32(d)))])
1255 (UMODW (MOVDconst [c]) (MOVDconst [d])) && d != 0 => (MOVDconst [int64(uint32(c)%uint32(d))])
1256 (ANDconst [c] (MOVDconst [d])) => (MOVDconst [c&d])
1257 (ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x)
1258 (ANDconst [c] (MOVWUreg x)) => (ANDconst [c&(1<<32-1)] x)
1259 (ANDconst [c] (MOVHUreg x)) => (ANDconst [c&(1<<16-1)] x)
1260 (ANDconst [c] (MOVBUreg x)) => (ANDconst [c&(1<<8-1)] x)
1261 (MOVWUreg (ANDconst [c] x)) => (ANDconst [c&(1<<32-1)] x)
1262 (MOVHUreg (ANDconst [c] x)) => (ANDconst [c&(1<<16-1)] x)
1263 (MOVBUreg (ANDconst [c] x)) => (ANDconst [c&(1<<8-1)] x)
1264 (ORconst [c] (MOVDconst [d])) => (MOVDconst [c|d])
1265 (ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x)
1266 (XORconst [c] (MOVDconst [d])) => (MOVDconst [c^d])
1267 (XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x)
1268 (MVN (MOVDconst [c])) => (MOVDconst [^c])
1269 (NEG (MOVDconst [c])) => (MOVDconst [-c])
1270 (MOVBreg (MOVDconst [c])) => (MOVDconst [int64(int8(c))])
1271 (MOVBUreg (MOVDconst [c])) => (MOVDconst [int64(uint8(c))])
1272 (MOVHreg (MOVDconst [c])) => (MOVDconst [int64(int16(c))])
1273 (MOVHUreg (MOVDconst [c])) => (MOVDconst [int64(uint16(c))])
1274 (MOVWreg (MOVDconst [c])) => (MOVDconst [int64(int32(c))])
1275 (MOVWUreg (MOVDconst [c])) => (MOVDconst [int64(uint32(c))])
1276 (MOVDreg (MOVDconst [c])) => (MOVDconst [c])
1277
1278 // constant comparisons
1279 (CMPconst (MOVDconst [x]) [y]) => (FlagConstant [subFlags64(x,y)])
1280 (CMPWconst (MOVDconst [x]) [y]) => (FlagConstant [subFlags32(int32(x),y)])
1281 (TSTconst (MOVDconst [x]) [y]) => (FlagConstant [logicFlags64(x&y)])
1282 (TSTWconst (MOVDconst [x]) [y]) => (FlagConstant [logicFlags32(int32(x)&y)])
1283 (CMNconst (MOVDconst [x]) [y]) => (FlagConstant [addFlags64(x,y)])
1284 (CMNWconst (MOVDconst [x]) [y]) => (FlagConstant [addFlags32(int32(x),y)])
1285
1286 // other known comparisons
1287 (CMPconst (MOVBUreg _) [c]) && 0xff < c => (FlagConstant [subFlags64(0,1)])
1288 (CMPconst (MOVHUreg _) [c]) && 0xffff < c => (FlagConstant [subFlags64(0,1)])
1289 (CMPconst (MOVWUreg _) [c]) && 0xffffffff < c => (FlagConstant [subFlags64(0,1)])
1290 (CMPconst (ANDconst _ [m]) [n]) && 0 <= m && m < n => (FlagConstant [subFlags64(0,1)])
1291 (CMPconst (SRLconst _ [c]) [n]) && 0 <= n && 0 < c && c <= 63 && (1<<uint64(64-c)) <= uint64(n) => (FlagConstant [subFlags64(0,1)])
1292 (CMPWconst (MOVBUreg _) [c]) && 0xff < c => (FlagConstant [subFlags64(0,1)])
1293 (CMPWconst (MOVHUreg _) [c]) && 0xffff < c => (FlagConstant [subFlags64(0,1)])
1294
1295 // absorb flag constants into branches
1296 (EQ (FlagConstant [fc]) yes no) && fc.eq() => (First yes no)
1297 (EQ (FlagConstant [fc]) yes no) && !fc.eq() => (First no yes)
1298
1299 (NE (FlagConstant [fc]) yes no) && fc.ne() => (First yes no)
1300 (NE (FlagConstant [fc]) yes no) && !fc.ne() => (First no yes)
1301
1302 (LT (FlagConstant [fc]) yes no) && fc.lt() => (First yes no)
1303 (LT (FlagConstant [fc]) yes no) && !fc.lt() => (First no yes)
1304
1305 (LE (FlagConstant [fc]) yes no) && fc.le() => (First yes no)
1306 (LE (FlagConstant [fc]) yes no) && !fc.le() => (First no yes)
1307
1308 (GT (FlagConstant [fc]) yes no) && fc.gt() => (First yes no)
1309 (GT (FlagConstant [fc]) yes no) && !fc.gt() => (First no yes)
1310
1311 (GE (FlagConstant [fc]) yes no) && fc.ge() => (First yes no)
1312 (GE (FlagConstant [fc]) yes no) && !fc.ge() => (First no yes)
1313
1314 (ULT (FlagConstant [fc]) yes no) && fc.ult() => (First yes no)
1315 (ULT (FlagConstant [fc]) yes no) && !fc.ult() => (First no yes)
1316
1317 (ULE (FlagConstant [fc]) yes no) && fc.ule() => (First yes no)
1318 (ULE (FlagConstant [fc]) yes no) && !fc.ule() => (First no yes)
1319
1320 (UGT (FlagConstant [fc]) yes no) && fc.ugt() => (First yes no)
1321 (UGT (FlagConstant [fc]) yes no) && !fc.ugt() => (First no yes)
1322
1323 (UGE (FlagConstant [fc]) yes no) && fc.uge() => (First yes no)
1324 (UGE (FlagConstant [fc]) yes no) && !fc.uge() => (First no yes)
1325
1326 (LTnoov (FlagConstant [fc]) yes no) && fc.ltNoov() => (First yes no)
1327 (LTnoov (FlagConstant [fc]) yes no) && !fc.ltNoov() => (First no yes)
1328
1329 (LEnoov (FlagConstant [fc]) yes no) && fc.leNoov() => (First yes no)
1330 (LEnoov (FlagConstant [fc]) yes no) && !fc.leNoov() => (First no yes)
1331
1332 (GTnoov (FlagConstant [fc]) yes no) && fc.gtNoov() => (First yes no)
1333 (GTnoov (FlagConstant [fc]) yes no) && !fc.gtNoov() => (First no yes)
1334
1335 (GEnoov (FlagConstant [fc]) yes no) && fc.geNoov() => (First yes no)
1336 (GEnoov (FlagConstant [fc]) yes no) && !fc.geNoov() => (First no yes)
1337
1338 (Z (MOVDconst [0]) yes no) => (First yes no)
1339 (Z (MOVDconst [c]) yes no) && c != 0 => (First no yes)
1340 (NZ (MOVDconst [0]) yes no) => (First no yes)
1341 (NZ (MOVDconst [c]) yes no) && c != 0 => (First yes no)
1342 (ZW (MOVDconst [c]) yes no) && int32(c) == 0 => (First yes no)
1343 (ZW (MOVDconst [c]) yes no) && int32(c) != 0 => (First no yes)
1344 (NZW (MOVDconst [c]) yes no) && int32(c) == 0 => (First no yes)
1345 (NZW (MOVDconst [c]) yes no) && int32(c) != 0 => (First yes no)
1346
1347 // absorb InvertFlags into branches
1348 (LT (InvertFlags cmp) yes no) => (GT cmp yes no)
1349 (GT (InvertFlags cmp) yes no) => (LT cmp yes no)
1350 (LE (InvertFlags cmp) yes no) => (GE cmp yes no)
1351 (GE (InvertFlags cmp) yes no) => (LE cmp yes no)
1352 (ULT (InvertFlags cmp) yes no) => (UGT cmp yes no)
1353 (UGT (InvertFlags cmp) yes no) => (ULT cmp yes no)
1354 (ULE (InvertFlags cmp) yes no) => (UGE cmp yes no)
1355 (UGE (InvertFlags cmp) yes no) => (ULE cmp yes no)
1356 (EQ (InvertFlags cmp) yes no) => (EQ cmp yes no)
1357 (NE (InvertFlags cmp) yes no) => (NE cmp yes no)
1358 (FLT (InvertFlags cmp) yes no) => (FGT cmp yes no)
1359 (FGT (InvertFlags cmp) yes no) => (FLT cmp yes no)
1360 (FLE (InvertFlags cmp) yes no) => (FGE cmp yes no)
1361 (FGE (InvertFlags cmp) yes no) => (FLE cmp yes no)
1362
1363 // absorb InvertFlags into conditional instructions
1364 (CSEL [cc] x y (InvertFlags cmp)) => (CSEL [arm64Invert(cc)] x y cmp)
1365 (CSEL0 [cc] x (InvertFlags cmp)) => (CSEL0 [arm64Invert(cc)] x cmp)
1366 (CSETM [cc] (InvertFlags cmp)) => (CSETM [arm64Invert(cc)] cmp)
1367 (CSINC [cc] x y (InvertFlags cmp)) => (CSINC [arm64Invert(cc)] x y cmp)
1368 (CSINV [cc] x y (InvertFlags cmp)) => (CSINV [arm64Invert(cc)] x y cmp)
1369 (CSNEG [cc] x y (InvertFlags cmp)) => (CSNEG [arm64Invert(cc)] x y cmp)
1370
1371 // absorb flag constants into boolean values
1372 (Equal (FlagConstant [fc])) => (MOVDconst [b2i(fc.eq())])
1373 (NotEqual (FlagConstant [fc])) => (MOVDconst [b2i(fc.ne())])
1374 (LessThan (FlagConstant [fc])) => (MOVDconst [b2i(fc.lt())])
1375 (LessThanU (FlagConstant [fc])) => (MOVDconst [b2i(fc.ult())])
1376 (LessEqual (FlagConstant [fc])) => (MOVDconst [b2i(fc.le())])
1377 (LessEqualU (FlagConstant [fc])) => (MOVDconst [b2i(fc.ule())])
1378 (GreaterThan (FlagConstant [fc])) => (MOVDconst [b2i(fc.gt())])
1379 (GreaterThanU (FlagConstant [fc])) => (MOVDconst [b2i(fc.ugt())])
1380 (GreaterEqual (FlagConstant [fc])) => (MOVDconst [b2i(fc.ge())])
1381 (GreaterEqualU (FlagConstant [fc])) => (MOVDconst [b2i(fc.uge())])
1382 (LessThanNoov (FlagConstant [fc])) => (MOVDconst [b2i(fc.ltNoov())])
1383 (GreaterEqualNoov (FlagConstant [fc])) => (MOVDconst [b2i(fc.geNoov())])
1384
1385 // absorb InvertFlags into boolean values
1386 (Equal (InvertFlags x)) => (Equal x)
1387 (NotEqual (InvertFlags x)) => (NotEqual x)
1388 (LessThan (InvertFlags x)) => (GreaterThan x)
1389 (LessThanU (InvertFlags x)) => (GreaterThanU x)
1390 (GreaterThan (InvertFlags x)) => (LessThan x)
1391 (GreaterThanU (InvertFlags x)) => (LessThanU x)
1392 (LessEqual (InvertFlags x)) => (GreaterEqual x)
1393 (LessEqualU (InvertFlags x)) => (GreaterEqualU x)
1394 (GreaterEqual (InvertFlags x)) => (LessEqual x)
1395 (GreaterEqualU (InvertFlags x)) => (LessEqualU x)
1396 (LessThanF (InvertFlags x)) => (GreaterThanF x)
1397 (LessEqualF (InvertFlags x)) => (GreaterEqualF x)
1398 (GreaterThanF (InvertFlags x)) => (LessThanF x)
1399 (GreaterEqualF (InvertFlags x)) => (LessEqualF x)
1400
1401 (GreaterEqual (CMPconst x [0])) => (XORconst [1] (SRLconst <v.Type> [63] x))
1402 (LessThan (CMPconst x [0])) => (SRLconst [63] x)
1403 (GreaterEqual (CMPWconst x [0])) => (XORconst [1] (UBFX <v.Type> [armBFAuxInt(31,1)] x))
1404 (LessThan (CMPWconst x [0])) => (UBFX [armBFAuxInt(31,1)] x)
1405
1406 // Don't bother extending if we're not using the higher bits.
1407 (MOV(B|BU)reg x) && v.Type.Size() <= 1 => x
1408 (MOV(H|HU)reg x) && v.Type.Size() <= 2 => x
1409 (MOV(W|WU)reg x) && v.Type.Size() <= 4 => x
1410
1411 // omit sign extension
1412 (MOVWreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffff80000000) == 0 => (ANDconst <t> x [c])
1413 (MOVHreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffff8000) == 0 => (ANDconst <t> x [c])
1414 (MOVBreg <t> (ANDconst x [c])) && uint64(c) & uint64(0xffffffffffffff80) == 0 => (ANDconst <t> x [c])
1415
1416 // absorb flag constants into conditional instructions
1417 (CSEL [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
1418 (CSEL [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => y
1419 (CSEL0 [cc] x flag) && ccARM64Eval(cc, flag) > 0 => x
1420 (CSEL0 [cc] _ flag) && ccARM64Eval(cc, flag) < 0 => (MOVDconst [0])
1421 (CSNEG [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
1422 (CSNEG [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (NEG y)
1423 (CSINV [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
1424 (CSINV [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (Not y)
1425 (CSINC [cc] x _ flag) && ccARM64Eval(cc, flag) > 0 => x
1426 (CSINC [cc] _ y flag) && ccARM64Eval(cc, flag) < 0 => (ADDconst [1] y)
1427 (CSETM [cc] flag) && ccARM64Eval(cc, flag) > 0 => (MOVDconst [-1])
1428 (CSETM [cc] flag) && ccARM64Eval(cc, flag) < 0 => (MOVDconst [0])
1429
1430 // absorb flags back into boolean CSEL
1431 (CSEL [cc] x y (CMPWconst [0] boolval)) && cc == OpARM64NotEqual && flagArg(boolval) != nil =>
1432 (CSEL [boolval.Op] x y flagArg(boolval))
1433 (CSEL [cc] x y (CMPWconst [0] boolval)) && cc == OpARM64Equal && flagArg(boolval) != nil =>
1434 (CSEL [arm64Negate(boolval.Op)] x y flagArg(boolval))
1435 (CSEL0 [cc] x (CMPWconst [0] boolval)) && cc == OpARM64NotEqual && flagArg(boolval) != nil =>
1436 (CSEL0 [boolval.Op] x flagArg(boolval))
1437 (CSEL0 [cc] x (CMPWconst [0] boolval)) && cc == OpARM64Equal && flagArg(boolval) != nil =>
1438 (CSEL0 [arm64Negate(boolval.Op)] x flagArg(boolval))
1439
1440 // absorb shifts into ops
1441 (NEG x:(SLLconst [c] y)) && clobberIfDead(x) => (NEGshiftLL [c] y)
1442 (NEG x:(SRLconst [c] y)) && clobberIfDead(x) => (NEGshiftRL [c] y)
1443 (NEG x:(SRAconst [c] y)) && clobberIfDead(x) => (NEGshiftRA [c] y)
1444 (MVN x:(SLLconst [c] y)) && clobberIfDead(x) => (MVNshiftLL [c] y)
1445 (MVN x:(SRLconst [c] y)) && clobberIfDead(x) => (MVNshiftRL [c] y)
1446 (MVN x:(SRAconst [c] y)) && clobberIfDead(x) => (MVNshiftRA [c] y)
1447 (MVN x:(RORconst [c] y)) && clobberIfDead(x) => (MVNshiftRO [c] y)
1448 (ADD x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ADDshiftLL x0 y [c])
1449 (ADD x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ADDshiftRL x0 y [c])
1450 (ADD x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ADDshiftRA x0 y [c])
1451 (SUB x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (SUBshiftLL x0 y [c])
1452 (SUB x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (SUBshiftRL x0 y [c])
1453 (SUB x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (SUBshiftRA x0 y [c])
1454 (AND x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ANDshiftLL x0 y [c])
1455 (AND x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ANDshiftRL x0 y [c])
1456 (AND x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ANDshiftRA x0 y [c])
1457 (AND x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (ANDshiftRO x0 y [c])
1458 (OR x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ORshiftLL x0 y [c]) // useful for combined load
1459 (OR x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ORshiftRL x0 y [c])
1460 (OR x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ORshiftRA x0 y [c])
1461 (OR x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (ORshiftRO x0 y [c])
1462 (XOR x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (XORshiftLL x0 y [c])
1463 (XOR x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (XORshiftRL x0 y [c])
1464 (XOR x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (XORshiftRA x0 y [c])
1465 (XOR x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (XORshiftRO x0 y [c])
1466 (BIC x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (BICshiftLL x0 y [c])
1467 (BIC x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (BICshiftRL x0 y [c])
1468 (BIC x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (BICshiftRA x0 y [c])
1469 (BIC x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (BICshiftRO x0 y [c])
1470 (ORN x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (ORNshiftLL x0 y [c])
1471 (ORN x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (ORNshiftRL x0 y [c])
1472 (ORN x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (ORNshiftRA x0 y [c])
1473 (ORN x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (ORNshiftRO x0 y [c])
1474 (EON x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (EONshiftLL x0 y [c])
1475 (EON x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (EONshiftRL x0 y [c])
1476 (EON x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (EONshiftRA x0 y [c])
1477 (EON x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (EONshiftRO x0 y [c])
1478 (CMP x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (CMPshiftLL x0 y [c])
1479 (CMP x0:(SLLconst [c] y) x1) && clobberIfDead(x0) => (InvertFlags (CMPshiftLL x1 y [c]))
1480 (CMP x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (CMPshiftRL x0 y [c])
1481 (CMP x0:(SRLconst [c] y) x1) && clobberIfDead(x0) => (InvertFlags (CMPshiftRL x1 y [c]))
1482 (CMP x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (CMPshiftRA x0 y [c])
1483 (CMP x0:(SRAconst [c] y) x1) && clobberIfDead(x0) => (InvertFlags (CMPshiftRA x1 y [c]))
1484 (CMN x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (CMNshiftLL x0 y [c])
1485 (CMN x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (CMNshiftRL x0 y [c])
1486 (CMN x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (CMNshiftRA x0 y [c])
1487 (TST x0 x1:(SLLconst [c] y)) && clobberIfDead(x1) => (TSTshiftLL x0 y [c])
1488 (TST x0 x1:(SRLconst [c] y)) && clobberIfDead(x1) => (TSTshiftRL x0 y [c])
1489 (TST x0 x1:(SRAconst [c] y)) && clobberIfDead(x1) => (TSTshiftRA x0 y [c])
1490 (TST x0 x1:(RORconst [c] y)) && clobberIfDead(x1) => (TSTshiftRO x0 y [c])
1491
1492 // prefer *const ops to *shift ops
1493 (ADDshiftLL (MOVDconst [c]) x [d]) => (ADDconst [c] (SLLconst <x.Type> x [d]))
1494 (ADDshiftRL (MOVDconst [c]) x [d]) => (ADDconst [c] (SRLconst <x.Type> x [d]))
1495 (ADDshiftRA (MOVDconst [c]) x [d]) => (ADDconst [c] (SRAconst <x.Type> x [d]))
1496 (ANDshiftLL (MOVDconst [c]) x [d]) => (ANDconst [c] (SLLconst <x.Type> x [d]))
1497 (ANDshiftRL (MOVDconst [c]) x [d]) => (ANDconst [c] (SRLconst <x.Type> x [d]))
1498 (ANDshiftRA (MOVDconst [c]) x [d]) => (ANDconst [c] (SRAconst <x.Type> x [d]))
1499 (ANDshiftRO (MOVDconst [c]) x [d]) => (ANDconst [c] (RORconst <x.Type> x [d]))
1500 (ORshiftLL (MOVDconst [c]) x [d]) => (ORconst [c] (SLLconst <x.Type> x [d]))
1501 (ORshiftRL (MOVDconst [c]) x [d]) => (ORconst [c] (SRLconst <x.Type> x [d]))
1502 (ORshiftRA (MOVDconst [c]) x [d]) => (ORconst [c] (SRAconst <x.Type> x [d]))
1503 (ORshiftRO (MOVDconst [c]) x [d]) => (ORconst [c] (RORconst <x.Type> x [d]))
1504 (XORshiftLL (MOVDconst [c]) x [d]) => (XORconst [c] (SLLconst <x.Type> x [d]))
1505 (XORshiftRL (MOVDconst [c]) x [d]) => (XORconst [c] (SRLconst <x.Type> x [d]))
1506 (XORshiftRA (MOVDconst [c]) x [d]) => (XORconst [c] (SRAconst <x.Type> x [d]))
1507 (XORshiftRO (MOVDconst [c]) x [d]) => (XORconst [c] (RORconst <x.Type> x [d]))
1508 (CMPshiftLL (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SLLconst <x.Type> x [d])))
1509 (CMPshiftRL (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SRLconst <x.Type> x [d])))
1510 (CMPshiftRA (MOVDconst [c]) x [d]) => (InvertFlags (CMPconst [c] (SRAconst <x.Type> x [d])))
1511 (CMNshiftLL (MOVDconst [c]) x [d]) => (CMNconst [c] (SLLconst <x.Type> x [d]))
1512 (CMNshiftRL (MOVDconst [c]) x [d]) => (CMNconst [c] (SRLconst <x.Type> x [d]))
1513 (CMNshiftRA (MOVDconst [c]) x [d]) => (CMNconst [c] (SRAconst <x.Type> x [d]))
1514 (TSTshiftLL (MOVDconst [c]) x [d]) => (TSTconst [c] (SLLconst <x.Type> x [d]))
1515 (TSTshiftRL (MOVDconst [c]) x [d]) => (TSTconst [c] (SRLconst <x.Type> x [d]))
1516 (TSTshiftRA (MOVDconst [c]) x [d]) => (TSTconst [c] (SRAconst <x.Type> x [d]))
1517 (TSTshiftRO (MOVDconst [c]) x [d]) => (TSTconst [c] (RORconst <x.Type> x [d]))
1518
1519 // constant folding in *shift ops
1520 (MVNshiftLL (MOVDconst [c]) [d]) => (MOVDconst [^int64(uint64(c)<<uint64(d))])
1521 (MVNshiftRL (MOVDconst [c]) [d]) => (MOVDconst [^int64(uint64(c)>>uint64(d))])
1522 (MVNshiftRA (MOVDconst [c]) [d]) => (MOVDconst [^(c>>uint64(d))])
1523 (MVNshiftRO (MOVDconst [c]) [d]) => (MOVDconst [^rotateRight64(c, d)])
1524 (NEGshiftLL (MOVDconst [c]) [d]) => (MOVDconst [-int64(uint64(c)<<uint64(d))])
1525 (NEGshiftRL (MOVDconst [c]) [d]) => (MOVDconst [-int64(uint64(c)>>uint64(d))])
1526 (NEGshiftRA (MOVDconst [c]) [d]) => (MOVDconst [-(c>>uint64(d))])
1527 (ADDshiftLL x (MOVDconst [c]) [d]) => (ADDconst x [int64(uint64(c)<<uint64(d))])
1528 (ADDshiftRL x (MOVDconst [c]) [d]) => (ADDconst x [int64(uint64(c)>>uint64(d))])
1529 (ADDshiftRA x (MOVDconst [c]) [d]) => (ADDconst x [c>>uint64(d)])
1530 (SUBshiftLL x (MOVDconst [c]) [d]) => (SUBconst x [int64(uint64(c)<<uint64(d))])
1531 (SUBshiftRL x (MOVDconst [c]) [d]) => (SUBconst x [int64(uint64(c)>>uint64(d))])
1532 (SUBshiftRA x (MOVDconst [c]) [d]) => (SUBconst x [c>>uint64(d)])
1533 (ANDshiftLL x (MOVDconst [c]) [d]) => (ANDconst x [int64(uint64(c)<<uint64(d))])
1534 (ANDshiftRL x (MOVDconst [c]) [d]) => (ANDconst x [int64(uint64(c)>>uint64(d))])
1535 (ANDshiftRA x (MOVDconst [c]) [d]) => (ANDconst x [c>>uint64(d)])
1536 (ANDshiftRO x (MOVDconst [c]) [d]) => (ANDconst x [rotateRight64(c, d)])
1537 (ORshiftLL x (MOVDconst [c]) [d]) => (ORconst x [int64(uint64(c)<<uint64(d))])
1538 (ORshiftRL x (MOVDconst [c]) [d]) => (ORconst x [int64(uint64(c)>>uint64(d))])
1539 (ORshiftRA x (MOVDconst [c]) [d]) => (ORconst x [c>>uint64(d)])
1540 (ORshiftRO x (MOVDconst [c]) [d]) => (ORconst x [rotateRight64(c, d)])
1541 (XORshiftLL x (MOVDconst [c]) [d]) => (XORconst x [int64(uint64(c)<<uint64(d))])
1542 (XORshiftRL x (MOVDconst [c]) [d]) => (XORconst x [int64(uint64(c)>>uint64(d))])
1543 (XORshiftRA x (MOVDconst [c]) [d]) => (XORconst x [c>>uint64(d)])
1544 (XORshiftRO x (MOVDconst [c]) [d]) => (XORconst x [rotateRight64(c, d)])
1545 (BICshiftLL x (MOVDconst [c]) [d]) => (ANDconst x [^int64(uint64(c)<<uint64(d))])
1546 (BICshiftRL x (MOVDconst [c]) [d]) => (ANDconst x [^int64(uint64(c)>>uint64(d))])
1547 (BICshiftRA x (MOVDconst [c]) [d]) => (ANDconst x [^(c>>uint64(d))])
1548 (BICshiftRO x (MOVDconst [c]) [d]) => (ANDconst x [^rotateRight64(c, d)])
1549 (ORNshiftLL x (MOVDconst [c]) [d]) => (ORconst x [^int64(uint64(c)<<uint64(d))])
1550 (ORNshiftRL x (MOVDconst [c]) [d]) => (ORconst x [^int64(uint64(c)>>uint64(d))])
1551 (ORNshiftRA x (MOVDconst [c]) [d]) => (ORconst x [^(c>>uint64(d))])
1552 (ORNshiftRO x (MOVDconst [c]) [d]) => (ORconst x [^rotateRight64(c, d)])
1553 (EONshiftLL x (MOVDconst [c]) [d]) => (XORconst x [^int64(uint64(c)<<uint64(d))])
1554 (EONshiftRL x (MOVDconst [c]) [d]) => (XORconst x [^int64(uint64(c)>>uint64(d))])
1555 (EONshiftRA x (MOVDconst [c]) [d]) => (XORconst x [^(c>>uint64(d))])
1556 (EONshiftRO x (MOVDconst [c]) [d]) => (XORconst x [^rotateRight64(c, d)])
1557 (CMPshiftLL x (MOVDconst [c]) [d]) => (CMPconst x [int64(uint64(c)<<uint64(d))])
1558 (CMPshiftRL x (MOVDconst [c]) [d]) => (CMPconst x [int64(uint64(c)>>uint64(d))])
1559 (CMPshiftRA x (MOVDconst [c]) [d]) => (CMPconst x [c>>uint64(d)])
1560 (CMNshiftLL x (MOVDconst [c]) [d]) => (CMNconst x [int64(uint64(c)<<uint64(d))])
1561 (CMNshiftRL x (MOVDconst [c]) [d]) => (CMNconst x [int64(uint64(c)>>uint64(d))])
1562 (CMNshiftRA x (MOVDconst [c]) [d]) => (CMNconst x [c>>uint64(d)])
1563 (TSTshiftLL x (MOVDconst [c]) [d]) => (TSTconst x [int64(uint64(c)<<uint64(d))])
1564 (TSTshiftRL x (MOVDconst [c]) [d]) => (TSTconst x [int64(uint64(c)>>uint64(d))])
1565 (TSTshiftRA x (MOVDconst [c]) [d]) => (TSTconst x [c>>uint64(d)])
1566 (TSTshiftRO x (MOVDconst [c]) [d]) => (TSTconst x [rotateRight64(c, d)])
1567
1568 // simplification with *shift ops
1569 (SUBshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0])
1570 (SUBshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0])
1571 (SUBshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0])
1572 (ANDshiftLL y:(SLLconst x [c]) x [c]) => y
1573 (ANDshiftRL y:(SRLconst x [c]) x [c]) => y
1574 (ANDshiftRA y:(SRAconst x [c]) x [c]) => y
1575 (ANDshiftRO y:(RORconst x [c]) x [c]) => y
1576 (ORshiftLL y:(SLLconst x [c]) x [c]) => y
1577 (ORshiftRL y:(SRLconst x [c]) x [c]) => y
1578 (ORshiftRA y:(SRAconst x [c]) x [c]) => y
1579 (ORshiftRO y:(RORconst x [c]) x [c]) => y
1580 (XORshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0])
1581 (XORshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0])
1582 (XORshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0])
1583 (XORshiftRO (RORconst x [c]) x [c]) => (MOVDconst [0])
1584 (BICshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [0])
1585 (BICshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [0])
1586 (BICshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [0])
1587 (BICshiftRO (RORconst x [c]) x [c]) => (MOVDconst [0])
1588 (EONshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [-1])
1589 (EONshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [-1])
1590 (EONshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [-1])
1591 (EONshiftRO (RORconst x [c]) x [c]) => (MOVDconst [-1])
1592 (ORNshiftLL (SLLconst x [c]) x [c]) => (MOVDconst [-1])
1593 (ORNshiftRL (SRLconst x [c]) x [c]) => (MOVDconst [-1])
1594 (ORNshiftRA (SRAconst x [c]) x [c]) => (MOVDconst [-1])
1595 (ORNshiftRO (RORconst x [c]) x [c]) => (MOVDconst [-1])
1596
1597 // rev16w | rev16
1598 // ((x>>8) | (x<<8)) => (REV16W x), the type of x is uint16, "|" can also be "^" or "+".
1599 ((ADDshiftLL|ORshiftLL|XORshiftLL) <typ.UInt16> [8] (UBFX <typ.UInt16> [armBFAuxInt(8, 8)] x) x) => (REV16W x)
1600
1601 // ((x & 0xff00ff00)>>8) | ((x & 0x00ff00ff)<<8), "|" can also be "^" or "+".
1602 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (UBFX [armBFAuxInt(8, 24)] (ANDconst [c1] x)) (ANDconst [c2] x))
1603 && uint32(c1) == 0xff00ff00 && uint32(c2) == 0x00ff00ff
1604 => (REV16W x)
1605
1606 // ((x & 0xff00ff00ff00ff00)>>8) | ((x & 0x00ff00ff00ff00ff)<<8), "|" can also be "^" or "+".
1607 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x))
1608 && (uint64(c1) == 0xff00ff00ff00ff00 && uint64(c2) == 0x00ff00ff00ff00ff)
1609 => (REV16 x)
1610
1611 // ((x & 0xff00ff00)>>8) | ((x & 0x00ff00ff)<<8), "|" can also be "^" or "+".
1612 ((ADDshiftLL|ORshiftLL|XORshiftLL) [8] (SRLconst [8] (ANDconst [c1] x)) (ANDconst [c2] x))
1613 && (uint64(c1) == 0xff00ff00 && uint64(c2) == 0x00ff00ff)
1614 => (REV16 (ANDconst <x.Type> [0xffffffff] x))
1615
1616 (REV16 (MOVWUreg x)) => (REV16W x)
1617
1618 // Extract from reg pair
1619 (ADDshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x)
1620 ( ORshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x)
1621 (XORshiftLL [c] (SRLconst x [64-c]) x2) => (EXTRconst [64-c] x2 x)
1622
1623 (ADDshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)
1624 => (EXTRWconst [32-c] x2 x)
1625 ( ORshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)
1626 => (EXTRWconst [32-c] x2 x)
1627 (XORshiftLL <t> [c] (UBFX [bfc] x) x2) && c < 32 && t.Size() == 4 && bfc == armBFAuxInt(32-c, c)
1628 => (EXTRWconst [32-c] x2 x)
1629
1630 // Rewrite special pairs of shifts to AND.
1631 // On ARM64 the bitmask can fit into an instruction.
1632 (SRLconst [c] (SLLconst [c] x)) && 0 < c && c < 64 => (ANDconst [1<<uint(64-c)-1] x) // mask out high bits
1633 (SLLconst [c] (SRLconst [c] x)) && 0 < c && c < 64 => (ANDconst [^(1<<uint(c)-1)] x) // mask out low bits
1634
1635 // Special case setting bit as 1. An example is math.Copysign(c,-1)
1636 (ORconst [c1] (ANDconst [c2] x)) && c2|c1 == ^0 => (ORconst [c1] x)
1637
1638 // If the shift amount is larger than the datasize(32, 16, 8), we can optimize to constant 0.
1639 (MOVWUreg (SLLconst [lc] x)) && lc >= 32 => (MOVDconst [0])
1640 (MOVHUreg (SLLconst [lc] x)) && lc >= 16 => (MOVDconst [0])
1641 (MOVBUreg (SLLconst [lc] x)) && lc >= 8 => (MOVDconst [0])
1642
1643 // After zero extension, the upper (64-datasize(32|16|8)) bits are zero, we can optimiza to constant 0.
1644 (SRLconst [rc] (MOVWUreg x)) && rc >= 32 => (MOVDconst [0])
1645 (SRLconst [rc] (MOVHUreg x)) && rc >= 16 => (MOVDconst [0])
1646 (SRLconst [rc] (MOVBUreg x)) && rc >= 8 => (MOVDconst [0])
1647
1648 // Special cases for slice operations
1649 (ADD x0 x1:(ANDshiftRA x2:(SLLconst [sl] y) z [63])) && x1.Uses == 1 && x2.Uses == 1 => (ADDshiftLL x0 (ANDshiftRA <y.Type> y z [63]) [sl])
1650 (ADD x0 x1:(ANDshiftLL x2:(SRAconst [63] z) y [sl])) && x1.Uses == 1 && x2.Uses == 1 => (ADDshiftLL x0 (ANDshiftRA <y.Type> y z [63]) [sl])
1651
1652 // bitfield ops
1653
1654 // sbfiz
1655 // (x << lc) >> rc
1656 (SRAconst [rc] (SLLconst [lc] x)) && lc > rc => (SBFIZ [armBFAuxInt(lc-rc, 64-lc)] x)
1657 // int64(x << lc)
1658 (MOVWreg (SLLconst [lc] x)) && lc < 32 => (SBFIZ [armBFAuxInt(lc, 32-lc)] x)
1659 (MOVHreg (SLLconst [lc] x)) && lc < 16 => (SBFIZ [armBFAuxInt(lc, 16-lc)] x)
1660 (MOVBreg (SLLconst [lc] x)) && lc < 8 => (SBFIZ [armBFAuxInt(lc, 8-lc)] x)
1661 // int64(x) << lc
1662 (SLLconst [lc] (MOVWreg x)) => (SBFIZ [armBFAuxInt(lc, min(32, 64-lc))] x)
1663 (SLLconst [lc] (MOVHreg x)) => (SBFIZ [armBFAuxInt(lc, min(16, 64-lc))] x)
1664 (SLLconst [lc] (MOVBreg x)) => (SBFIZ [armBFAuxInt(lc, min(8, 64-lc))] x)
1665
1666 // sbfx
1667 // (x << lc) >> rc
1668 (SRAconst [rc] (SLLconst [lc] x)) && lc <= rc => (SBFX [armBFAuxInt(rc-lc, 64-rc)] x)
1669 // int64(x) >> rc
1670 (SRAconst [rc] (MOVWreg x)) && rc < 32 => (SBFX [armBFAuxInt(rc, 32-rc)] x)
1671 (SRAconst [rc] (MOVHreg x)) && rc < 16 => (SBFX [armBFAuxInt(rc, 16-rc)] x)
1672 (SRAconst [rc] (MOVBreg x)) && rc < 8 => (SBFX [armBFAuxInt(rc, 8-rc)] x)
1673 // merge sbfx and sign-extension into sbfx
1674 (MOVWreg (SBFX [bfc] x)) && bfc.width() <= 32 => (SBFX [bfc] x)
1675 (MOVHreg (SBFX [bfc] x)) && bfc.width() <= 16 => (SBFX [bfc] x)
1676 (MOVBreg (SBFX [bfc] x)) && bfc.width() <= 8 => (SBFX [bfc] x)
1677
1678 // sbfiz/sbfx combinations: merge shifts into bitfield ops
1679 (SRAconst [sc] (SBFIZ [bfc] x)) && sc < bfc.lsb()
1680 => (SBFIZ [armBFAuxInt(bfc.lsb()-sc, bfc.width())] x)
1681 (SRAconst [sc] (SBFIZ [bfc] x)) && sc >= bfc.lsb()
1682 && sc < bfc.lsb()+bfc.width()
1683 => (SBFX [armBFAuxInt(sc-bfc.lsb(), bfc.lsb()+bfc.width()-sc)] x)
1684 (SBFX [bfc] s:(SLLconst [sc] x))
1685 && s.Uses == 1
1686 && sc <= bfc.lsb()
1687 => (SBFX [armBFAuxInt(bfc.lsb() - sc, bfc.width())] x)
1688 (SBFX [bfc] s:(SLLconst [sc] x))
1689 && s.Uses == 1
1690 && sc > bfc.lsb()
1691 && sc < bfc.lsb()+bfc.width()
1692 => (SBFIZ [armBFAuxInt(sc - bfc.lsb(), bfc.width() - (sc-bfc.lsb()))] x)
1693
1694 // ubfiz
1695 // (x << lc) >> rc
1696 (SRLconst [rc] (SLLconst [lc] x)) && lc > rc => (UBFIZ [armBFAuxInt(lc-rc, 64-lc)] x)
1697 // uint64(x) << lc
1698 (SLLconst [lc] (MOVWUreg x)) => (UBFIZ [armBFAuxInt(lc, min(32, 64-lc))] x)
1699 (SLLconst [lc] (MOVHUreg x)) => (UBFIZ [armBFAuxInt(lc, min(16, 64-lc))] x)
1700 (SLLconst [lc] (MOVBUreg x)) => (UBFIZ [armBFAuxInt(lc, min(8, 64-lc))] x)
1701 // uint64(x << lc)
1702 (MOVWUreg (SLLconst [lc] x)) && lc < 32 => (UBFIZ [armBFAuxInt(lc, 32-lc)] x)
1703 (MOVHUreg (SLLconst [lc] x)) && lc < 16 => (UBFIZ [armBFAuxInt(lc, 16-lc)] x)
1704 (MOVBUreg (SLLconst [lc] x)) && lc < 8 => (UBFIZ [armBFAuxInt(lc, 8-lc)] x)
1705
1706 // merge ANDconst into ubfiz
1707 // (x & ac) << sc
1708 (SLLconst [sc] (ANDconst [ac] x)) && isARM64BFMask(sc, ac, 0)
1709 => (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x)
1710 // (x << sc) & ac
1711 (ANDconst [ac] (SLLconst [sc] x)) && isARM64BFMask(sc, ac, sc)
1712 => (UBFIZ [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x)
1713
1714 // ubfx
1715 // (x << lc) >> rc
1716 (SRLconst [rc] (SLLconst [lc] x)) && lc < rc => (UBFX [armBFAuxInt(rc-lc, 64-rc)] x)
1717 // uint64(x) >> rc
1718 (SRLconst [rc] (MOVWUreg x)) && rc < 32 => (UBFX [armBFAuxInt(rc, 32-rc)] x)
1719 (SRLconst [rc] (MOVHUreg x)) && rc < 16 => (UBFX [armBFAuxInt(rc, 16-rc)] x)
1720 (SRLconst [rc] (MOVBUreg x)) && rc < 8 => (UBFX [armBFAuxInt(rc, 8-rc)] x)
1721 // uint64(x >> rc)
1722 (MOVWUreg (SRLconst [rc] x)) && rc < 32 => (UBFX [armBFAuxInt(rc, 32)] x)
1723 (MOVHUreg (SRLconst [rc] x)) && rc < 16 => (UBFX [armBFAuxInt(rc, 16)] x)
1724 (MOVBUreg (SRLconst [rc] x)) && rc < 8 => (UBFX [armBFAuxInt(rc, 8)] x)
1725 // merge ANDconst into ubfx
1726 // (x >> sc) & ac
1727 (ANDconst [ac] (SRLconst [sc] x)) && isARM64BFMask(sc, ac, 0)
1728 => (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, 0))] x)
1729 // (x & ac) >> sc
1730 (SRLconst [sc] (ANDconst [ac] x)) && isARM64BFMask(sc, ac, sc)
1731 => (UBFX [armBFAuxInt(sc, arm64BFWidth(ac, sc))] x)
1732 // merge ANDconst and ubfx into ubfx
1733 (ANDconst [c] (UBFX [bfc] x)) && isARM64BFMask(0, c, 0) =>
1734 (UBFX [armBFAuxInt(bfc.lsb(), min(bfc.width(), arm64BFWidth(c, 0)))] x)
1735 (UBFX [bfc] (ANDconst [c] x)) && isARM64BFMask(0, c, 0) && bfc.lsb() + bfc.width() <= arm64BFWidth(c, 0) =>
1736 (UBFX [bfc] x)
1737 // merge ubfx and zero-extension into ubfx
1738 (MOVWUreg (UBFX [bfc] x)) && bfc.width() <= 32 => (UBFX [bfc] x)
1739 (MOVHUreg (UBFX [bfc] x)) && bfc.width() <= 16 => (UBFX [bfc] x)
1740 (MOVBUreg (UBFX [bfc] x)) && bfc.width() <= 8 => (UBFX [bfc] x)
1741
1742 // Extracting bits from across a zero-extension boundary.
1743 (UBFX [bfc] e:(MOVWUreg x))
1744 && e.Uses == 1
1745 && bfc.lsb() < 32
1746 => (UBFX [armBFAuxInt(bfc.lsb(), min(bfc.width(), 32-bfc.lsb()))] x)
1747 (UBFX [bfc] e:(MOVHUreg x))
1748 && e.Uses == 1
1749 && bfc.lsb() < 16
1750 => (UBFX [armBFAuxInt(bfc.lsb(), min(bfc.width(), 16-bfc.lsb()))] x)
1751 (UBFX [bfc] e:(MOVBUreg x))
1752 && e.Uses == 1
1753 && bfc.lsb() < 8
1754 => (UBFX [armBFAuxInt(bfc.lsb(), min(bfc.width(), 8-bfc.lsb()))] x)
1755
1756 // ubfiz/ubfx combinations: merge shifts into bitfield ops
1757 (SRLconst [sc] (UBFX [bfc] x)) && sc < bfc.width()
1758 => (UBFX [armBFAuxInt(bfc.lsb()+sc, bfc.width()-sc)] x)
1759 (UBFX [bfc] (SRLconst [sc] x)) && sc+bfc.width()+bfc.lsb() < 64
1760 => (UBFX [armBFAuxInt(bfc.lsb()+sc, bfc.width())] x)
1761 (SLLconst [sc] (UBFIZ [bfc] x)) && sc+bfc.width()+bfc.lsb() < 64
1762 => (UBFIZ [armBFAuxInt(bfc.lsb()+sc, bfc.width())] x)
1763 (UBFIZ [bfc] (SLLconst [sc] x)) && sc < bfc.width()
1764 => (UBFIZ [armBFAuxInt(bfc.lsb()+sc, bfc.width()-sc)] x)
1765 // ((x << c1) >> c2) >> c3
1766 (SRLconst [sc] (UBFIZ [bfc] x)) && sc == bfc.lsb()
1767 => (ANDconst [1<<uint(bfc.width())-1] x)
1768 (SRLconst [sc] (UBFIZ [bfc] x)) && sc < bfc.lsb()
1769 => (UBFIZ [armBFAuxInt(bfc.lsb()-sc, bfc.width())] x)
1770 (SRLconst [sc] (UBFIZ [bfc] x)) && sc > bfc.lsb()
1771 && sc < bfc.lsb()+bfc.width()
1772 => (UBFX [armBFAuxInt(sc-bfc.lsb(), bfc.lsb()+bfc.width()-sc)] x)
1773 // ((x << c1) << c2) >> c3
1774 (UBFX [bfc] (SLLconst [sc] x)) && sc == bfc.lsb()
1775 => (ANDconst [1<<uint(bfc.width())-1] x)
1776 (UBFX [bfc] (SLLconst [sc] x)) && sc < bfc.lsb()
1777 => (UBFX [armBFAuxInt(bfc.lsb()-sc, bfc.width())] x)
1778 (UBFX [bfc] (SLLconst [sc] x)) && sc > bfc.lsb()
1779 && sc < bfc.lsb()+bfc.width()
1780 => (UBFIZ [armBFAuxInt(sc-bfc.lsb(), bfc.lsb()+bfc.width()-sc)] x)
1781
1782 // bfi
1783 (OR (UBFIZ [bfc] x) (ANDconst [ac] y))
1784 && ac == ^((1<<uint(bfc.width())-1) << uint(bfc.lsb()))
1785 => (BFI [bfc] y x)
1786 (ORshiftLL [s] (ANDconst [xc] x) (ANDconst [yc] y))
1787 && xc == ^(yc << s) // opposite masks
1788 && yc & (yc+1) == 0 // power of 2 minus 1
1789 && yc > 0 // not 0, not all 64 bits (there are better rewrites in that case)
1790 && s+log64(yc+1) <= 64 // shifted mask doesn't overflow
1791 => (BFI [armBFAuxInt(s, log64(yc+1))] x y)
1792 (ORshiftRL [rc] (ANDconst [ac] x) (SLLconst [lc] y))
1793 && lc > rc && ac == ^((1<<uint(64-lc)-1) << uint64(lc-rc))
1794 => (BFI [armBFAuxInt(lc-rc, 64-lc)] x y)
1795 // bfxil
1796 (OR (UBFX [bfc] x) (ANDconst [ac] y)) && ac == ^(1<<uint(bfc.width())-1)
1797 => (BFXIL [bfc] y x)
1798 (ORshiftLL [sc] (UBFX [bfc] x) (SRLconst [sc] y)) && sc == bfc.width()
1799 => (BFXIL [bfc] y x)
1800 (ORshiftRL [rc] (ANDconst [ac] y) (SLLconst [lc] x)) && lc < rc && ac == ^((1<<uint(64-rc)-1))
1801 => (BFXIL [armBFAuxInt(rc-lc, 64-rc)] y x)
1802
1803 // FP simplification
1804 (FNEGS (FMULS x y)) => (FNMULS x y)
1805 (FNEGD (FMULD x y)) => (FNMULD x y)
1806 (FMULS (FNEGS x) y) => (FNMULS x y)
1807 (FMULD (FNEGD x) y) => (FNMULD x y)
1808 (FNEGS (FNMULS x y)) => (FMULS x y)
1809 (FNEGD (FNMULD x y)) => (FMULD x y)
1810 (FNMULS (FNEGS x) y) => (FMULS x y)
1811 (FNMULD (FNEGD x) y) => (FMULD x y)
1812
1813 (FADDS a (FMULS x y)) && a.Block.Func.useFMA(v) => (FMADDS a x y)
1814 (FADDD a (FMULD x y)) && a.Block.Func.useFMA(v) => (FMADDD a x y)
1815 (FSUBS a (FMULS x y)) && a.Block.Func.useFMA(v) => (FMSUBS a x y)
1816 (FSUBD a (FMULD x y)) && a.Block.Func.useFMA(v) => (FMSUBD a x y)
1817 (FSUBS (FMULS x y) a) && a.Block.Func.useFMA(v) => (FNMSUBS a x y)
1818 (FSUBD (FMULD x y) a) && a.Block.Func.useFMA(v) => (FNMSUBD a x y)
1819 (FADDS a (FNMULS x y)) && a.Block.Func.useFMA(v) => (FMSUBS a x y)
1820 (FADDD a (FNMULD x y)) && a.Block.Func.useFMA(v) => (FMSUBD a x y)
1821 (FSUBS a (FNMULS x y)) && a.Block.Func.useFMA(v) => (FMADDS a x y)
1822 (FSUBD a (FNMULD x y)) && a.Block.Func.useFMA(v) => (FMADDD a x y)
1823 (FSUBS (FNMULS x y) a) && a.Block.Func.useFMA(v) => (FNMADDS a x y)
1824 (FSUBD (FNMULD x y) a) && a.Block.Func.useFMA(v) => (FNMADDD a x y)
1825
1826 (MOVBUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read8(sym, int64(off)))])
1827 (MOVHUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read16(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1828 (MOVWUload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read32(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1829 (MOVDload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(read64(sym, int64(off), config.ctxt.Arch.ByteOrder))])
1830 (MOVBload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(int8(read8(sym, int64(off))))])
1831 (MOVHload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(int16(read16(sym, int64(off), config.ctxt.Arch.ByteOrder)))])
1832 (MOVWload [off] {sym} (SB) _) && symIsRO(sym) => (MOVDconst [int64(int32(read32(sym, int64(off), config.ctxt.Arch.ByteOrder)))])
1833
1834 // Prefetch instructions (aux is option: 0 - PLDL1KEEP; 1 - PLDL1STRM)
1835 (PrefetchCache addr mem) => (PRFM [0] addr mem)
1836 (PrefetchCacheStreamed addr mem) => (PRFM [1] addr mem)
1837
1838 // Arch-specific inlining for small or disjoint runtime.memmove
1839 (SelectN [0] call:(CALLstatic {sym} s1:(MOVDstore _ (MOVDconst [sz]) s2:(MOVDstore _ src s3:(MOVDstore {t} _ dst mem)))))
1840 && sz >= 0
1841 && isSameCall(sym, "runtime.memmove")
1842 && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1
1843 && isInlinableMemmove(dst, src, sz, config)
1844 && clobber(s1, s2, s3, call)
1845 => (Move [sz] dst src mem)
1846
1847 // Match post-lowering calls, register version.
1848 (SelectN [0] call:(CALLstatic {sym} dst src (MOVDconst [sz]) mem))
1849 && sz >= 0
1850 && isSameCall(sym, "runtime.memmove")
1851 && call.Uses == 1
1852 && isInlinableMemmove(dst, src, sz, config)
1853 && clobber(call)
1854 => (Move [sz] dst src mem)
1855
1856 ((REV|REVW) ((REV|REVW) p)) => p
1857
1858 // internal/runtime/math.MulUintptr intrinsics
1859
1860 (Select0 (Mul64uover x y)) => (MUL x y)
1861 (Select1 (Mul64uover x y)) => (NotEqual (CMPconst (UMULH <typ.UInt64> x y) [0]))
1862
1863 // 32 mul 32 -> 64
1864 (MUL r:(MOVWUreg x) s:(MOVWUreg y)) && r.Uses == 1 && s.Uses == 1 => (UMULL x y)
1865 (MUL r:(MOVWreg x) s:(MOVWreg y)) && r.Uses == 1 && s.Uses == 1 => (MULL x y)
1866
1867 // ANDconst to zext
1868 (ANDconst [0xffffffff] x) => (MOVWUreg x)
1869 (ANDconst [0xffff ] x) => (MOVHUreg x)
1870 (ANDconst [0xff ] x) => (MOVBUreg x)
1871
1872 // SIMD zero
1873 (ZeroSIMD <t>) && t.Size() == 16 => (VMOVI16B [0] <t>)
1874
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