config.go

     1  // Copyright 2015 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package ssacompile
     6  
     7  import (
     8  	"cmd/compile/internal/abi"
     9  	"cmd/compile/internal/base"
    10  	"cmd/compile/internal/ssa"
    11  	"cmd/compile/internal/ssa/ssaop"
    12  	"cmd/compile/internal/ssarewrite/rewrite386"
    13  	"cmd/compile/internal/ssarewrite/rewrite386splitload"
    14  	"cmd/compile/internal/ssarewrite/rewriteamd64"
    15  	"cmd/compile/internal/ssarewrite/rewriteamd64latelower"
    16  	"cmd/compile/internal/ssarewrite/rewriteamd64splitload"
    17  	"cmd/compile/internal/ssarewrite/rewritearm"
    18  	"cmd/compile/internal/ssarewrite/rewritearm64"
    19  	"cmd/compile/internal/ssarewrite/rewritearm64latelower"
    20  	"cmd/compile/internal/ssarewrite/rewriteloong64"
    21  	"cmd/compile/internal/ssarewrite/rewriteloong64latelower"
    22  	"cmd/compile/internal/ssarewrite/rewritemips"
    23  	"cmd/compile/internal/ssarewrite/rewritemips64"
    24  	"cmd/compile/internal/ssarewrite/rewritemips64latelower"
    25  	"cmd/compile/internal/ssarewrite/rewriteppc64"
    26  	"cmd/compile/internal/ssarewrite/rewriteppc64latelower"
    27  	"cmd/compile/internal/ssarewrite/rewriteriscv64"
    28  	"cmd/compile/internal/ssarewrite/rewriteriscv64latelower"
    29  	"cmd/compile/internal/ssarewrite/rewrites390x"
    30  	"cmd/compile/internal/ssarewrite/rewritewasm"
    31  	"cmd/internal/obj"
    32  )
    33  
    34  func NewConfig(softFloat bool) *ssa.Config {
    35  	types_ := ssa.NewTypes()
    36  	return newConfig(base.Ctxt.Arch.Name, *types_, base.Ctxt, base.Flag.N == 0, softFloat)
    37  }
    38  
    39  // newConfig returns a new configuration object for the given architecture.
    40  func newConfig(arch string, types ssa.Types, ctxt *obj.Link, optimize, softfloat bool) *ssa.Config {
    41  	c := &ssa.Config{Arch: arch, Types: types}
    42  	switch arch {
    43  	case "amd64":
    44  		c.PtrSize = 8
    45  		c.RegSize = 8
    46  		c.LowerBlock = rewriteamd64.RewriteBlock
    47  		c.LowerValue = rewriteamd64.RewriteValue
    48  		c.LateLowerBlock = rewriteamd64latelower.RewriteBlock
    49  		c.LateLowerValue = rewriteamd64latelower.RewriteValue
    50  		c.SplitLoad = rewriteamd64splitload.RewriteValue
    51  		c.Registers = registersAMD64[:]
    52  		c.GpRegMask = gpRegMaskAMD64
    53  		c.FpRegMask = fpRegMaskAMD64
    54  		c.SimdRegMask = simdRegMaskAMD64
    55  		c.SpecialRegMask = specialRegMaskAMD64
    56  		c.IntParamRegs = paramIntRegAMD64
    57  		c.FloatParamRegs = paramFloatRegAMD64
    58  		c.FPReg = framepointerRegAMD64
    59  		c.LinkReg = linkRegAMD64
    60  		c.HasGReg = true
    61  		c.UnalignedOK = true
    62  		c.HaveBswap64 = true
    63  		c.HaveBswap32 = true
    64  		c.HaveBswap16 = true
    65  		c.HaveCondSelect = true
    66  	case "386":
    67  		c.PtrSize = 4
    68  		c.RegSize = 4
    69  		c.LowerBlock = rewrite386.RewriteBlock
    70  		c.LowerValue = rewrite386.RewriteValue
    71  		c.SplitLoad = rewrite386splitload.RewriteValue
    72  		c.Registers = registers386[:]
    73  		c.GpRegMask = gpRegMask386
    74  		c.FpRegMask = fpRegMask386
    75  		c.FPReg = framepointerReg386
    76  		c.LinkReg = linkReg386
    77  		c.HasGReg = false
    78  		c.UnalignedOK = true
    79  		c.HaveBswap32 = true
    80  		c.HaveBswap16 = true
    81  	case "arm":
    82  		c.PtrSize = 4
    83  		c.RegSize = 4
    84  		c.LowerBlock = rewritearm.RewriteBlock
    85  		c.LowerValue = rewritearm.RewriteValue
    86  		c.Registers = registersARM[:]
    87  		c.GpRegMask = gpRegMaskARM
    88  		c.FpRegMask = fpRegMaskARM
    89  		c.FPReg = framepointerRegARM
    90  		c.LinkReg = linkRegARM
    91  		c.HasGReg = true
    92  	case "arm64":
    93  		c.PtrSize = 8
    94  		c.RegSize = 8
    95  		c.LowerBlock = rewritearm64.RewriteBlock
    96  		c.LowerValue = rewritearm64.RewriteValue
    97  		c.LateLowerBlock = rewritearm64latelower.RewriteBlock
    98  		c.LateLowerValue = rewritearm64latelower.RewriteValue
    99  		c.Registers = registersARM64[:]
   100  		c.GpRegMask = gpRegMaskARM64
   101  		c.FpRegMask = fpRegMaskARM64
   102  		c.SimdRegMask = simdRegMaskARM64
   103  		c.SpecialRegMask = specialRegMaskARM64
   104  		c.IntParamRegs = paramIntRegARM64
   105  		c.FloatParamRegs = paramFloatRegARM64
   106  		c.FPReg = framepointerRegARM64
   107  		c.LinkReg = linkRegARM64
   108  		c.HasGReg = true
   109  		c.UnalignedOK = true
   110  		c.HaveBswap64 = true
   111  		c.HaveBswap32 = true
   112  		c.HaveBswap16 = true
   113  		c.HaveCondSelect = true
   114  	case "ppc64":
   115  		c.BigEndian = true
   116  		fallthrough
   117  	case "ppc64le":
   118  		c.PtrSize = 8
   119  		c.RegSize = 8
   120  		c.LowerBlock = rewriteppc64.RewriteBlock
   121  		c.LowerValue = rewriteppc64.RewriteValue
   122  		c.LateLowerBlock = rewriteppc64latelower.RewriteBlock
   123  		c.LateLowerValue = rewriteppc64latelower.RewriteValue
   124  		c.Registers = registersPPC64[:]
   125  		c.GpRegMask = gpRegMaskPPC64
   126  		c.FpRegMask = fpRegMaskPPC64
   127  		c.SpecialRegMask = specialRegMaskPPC64
   128  		c.IntParamRegs = paramIntRegPPC64
   129  		c.FloatParamRegs = paramFloatRegPPC64
   130  		c.FPReg = framepointerRegPPC64
   131  		c.LinkReg = linkRegPPC64
   132  		c.HasGReg = true
   133  		c.UnalignedOK = true
   134  		// Note: ppc64 has register bswap ops only when GOPPC64>=10.
   135  		// But it has bswap+load and bswap+store ops for all ppc64 variants.
   136  		// That is the sense we're using them here - they are only used
   137  		// in contexts where they can be merged with a load or store.
   138  		c.HaveBswap64 = true
   139  		c.HaveBswap32 = true
   140  		c.HaveBswap16 = true
   141  		c.HaveCondSelect = true
   142  	case "mips64":
   143  		c.BigEndian = true
   144  		fallthrough
   145  	case "mips64le":
   146  		c.PtrSize = 8
   147  		c.RegSize = 8
   148  		c.LowerBlock = rewritemips64.RewriteBlock
   149  		c.LowerValue = rewritemips64.RewriteValue
   150  		c.LateLowerBlock = rewritemips64latelower.RewriteBlock
   151  		c.LateLowerValue = rewritemips64latelower.RewriteValue
   152  		c.Registers = registersMIPS64[:]
   153  		c.GpRegMask = gpRegMaskMIPS64
   154  		c.FpRegMask = fpRegMaskMIPS64
   155  		c.SpecialRegMask = specialRegMaskMIPS64
   156  		c.FPReg = framepointerRegMIPS64
   157  		c.LinkReg = linkRegMIPS64
   158  		c.HasGReg = true
   159  	case "loong64":
   160  		c.PtrSize = 8
   161  		c.RegSize = 8
   162  		c.LowerBlock = rewriteloong64.RewriteBlock
   163  		c.LowerValue = rewriteloong64.RewriteValue
   164  		c.LateLowerBlock = rewriteloong64latelower.RewriteBlock
   165  		c.LateLowerValue = rewriteloong64latelower.RewriteValue
   166  		c.Registers = registersLOONG64[:]
   167  		c.GpRegMask = gpRegMaskLOONG64
   168  		c.FpRegMask = fpRegMaskLOONG64
   169  		c.IntParamRegs = paramIntRegLOONG64
   170  		c.FloatParamRegs = paramFloatRegLOONG64
   171  		c.FPReg = framepointerRegLOONG64
   172  		c.LinkReg = linkRegLOONG64
   173  		c.HasGReg = true
   174  		c.UnalignedOK = true
   175  		c.HaveBswap64 = true
   176  		c.HaveBswap32 = true
   177  		c.HaveBswap16 = true
   178  		c.HaveCondSelect = true
   179  	case "s390x":
   180  		c.PtrSize = 8
   181  		c.RegSize = 8
   182  		c.LowerBlock = rewrites390x.RewriteBlock
   183  		c.LowerValue = rewrites390x.RewriteValue
   184  		c.Registers = registersS390X[:]
   185  		c.GpRegMask = gpRegMaskS390X
   186  		c.FpRegMask = fpRegMaskS390X
   187  		c.IntParamRegs = paramIntRegS390X
   188  		c.FloatParamRegs = paramFloatRegS390X
   189  		c.FPReg = framepointerRegS390X
   190  		c.LinkReg = linkRegS390X
   191  		c.HasGReg = true
   192  		c.BigEndian = true
   193  		c.UnalignedOK = true
   194  		c.HaveBswap64 = true
   195  		c.HaveBswap32 = true
   196  		c.HaveBswap16 = true // only for loads&stores, see ppc64 comment
   197  	case "mips":
   198  		c.BigEndian = true
   199  		fallthrough
   200  	case "mipsle":
   201  		c.PtrSize = 4
   202  		c.RegSize = 4
   203  		c.LowerBlock = rewritemips.RewriteBlock
   204  		c.LowerValue = rewritemips.RewriteValue
   205  		c.Registers = registersMIPS[:]
   206  		c.GpRegMask = gpRegMaskMIPS
   207  		c.FpRegMask = fpRegMaskMIPS
   208  		c.SpecialRegMask = specialRegMaskMIPS
   209  		c.FPReg = framepointerRegMIPS
   210  		c.LinkReg = linkRegMIPS
   211  		c.HasGReg = true
   212  	case "riscv64":
   213  		c.PtrSize = 8
   214  		c.RegSize = 8
   215  		c.LowerBlock = rewriteriscv64.RewriteBlock
   216  		c.LowerValue = rewriteriscv64.RewriteValue
   217  		c.LateLowerBlock = rewriteriscv64latelower.RewriteBlock
   218  		c.LateLowerValue = rewriteriscv64latelower.RewriteValue
   219  		c.Registers = registersRISCV64[:]
   220  		c.GpRegMask = gpRegMaskRISCV64
   221  		c.FpRegMask = fpRegMaskRISCV64
   222  		c.IntParamRegs = paramIntRegRISCV64
   223  		c.FloatParamRegs = paramFloatRegRISCV64
   224  		c.FPReg = framepointerRegRISCV64
   225  		c.HasGReg = true
   226  	case "wasm":
   227  		c.PtrSize = 8
   228  		c.RegSize = 8
   229  		c.LowerBlock = rewritewasm.RewriteBlock
   230  		c.LowerValue = rewritewasm.RewriteValue
   231  		c.Registers = registersWasm[:]
   232  		c.GpRegMask = gpRegMaskWasm
   233  		c.FpRegMask = fpRegMaskWasm
   234  		c.Fp32RegMask = fp32RegMaskWasm
   235  		c.Fp64RegMask = fp64RegMaskWasm
   236  		c.SimdRegMask = simdRegMaskWasm
   237  		c.FPReg = framepointerRegWasm
   238  		c.LinkReg = linkRegWasm
   239  		c.HasGReg = true
   240  		c.UnalignedOK = true
   241  		c.HaveCondSelect = true
   242  	default:
   243  		ctxt.Diag("arch %s not implemented", arch)
   244  	}
   245  	c.Ctxt = ctxt
   246  	c.Optimize = optimize
   247  	c.SoftFloat = softfloat
   248  	if softfloat {
   249  		c.FloatParamRegs = nil // no FP registers in softfloat mode
   250  	}
   251  
   252  	c.ABI0 = abi.NewABIConfig(0, 0, ctxt.Arch.FixedFrameSize, 0)
   253  	c.ABI1 = abi.NewABIConfig(len(c.IntParamRegs), len(c.FloatParamRegs), ctxt.Arch.FixedFrameSize, 1)
   254  
   255  	if ctxt.Flag_shared {
   256  		// LoweredWB is secretly a CALL and CALLs on 386 in
   257  		// shared mode get rewritten by obj6.go to go through
   258  		// the GOT, which clobbers BX.
   259  		ssaop.OpcodeTable[ssaop.Op386LoweredWB].Reg.Clobbers = ssaop.OpcodeTable[ssaop.Op386LoweredWB].Reg.Clobbers.AddReg(3) // BX
   260  	}
   261  
   262  	c.BuildRecipes(arch)
   263  
   264  	return c
   265  }
   266
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