// Code generated from _gen/AMD64.rules using 'go generate'; DO NOT EDIT.

package rewriteamd64

import "internal/buildcfg"
import "math"
import "cmd/internal/obj"
import "cmd/compile/internal/base"
import "cmd/compile/internal/types"
import "cmd/compile/internal/ssa/block"
import "cmd/compile/internal/ssa/ssaop"
import "cmd/compile/internal/ssa"

func RewriteValue(v *ssa.Value) bool {
	switch v.Op {
	case ssaop.OpAESDecryptLastRoundUint8x16:
		v.Op = ssaop.OpAMD64VAESDECLAST128
		return true
	case ssaop.OpAESDecryptLastRoundUint8x32:
		v.Op = ssaop.OpAMD64VAESDECLAST256
		return true
	case ssaop.OpAESDecryptLastRoundUint8x64:
		v.Op = ssaop.OpAMD64VAESDECLAST512
		return true
	case ssaop.OpAESDecryptOneRoundUint8x16:
		v.Op = ssaop.OpAMD64VAESDEC128
		return true
	case ssaop.OpAESDecryptOneRoundUint8x32:
		v.Op = ssaop.OpAMD64VAESDEC256
		return true
	case ssaop.OpAESDecryptOneRoundUint8x64:
		v.Op = ssaop.OpAMD64VAESDEC512
		return true
	case ssaop.OpAESEncryptLastRoundUint8x16:
		v.Op = ssaop.OpAMD64VAESENCLAST128
		return true
	case ssaop.OpAESEncryptLastRoundUint8x32:
		v.Op = ssaop.OpAMD64VAESENCLAST256
		return true
	case ssaop.OpAESEncryptLastRoundUint8x64:
		v.Op = ssaop.OpAMD64VAESENCLAST512
		return true
	case ssaop.OpAESEncryptOneRoundUint8x16:
		v.Op = ssaop.OpAMD64VAESENC128
		return true
	case ssaop.OpAESEncryptOneRoundUint8x32:
		v.Op = ssaop.OpAMD64VAESENC256
		return true
	case ssaop.OpAESEncryptOneRoundUint8x64:
		v.Op = ssaop.OpAMD64VAESENC512
		return true
	case ssaop.OpAESInvMixColumnsUint32x4:
		v.Op = ssaop.OpAMD64VAESIMC128
		return true
	case ssaop.OpAESRoundKeyGenAssistUint32x4:
		v.Op = ssaop.OpAMD64VAESKEYGENASSIST128
		return true
	case ssaop.OpAMD64ADCQ:
		return rewriteValue_OpAMD64ADCQ(v)
	case ssaop.OpAMD64ADCQconst:
		return rewriteValue_OpAMD64ADCQconst(v)
	case ssaop.OpAMD64ADDBconstmodify:
		return rewriteValue_OpAMD64ADDBconstmodify(v)
	case ssaop.OpAMD64ADDL:
		return rewriteValue_OpAMD64ADDL(v)
	case ssaop.OpAMD64ADDLconst:
		return rewriteValue_OpAMD64ADDLconst(v)
	case ssaop.OpAMD64ADDLconstmodify:
		return rewriteValue_OpAMD64ADDLconstmodify(v)
	case ssaop.OpAMD64ADDLload:
		return rewriteValue_OpAMD64ADDLload(v)
	case ssaop.OpAMD64ADDLlock:
		return rewriteValue_OpAMD64ADDLlock(v)
	case ssaop.OpAMD64ADDLmodify:
		return rewriteValue_OpAMD64ADDLmodify(v)
	case ssaop.OpAMD64ADDQ:
		return rewriteValue_OpAMD64ADDQ(v)
	case ssaop.OpAMD64ADDQcarry:
		return rewriteValue_OpAMD64ADDQcarry(v)
	case ssaop.OpAMD64ADDQconst:
		return rewriteValue_OpAMD64ADDQconst(v)
	case ssaop.OpAMD64ADDQconstmodify:
		return rewriteValue_OpAMD64ADDQconstmodify(v)
	case ssaop.OpAMD64ADDQload:
		return rewriteValue_OpAMD64ADDQload(v)
	case ssaop.OpAMD64ADDQlock:
		return rewriteValue_OpAMD64ADDQlock(v)
	case ssaop.OpAMD64ADDQmodify:
		return rewriteValue_OpAMD64ADDQmodify(v)
	case ssaop.OpAMD64ADDSD:
		return rewriteValue_OpAMD64ADDSD(v)
	case ssaop.OpAMD64ADDSDload:
		return rewriteValue_OpAMD64ADDSDload(v)
	case ssaop.OpAMD64ADDSS:
		return rewriteValue_OpAMD64ADDSS(v)
	case ssaop.OpAMD64ADDSSload:
		return rewriteValue_OpAMD64ADDSSload(v)
	case ssaop.OpAMD64ADDWconstmodify:
		return rewriteValue_OpAMD64ADDWconstmodify(v)
	case ssaop.OpAMD64ANDBconstmodify:
		return rewriteValue_OpAMD64ANDBconstmodify(v)
	case ssaop.OpAMD64ANDL:
		return rewriteValue_OpAMD64ANDL(v)
	case ssaop.OpAMD64ANDLconst:
		return rewriteValue_OpAMD64ANDLconst(v)
	case ssaop.OpAMD64ANDLconstmodify:
		return rewriteValue_OpAMD64ANDLconstmodify(v)
	case ssaop.OpAMD64ANDLload:
		return rewriteValue_OpAMD64ANDLload(v)
	case ssaop.OpAMD64ANDLmodify:
		return rewriteValue_OpAMD64ANDLmodify(v)
	case ssaop.OpAMD64ANDNL:
		return rewriteValue_OpAMD64ANDNL(v)
	case ssaop.OpAMD64ANDNQ:
		return rewriteValue_OpAMD64ANDNQ(v)
	case ssaop.OpAMD64ANDQ:
		return rewriteValue_OpAMD64ANDQ(v)
	case ssaop.OpAMD64ANDQconst:
		return rewriteValue_OpAMD64ANDQconst(v)
	case ssaop.OpAMD64ANDQconstmodify:
		return rewriteValue_OpAMD64ANDQconstmodify(v)
	case ssaop.OpAMD64ANDQload:
		return rewriteValue_OpAMD64ANDQload(v)
	case ssaop.OpAMD64ANDQmodify:
		return rewriteValue_OpAMD64ANDQmodify(v)
	case ssaop.OpAMD64ANDWconstmodify:
		return rewriteValue_OpAMD64ANDWconstmodify(v)
	case ssaop.OpAMD64AddTupleFirst32:
		return rewriteValue_OpAMD64AddTupleFirst32(v)
	case ssaop.OpAMD64AddTupleFirst64:
		return rewriteValue_OpAMD64AddTupleFirst64(v)
	case ssaop.OpAMD64BSFQ:
		return rewriteValue_OpAMD64BSFQ(v)
	case ssaop.OpAMD64BSWAPL:
		return rewriteValue_OpAMD64BSWAPL(v)
	case ssaop.OpAMD64BSWAPQ:
		return rewriteValue_OpAMD64BSWAPQ(v)
	case ssaop.OpAMD64BTCQconst:
		return rewriteValue_OpAMD64BTCQconst(v)
	case ssaop.OpAMD64BTLconst:
		return rewriteValue_OpAMD64BTLconst(v)
	case ssaop.OpAMD64BTQconst:
		return rewriteValue_OpAMD64BTQconst(v)
	case ssaop.OpAMD64BTRQconst:
		return rewriteValue_OpAMD64BTRQconst(v)
	case ssaop.OpAMD64BTSQconst:
		return rewriteValue_OpAMD64BTSQconst(v)
	case ssaop.OpAMD64CMOVLCC:
		return rewriteValue_OpAMD64CMOVLCC(v)
	case ssaop.OpAMD64CMOVLCS:
		return rewriteValue_OpAMD64CMOVLCS(v)
	case ssaop.OpAMD64CMOVLEQ:
		return rewriteValue_OpAMD64CMOVLEQ(v)
	case ssaop.OpAMD64CMOVLGE:
		return rewriteValue_OpAMD64CMOVLGE(v)
	case ssaop.OpAMD64CMOVLGT:
		return rewriteValue_OpAMD64CMOVLGT(v)
	case ssaop.OpAMD64CMOVLHI:
		return rewriteValue_OpAMD64CMOVLHI(v)
	case ssaop.OpAMD64CMOVLLE:
		return rewriteValue_OpAMD64CMOVLLE(v)
	case ssaop.OpAMD64CMOVLLS:
		return rewriteValue_OpAMD64CMOVLLS(v)
	case ssaop.OpAMD64CMOVLLT:
		return rewriteValue_OpAMD64CMOVLLT(v)
	case ssaop.OpAMD64CMOVLNE:
		return rewriteValue_OpAMD64CMOVLNE(v)
	case ssaop.OpAMD64CMOVQCC:
		return rewriteValue_OpAMD64CMOVQCC(v)
	case ssaop.OpAMD64CMOVQCS:
		return rewriteValue_OpAMD64CMOVQCS(v)
	case ssaop.OpAMD64CMOVQEQ:
		return rewriteValue_OpAMD64CMOVQEQ(v)
	case ssaop.OpAMD64CMOVQGE:
		return rewriteValue_OpAMD64CMOVQGE(v)
	case ssaop.OpAMD64CMOVQGT:
		return rewriteValue_OpAMD64CMOVQGT(v)
	case ssaop.OpAMD64CMOVQHI:
		return rewriteValue_OpAMD64CMOVQHI(v)
	case ssaop.OpAMD64CMOVQLE:
		return rewriteValue_OpAMD64CMOVQLE(v)
	case ssaop.OpAMD64CMOVQLS:
		return rewriteValue_OpAMD64CMOVQLS(v)
	case ssaop.OpAMD64CMOVQLT:
		return rewriteValue_OpAMD64CMOVQLT(v)
	case ssaop.OpAMD64CMOVQNE:
		return rewriteValue_OpAMD64CMOVQNE(v)
	case ssaop.OpAMD64CMOVWCC:
		return rewriteValue_OpAMD64CMOVWCC(v)
	case ssaop.OpAMD64CMOVWCS:
		return rewriteValue_OpAMD64CMOVWCS(v)
	case ssaop.OpAMD64CMOVWEQ:
		return rewriteValue_OpAMD64CMOVWEQ(v)
	case ssaop.OpAMD64CMOVWGE:
		return rewriteValue_OpAMD64CMOVWGE(v)
	case ssaop.OpAMD64CMOVWGT:
		return rewriteValue_OpAMD64CMOVWGT(v)
	case ssaop.OpAMD64CMOVWHI:
		return rewriteValue_OpAMD64CMOVWHI(v)
	case ssaop.OpAMD64CMOVWLE:
		return rewriteValue_OpAMD64CMOVWLE(v)
	case ssaop.OpAMD64CMOVWLS:
		return rewriteValue_OpAMD64CMOVWLS(v)
	case ssaop.OpAMD64CMOVWLT:
		return rewriteValue_OpAMD64CMOVWLT(v)
	case ssaop.OpAMD64CMOVWNE:
		return rewriteValue_OpAMD64CMOVWNE(v)
	case ssaop.OpAMD64CMPB:
		return rewriteValue_OpAMD64CMPB(v)
	case ssaop.OpAMD64CMPBconst:
		return rewriteValue_OpAMD64CMPBconst(v)
	case ssaop.OpAMD64CMPBconstload:
		return rewriteValue_OpAMD64CMPBconstload(v)
	case ssaop.OpAMD64CMPBload:
		return rewriteValue_OpAMD64CMPBload(v)
	case ssaop.OpAMD64CMPL:
		return rewriteValue_OpAMD64CMPL(v)
	case ssaop.OpAMD64CMPLconst:
		return rewriteValue_OpAMD64CMPLconst(v)
	case ssaop.OpAMD64CMPLconstload:
		return rewriteValue_OpAMD64CMPLconstload(v)
	case ssaop.OpAMD64CMPLload:
		return rewriteValue_OpAMD64CMPLload(v)
	case ssaop.OpAMD64CMPQ:
		return rewriteValue_OpAMD64CMPQ(v)
	case ssaop.OpAMD64CMPQconst:
		return rewriteValue_OpAMD64CMPQconst(v)
	case ssaop.OpAMD64CMPQconstload:
		return rewriteValue_OpAMD64CMPQconstload(v)
	case ssaop.OpAMD64CMPQload:
		return rewriteValue_OpAMD64CMPQload(v)
	case ssaop.OpAMD64CMPW:
		return rewriteValue_OpAMD64CMPW(v)
	case ssaop.OpAMD64CMPWconst:
		return rewriteValue_OpAMD64CMPWconst(v)
	case ssaop.OpAMD64CMPWconstload:
		return rewriteValue_OpAMD64CMPWconstload(v)
	case ssaop.OpAMD64CMPWload:
		return rewriteValue_OpAMD64CMPWload(v)
	case ssaop.OpAMD64CMPXCHGLlock:
		return rewriteValue_OpAMD64CMPXCHGLlock(v)
	case ssaop.OpAMD64CMPXCHGQlock:
		return rewriteValue_OpAMD64CMPXCHGQlock(v)
	case ssaop.OpAMD64CVTSD2SS:
		return rewriteValue_OpAMD64CVTSD2SS(v)
	case ssaop.OpAMD64DIVSD:
		return rewriteValue_OpAMD64DIVSD(v)
	case ssaop.OpAMD64DIVSDload:
		return rewriteValue_OpAMD64DIVSDload(v)
	case ssaop.OpAMD64DIVSS:
		return rewriteValue_OpAMD64DIVSS(v)
	case ssaop.OpAMD64DIVSSload:
		return rewriteValue_OpAMD64DIVSSload(v)
	case ssaop.OpAMD64HMULL:
		return rewriteValue_OpAMD64HMULL(v)
	case ssaop.OpAMD64HMULLU:
		return rewriteValue_OpAMD64HMULLU(v)
	case ssaop.OpAMD64HMULQ:
		return rewriteValue_OpAMD64HMULQ(v)
	case ssaop.OpAMD64HMULQU:
		return rewriteValue_OpAMD64HMULQU(v)
	case ssaop.OpAMD64KANDB:
		return rewriteValue_OpAMD64KANDB(v)
	case ssaop.OpAMD64KANDW:
		return rewriteValue_OpAMD64KANDW(v)
	case ssaop.OpAMD64KMOVBk:
		return rewriteValue_OpAMD64KMOVBk(v)
	case ssaop.OpAMD64KMOVDk:
		return rewriteValue_OpAMD64KMOVDk(v)
	case ssaop.OpAMD64KMOVQk:
		return rewriteValue_OpAMD64KMOVQk(v)
	case ssaop.OpAMD64KMOVWk:
		return rewriteValue_OpAMD64KMOVWk(v)
	case ssaop.OpAMD64LEAL:
		return rewriteValue_OpAMD64LEAL(v)
	case ssaop.OpAMD64LEAL1:
		return rewriteValue_OpAMD64LEAL1(v)
	case ssaop.OpAMD64LEAL2:
		return rewriteValue_OpAMD64LEAL2(v)
	case ssaop.OpAMD64LEAL4:
		return rewriteValue_OpAMD64LEAL4(v)
	case ssaop.OpAMD64LEAL8:
		return rewriteValue_OpAMD64LEAL8(v)
	case ssaop.OpAMD64LEAQ:
		return rewriteValue_OpAMD64LEAQ(v)
	case ssaop.OpAMD64LEAQ1:
		return rewriteValue_OpAMD64LEAQ1(v)
	case ssaop.OpAMD64LEAQ2:
		return rewriteValue_OpAMD64LEAQ2(v)
	case ssaop.OpAMD64LEAQ4:
		return rewriteValue_OpAMD64LEAQ4(v)
	case ssaop.OpAMD64LEAQ8:
		return rewriteValue_OpAMD64LEAQ8(v)
	case ssaop.OpAMD64LoweredPanicBoundsCR:
		return rewriteValue_OpAMD64LoweredPanicBoundsCR(v)
	case ssaop.OpAMD64LoweredPanicBoundsRC:
		return rewriteValue_OpAMD64LoweredPanicBoundsRC(v)
	case ssaop.OpAMD64LoweredPanicBoundsRR:
		return rewriteValue_OpAMD64LoweredPanicBoundsRR(v)
	case ssaop.OpAMD64MOVBELstore:
		return rewriteValue_OpAMD64MOVBELstore(v)
	case ssaop.OpAMD64MOVBEQstore:
		return rewriteValue_OpAMD64MOVBEQstore(v)
	case ssaop.OpAMD64MOVBEWstore:
		return rewriteValue_OpAMD64MOVBEWstore(v)
	case ssaop.OpAMD64MOVBQSX:
		return rewriteValue_OpAMD64MOVBQSX(v)
	case ssaop.OpAMD64MOVBQSXload:
		return rewriteValue_OpAMD64MOVBQSXload(v)
	case ssaop.OpAMD64MOVBQZX:
		return rewriteValue_OpAMD64MOVBQZX(v)
	case ssaop.OpAMD64MOVBatomicload:
		return rewriteValue_OpAMD64MOVBatomicload(v)
	case ssaop.OpAMD64MOVBload:
		return rewriteValue_OpAMD64MOVBload(v)
	case ssaop.OpAMD64MOVBstore:
		return rewriteValue_OpAMD64MOVBstore(v)
	case ssaop.OpAMD64MOVBstoreconst:
		return rewriteValue_OpAMD64MOVBstoreconst(v)
	case ssaop.OpAMD64MOVLQSX:
		return rewriteValue_OpAMD64MOVLQSX(v)
	case ssaop.OpAMD64MOVLQSXload:
		return rewriteValue_OpAMD64MOVLQSXload(v)
	case ssaop.OpAMD64MOVLQZX:
		return rewriteValue_OpAMD64MOVLQZX(v)
	case ssaop.OpAMD64MOVLatomicload:
		return rewriteValue_OpAMD64MOVLatomicload(v)
	case ssaop.OpAMD64MOVLf2i:
		return rewriteValue_OpAMD64MOVLf2i(v)
	case ssaop.OpAMD64MOVLi2f:
		return rewriteValue_OpAMD64MOVLi2f(v)
	case ssaop.OpAMD64MOVLload:
		return rewriteValue_OpAMD64MOVLload(v)
	case ssaop.OpAMD64MOVLstore:
		return rewriteValue_OpAMD64MOVLstore(v)
	case ssaop.OpAMD64MOVLstoreconst:
		return rewriteValue_OpAMD64MOVLstoreconst(v)
	case ssaop.OpAMD64MOVOload:
		return rewriteValue_OpAMD64MOVOload(v)
	case ssaop.OpAMD64MOVOstore:
		return rewriteValue_OpAMD64MOVOstore(v)
	case ssaop.OpAMD64MOVOstoreconst:
		return rewriteValue_OpAMD64MOVOstoreconst(v)
	case ssaop.OpAMD64MOVQatomicload:
		return rewriteValue_OpAMD64MOVQatomicload(v)
	case ssaop.OpAMD64MOVQf2i:
		return rewriteValue_OpAMD64MOVQf2i(v)
	case ssaop.OpAMD64MOVQi2f:
		return rewriteValue_OpAMD64MOVQi2f(v)
	case ssaop.OpAMD64MOVQload:
		return rewriteValue_OpAMD64MOVQload(v)
	case ssaop.OpAMD64MOVQstore:
		return rewriteValue_OpAMD64MOVQstore(v)
	case ssaop.OpAMD64MOVQstoreconst:
		return rewriteValue_OpAMD64MOVQstoreconst(v)
	case ssaop.OpAMD64MOVSDload:
		return rewriteValue_OpAMD64MOVSDload(v)
	case ssaop.OpAMD64MOVSDstore:
		return rewriteValue_OpAMD64MOVSDstore(v)
	case ssaop.OpAMD64MOVSSload:
		return rewriteValue_OpAMD64MOVSSload(v)
	case ssaop.OpAMD64MOVSSstore:
		return rewriteValue_OpAMD64MOVSSstore(v)
	case ssaop.OpAMD64MOVWQSX:
		return rewriteValue_OpAMD64MOVWQSX(v)
	case ssaop.OpAMD64MOVWQSXload:
		return rewriteValue_OpAMD64MOVWQSXload(v)
	case ssaop.OpAMD64MOVWQZX:
		return rewriteValue_OpAMD64MOVWQZX(v)
	case ssaop.OpAMD64MOVWload:
		return rewriteValue_OpAMD64MOVWload(v)
	case ssaop.OpAMD64MOVWstore:
		return rewriteValue_OpAMD64MOVWstore(v)
	case ssaop.OpAMD64MOVWstoreconst:
		return rewriteValue_OpAMD64MOVWstoreconst(v)
	case ssaop.OpAMD64MULL:
		return rewriteValue_OpAMD64MULL(v)
	case ssaop.OpAMD64MULLconst:
		return rewriteValue_OpAMD64MULLconst(v)
	case ssaop.OpAMD64MULQ:
		return rewriteValue_OpAMD64MULQ(v)
	case ssaop.OpAMD64MULQconst:
		return rewriteValue_OpAMD64MULQconst(v)
	case ssaop.OpAMD64MULSD:
		return rewriteValue_OpAMD64MULSD(v)
	case ssaop.OpAMD64MULSDload:
		return rewriteValue_OpAMD64MULSDload(v)
	case ssaop.OpAMD64MULSS:
		return rewriteValue_OpAMD64MULSS(v)
	case ssaop.OpAMD64MULSSload:
		return rewriteValue_OpAMD64MULSSload(v)
	case ssaop.OpAMD64NEGL:
		return rewriteValue_OpAMD64NEGL(v)
	case ssaop.OpAMD64NEGQ:
		return rewriteValue_OpAMD64NEGQ(v)
	case ssaop.OpAMD64NOTL:
		return rewriteValue_OpAMD64NOTL(v)
	case ssaop.OpAMD64NOTQ:
		return rewriteValue_OpAMD64NOTQ(v)
	case ssaop.OpAMD64ORBconstmodify:
		return rewriteValue_OpAMD64ORBconstmodify(v)
	case ssaop.OpAMD64ORL:
		return rewriteValue_OpAMD64ORL(v)
	case ssaop.OpAMD64ORLconst:
		return rewriteValue_OpAMD64ORLconst(v)
	case ssaop.OpAMD64ORLconstmodify:
		return rewriteValue_OpAMD64ORLconstmodify(v)
	case ssaop.OpAMD64ORLload:
		return rewriteValue_OpAMD64ORLload(v)
	case ssaop.OpAMD64ORLmodify:
		return rewriteValue_OpAMD64ORLmodify(v)
	case ssaop.OpAMD64ORQ:
		return rewriteValue_OpAMD64ORQ(v)
	case ssaop.OpAMD64ORQconst:
		return rewriteValue_OpAMD64ORQconst(v)
	case ssaop.OpAMD64ORQconstmodify:
		return rewriteValue_OpAMD64ORQconstmodify(v)
	case ssaop.OpAMD64ORQload:
		return rewriteValue_OpAMD64ORQload(v)
	case ssaop.OpAMD64ORQmodify:
		return rewriteValue_OpAMD64ORQmodify(v)
	case ssaop.OpAMD64ORWconstmodify:
		return rewriteValue_OpAMD64ORWconstmodify(v)
	case ssaop.OpAMD64ROLB:
		return rewriteValue_OpAMD64ROLB(v)
	case ssaop.OpAMD64ROLBconst:
		return rewriteValue_OpAMD64ROLBconst(v)
	case ssaop.OpAMD64ROLL:
		return rewriteValue_OpAMD64ROLL(v)
	case ssaop.OpAMD64ROLLconst:
		return rewriteValue_OpAMD64ROLLconst(v)
	case ssaop.OpAMD64ROLQ:
		return rewriteValue_OpAMD64ROLQ(v)
	case ssaop.OpAMD64ROLQconst:
		return rewriteValue_OpAMD64ROLQconst(v)
	case ssaop.OpAMD64ROLW:
		return rewriteValue_OpAMD64ROLW(v)
	case ssaop.OpAMD64ROLWconst:
		return rewriteValue_OpAMD64ROLWconst(v)
	case ssaop.OpAMD64RORB:
		return rewriteValue_OpAMD64RORB(v)
	case ssaop.OpAMD64RORL:
		return rewriteValue_OpAMD64RORL(v)
	case ssaop.OpAMD64RORQ:
		return rewriteValue_OpAMD64RORQ(v)
	case ssaop.OpAMD64RORW:
		return rewriteValue_OpAMD64RORW(v)
	case ssaop.OpAMD64SARB:
		return rewriteValue_OpAMD64SARB(v)
	case ssaop.OpAMD64SARBconst:
		return rewriteValue_OpAMD64SARBconst(v)
	case ssaop.OpAMD64SARL:
		return rewriteValue_OpAMD64SARL(v)
	case ssaop.OpAMD64SARLconst:
		return rewriteValue_OpAMD64SARLconst(v)
	case ssaop.OpAMD64SARQ:
		return rewriteValue_OpAMD64SARQ(v)
	case ssaop.OpAMD64SARQconst:
		return rewriteValue_OpAMD64SARQconst(v)
	case ssaop.OpAMD64SARW:
		return rewriteValue_OpAMD64SARW(v)
	case ssaop.OpAMD64SARWconst:
		return rewriteValue_OpAMD64SARWconst(v)
	case ssaop.OpAMD64SARXLload:
		return rewriteValue_OpAMD64SARXLload(v)
	case ssaop.OpAMD64SARXQload:
		return rewriteValue_OpAMD64SARXQload(v)
	case ssaop.OpAMD64SBBLcarrymask:
		return rewriteValue_OpAMD64SBBLcarrymask(v)
	case ssaop.OpAMD64SBBQ:
		return rewriteValue_OpAMD64SBBQ(v)
	case ssaop.OpAMD64SBBQcarrymask:
		return rewriteValue_OpAMD64SBBQcarrymask(v)
	case ssaop.OpAMD64SBBQconst:
		return rewriteValue_OpAMD64SBBQconst(v)
	case ssaop.OpAMD64SETA:
		return rewriteValue_OpAMD64SETA(v)
	case ssaop.OpAMD64SETAE:
		return rewriteValue_OpAMD64SETAE(v)
	case ssaop.OpAMD64SETAEstore:
		return rewriteValue_OpAMD64SETAEstore(v)
	case ssaop.OpAMD64SETAstore:
		return rewriteValue_OpAMD64SETAstore(v)
	case ssaop.OpAMD64SETB:
		return rewriteValue_OpAMD64SETB(v)
	case ssaop.OpAMD64SETBE:
		return rewriteValue_OpAMD64SETBE(v)
	case ssaop.OpAMD64SETBEstore:
		return rewriteValue_OpAMD64SETBEstore(v)
	case ssaop.OpAMD64SETBstore:
		return rewriteValue_OpAMD64SETBstore(v)
	case ssaop.OpAMD64SETEQ:
		return rewriteValue_OpAMD64SETEQ(v)
	case ssaop.OpAMD64SETEQstore:
		return rewriteValue_OpAMD64SETEQstore(v)
	case ssaop.OpAMD64SETG:
		return rewriteValue_OpAMD64SETG(v)
	case ssaop.OpAMD64SETGE:
		return rewriteValue_OpAMD64SETGE(v)
	case ssaop.OpAMD64SETGEstore:
		return rewriteValue_OpAMD64SETGEstore(v)
	case ssaop.OpAMD64SETGstore:
		return rewriteValue_OpAMD64SETGstore(v)
	case ssaop.OpAMD64SETL:
		return rewriteValue_OpAMD64SETL(v)
	case ssaop.OpAMD64SETLE:
		return rewriteValue_OpAMD64SETLE(v)
	case ssaop.OpAMD64SETLEstore:
		return rewriteValue_OpAMD64SETLEstore(v)
	case ssaop.OpAMD64SETLstore:
		return rewriteValue_OpAMD64SETLstore(v)
	case ssaop.OpAMD64SETNE:
		return rewriteValue_OpAMD64SETNE(v)
	case ssaop.OpAMD64SETNEstore:
		return rewriteValue_OpAMD64SETNEstore(v)
	case ssaop.OpAMD64SHLL:
		return rewriteValue_OpAMD64SHLL(v)
	case ssaop.OpAMD64SHLLconst:
		return rewriteValue_OpAMD64SHLLconst(v)
	case ssaop.OpAMD64SHLQ:
		return rewriteValue_OpAMD64SHLQ(v)
	case ssaop.OpAMD64SHLQconst:
		return rewriteValue_OpAMD64SHLQconst(v)
	case ssaop.OpAMD64SHLXLload:
		return rewriteValue_OpAMD64SHLXLload(v)
	case ssaop.OpAMD64SHLXQload:
		return rewriteValue_OpAMD64SHLXQload(v)
	case ssaop.OpAMD64SHRB:
		return rewriteValue_OpAMD64SHRB(v)
	case ssaop.OpAMD64SHRBconst:
		return rewriteValue_OpAMD64SHRBconst(v)
	case ssaop.OpAMD64SHRL:
		return rewriteValue_OpAMD64SHRL(v)
	case ssaop.OpAMD64SHRLconst:
		return rewriteValue_OpAMD64SHRLconst(v)
	case ssaop.OpAMD64SHRQ:
		return rewriteValue_OpAMD64SHRQ(v)
	case ssaop.OpAMD64SHRQconst:
		return rewriteValue_OpAMD64SHRQconst(v)
	case ssaop.OpAMD64SHRW:
		return rewriteValue_OpAMD64SHRW(v)
	case ssaop.OpAMD64SHRWconst:
		return rewriteValue_OpAMD64SHRWconst(v)
	case ssaop.OpAMD64SHRXLload:
		return rewriteValue_OpAMD64SHRXLload(v)
	case ssaop.OpAMD64SHRXQload:
		return rewriteValue_OpAMD64SHRXQload(v)
	case ssaop.OpAMD64SUBL:
		return rewriteValue_OpAMD64SUBL(v)
	case ssaop.OpAMD64SUBLconst:
		return rewriteValue_OpAMD64SUBLconst(v)
	case ssaop.OpAMD64SUBLload:
		return rewriteValue_OpAMD64SUBLload(v)
	case ssaop.OpAMD64SUBLmodify:
		return rewriteValue_OpAMD64SUBLmodify(v)
	case ssaop.OpAMD64SUBQ:
		return rewriteValue_OpAMD64SUBQ(v)
	case ssaop.OpAMD64SUBQborrow:
		return rewriteValue_OpAMD64SUBQborrow(v)
	case ssaop.OpAMD64SUBQconst:
		return rewriteValue_OpAMD64SUBQconst(v)
	case ssaop.OpAMD64SUBQload:
		return rewriteValue_OpAMD64SUBQload(v)
	case ssaop.OpAMD64SUBQmodify:
		return rewriteValue_OpAMD64SUBQmodify(v)
	case ssaop.OpAMD64SUBSD:
		return rewriteValue_OpAMD64SUBSD(v)
	case ssaop.OpAMD64SUBSDload:
		return rewriteValue_OpAMD64SUBSDload(v)
	case ssaop.OpAMD64SUBSS:
		return rewriteValue_OpAMD64SUBSS(v)
	case ssaop.OpAMD64SUBSSload:
		return rewriteValue_OpAMD64SUBSSload(v)
	case ssaop.OpAMD64TESTB:
		return rewriteValue_OpAMD64TESTB(v)
	case ssaop.OpAMD64TESTBconst:
		return rewriteValue_OpAMD64TESTBconst(v)
	case ssaop.OpAMD64TESTL:
		return rewriteValue_OpAMD64TESTL(v)
	case ssaop.OpAMD64TESTLconst:
		return rewriteValue_OpAMD64TESTLconst(v)
	case ssaop.OpAMD64TESTQ:
		return rewriteValue_OpAMD64TESTQ(v)
	case ssaop.OpAMD64TESTQconst:
		return rewriteValue_OpAMD64TESTQconst(v)
	case ssaop.OpAMD64TESTW:
		return rewriteValue_OpAMD64TESTW(v)
	case ssaop.OpAMD64TESTWconst:
		return rewriteValue_OpAMD64TESTWconst(v)
	case ssaop.OpAMD64VADDPD128:
		return rewriteValue_OpAMD64VADDPD128(v)
	case ssaop.OpAMD64VADDPD256:
		return rewriteValue_OpAMD64VADDPD256(v)
	case ssaop.OpAMD64VADDPD512:
		return rewriteValue_OpAMD64VADDPD512(v)
	case ssaop.OpAMD64VADDPDMasked128:
		return rewriteValue_OpAMD64VADDPDMasked128(v)
	case ssaop.OpAMD64VADDPDMasked256:
		return rewriteValue_OpAMD64VADDPDMasked256(v)
	case ssaop.OpAMD64VADDPDMasked512:
		return rewriteValue_OpAMD64VADDPDMasked512(v)
	case ssaop.OpAMD64VADDPS128:
		return rewriteValue_OpAMD64VADDPS128(v)
	case ssaop.OpAMD64VADDPS256:
		return rewriteValue_OpAMD64VADDPS256(v)
	case ssaop.OpAMD64VADDPS512:
		return rewriteValue_OpAMD64VADDPS512(v)
	case ssaop.OpAMD64VADDPSMasked128:
		return rewriteValue_OpAMD64VADDPSMasked128(v)
	case ssaop.OpAMD64VADDPSMasked256:
		return rewriteValue_OpAMD64VADDPSMasked256(v)
	case ssaop.OpAMD64VADDPSMasked512:
		return rewriteValue_OpAMD64VADDPSMasked512(v)
	case ssaop.OpAMD64VADDSUBPD128:
		return rewriteValue_OpAMD64VADDSUBPD128(v)
	case ssaop.OpAMD64VADDSUBPD256:
		return rewriteValue_OpAMD64VADDSUBPD256(v)
	case ssaop.OpAMD64VADDSUBPS128:
		return rewriteValue_OpAMD64VADDSUBPS128(v)
	case ssaop.OpAMD64VADDSUBPS256:
		return rewriteValue_OpAMD64VADDSUBPS256(v)
	case ssaop.OpAMD64VAESDEC128:
		return rewriteValue_OpAMD64VAESDEC128(v)
	case ssaop.OpAMD64VAESDEC256:
		return rewriteValue_OpAMD64VAESDEC256(v)
	case ssaop.OpAMD64VAESDECLAST128:
		return rewriteValue_OpAMD64VAESDECLAST128(v)
	case ssaop.OpAMD64VAESDECLAST256:
		return rewriteValue_OpAMD64VAESDECLAST256(v)
	case ssaop.OpAMD64VAESENC128:
		return rewriteValue_OpAMD64VAESENC128(v)
	case ssaop.OpAMD64VAESENC256:
		return rewriteValue_OpAMD64VAESENC256(v)
	case ssaop.OpAMD64VAESENCLAST128:
		return rewriteValue_OpAMD64VAESENCLAST128(v)
	case ssaop.OpAMD64VAESENCLAST256:
		return rewriteValue_OpAMD64VAESENCLAST256(v)
	case ssaop.OpAMD64VAESIMC128:
		return rewriteValue_OpAMD64VAESIMC128(v)
	case ssaop.OpAMD64VAESKEYGENASSIST128:
		return rewriteValue_OpAMD64VAESKEYGENASSIST128(v)
	case ssaop.OpAMD64VBROADCASTSD256:
		return rewriteValue_OpAMD64VBROADCASTSD256(v)
	case ssaop.OpAMD64VBROADCASTSD512:
		return rewriteValue_OpAMD64VBROADCASTSD512(v)
	case ssaop.OpAMD64VBROADCASTSDMasked256:
		return rewriteValue_OpAMD64VBROADCASTSDMasked256(v)
	case ssaop.OpAMD64VBROADCASTSDMasked512:
		return rewriteValue_OpAMD64VBROADCASTSDMasked512(v)
	case ssaop.OpAMD64VBROADCASTSS128:
		return rewriteValue_OpAMD64VBROADCASTSS128(v)
	case ssaop.OpAMD64VBROADCASTSS256:
		return rewriteValue_OpAMD64VBROADCASTSS256(v)
	case ssaop.OpAMD64VBROADCASTSS512:
		return rewriteValue_OpAMD64VBROADCASTSS512(v)
	case ssaop.OpAMD64VBROADCASTSSMasked128:
		return rewriteValue_OpAMD64VBROADCASTSSMasked128(v)
	case ssaop.OpAMD64VBROADCASTSSMasked256:
		return rewriteValue_OpAMD64VBROADCASTSSMasked256(v)
	case ssaop.OpAMD64VBROADCASTSSMasked512:
		return rewriteValue_OpAMD64VBROADCASTSSMasked512(v)
	case ssaop.OpAMD64VCMPPD128:
		return rewriteValue_OpAMD64VCMPPD128(v)
	case ssaop.OpAMD64VCMPPD256:
		return rewriteValue_OpAMD64VCMPPD256(v)
	case ssaop.OpAMD64VCMPPD512:
		return rewriteValue_OpAMD64VCMPPD512(v)
	case ssaop.OpAMD64VCMPPDMasked128:
		return rewriteValue_OpAMD64VCMPPDMasked128(v)
	case ssaop.OpAMD64VCMPPDMasked256:
		return rewriteValue_OpAMD64VCMPPDMasked256(v)
	case ssaop.OpAMD64VCMPPDMasked512:
		return rewriteValue_OpAMD64VCMPPDMasked512(v)
	case ssaop.OpAMD64VCMPPS128:
		return rewriteValue_OpAMD64VCMPPS128(v)
	case ssaop.OpAMD64VCMPPS256:
		return rewriteValue_OpAMD64VCMPPS256(v)
	case ssaop.OpAMD64VCMPPS512:
		return rewriteValue_OpAMD64VCMPPS512(v)
	case ssaop.OpAMD64VCMPPSMasked128:
		return rewriteValue_OpAMD64VCMPPSMasked128(v)
	case ssaop.OpAMD64VCMPPSMasked256:
		return rewriteValue_OpAMD64VCMPPSMasked256(v)
	case ssaop.OpAMD64VCMPPSMasked512:
		return rewriteValue_OpAMD64VCMPPSMasked512(v)
	case ssaop.OpAMD64VCVTDQ2PD256:
		return rewriteValue_OpAMD64VCVTDQ2PD256(v)
	case ssaop.OpAMD64VCVTDQ2PD512:
		return rewriteValue_OpAMD64VCVTDQ2PD512(v)
	case ssaop.OpAMD64VCVTDQ2PDMasked256:
		return rewriteValue_OpAMD64VCVTDQ2PDMasked256(v)
	case ssaop.OpAMD64VCVTDQ2PDMasked512:
		return rewriteValue_OpAMD64VCVTDQ2PDMasked512(v)
	case ssaop.OpAMD64VCVTDQ2PS128:
		return rewriteValue_OpAMD64VCVTDQ2PS128(v)
	case ssaop.OpAMD64VCVTDQ2PS256:
		return rewriteValue_OpAMD64VCVTDQ2PS256(v)
	case ssaop.OpAMD64VCVTDQ2PS512:
		return rewriteValue_OpAMD64VCVTDQ2PS512(v)
	case ssaop.OpAMD64VCVTDQ2PSMasked128:
		return rewriteValue_OpAMD64VCVTDQ2PSMasked128(v)
	case ssaop.OpAMD64VCVTDQ2PSMasked256:
		return rewriteValue_OpAMD64VCVTDQ2PSMasked256(v)
	case ssaop.OpAMD64VCVTDQ2PSMasked512:
		return rewriteValue_OpAMD64VCVTDQ2PSMasked512(v)
	case ssaop.OpAMD64VCVTPD2PS256:
		return rewriteValue_OpAMD64VCVTPD2PS256(v)
	case ssaop.OpAMD64VCVTPD2PSMasked256:
		return rewriteValue_OpAMD64VCVTPD2PSMasked256(v)
	case ssaop.OpAMD64VCVTPD2PSX128:
		return rewriteValue_OpAMD64VCVTPD2PSX128(v)
	case ssaop.OpAMD64VCVTPD2PSXMasked128:
		return rewriteValue_OpAMD64VCVTPD2PSXMasked128(v)
	case ssaop.OpAMD64VCVTPD2PSY128:
		return rewriteValue_OpAMD64VCVTPD2PSY128(v)
	case ssaop.OpAMD64VCVTPD2PSYMasked128:
		return rewriteValue_OpAMD64VCVTPD2PSYMasked128(v)
	case ssaop.OpAMD64VCVTPS2PD256:
		return rewriteValue_OpAMD64VCVTPS2PD256(v)
	case ssaop.OpAMD64VCVTPS2PD512:
		return rewriteValue_OpAMD64VCVTPS2PD512(v)
	case ssaop.OpAMD64VCVTPS2PDMasked256:
		return rewriteValue_OpAMD64VCVTPS2PDMasked256(v)
	case ssaop.OpAMD64VCVTPS2PDMasked512:
		return rewriteValue_OpAMD64VCVTPS2PDMasked512(v)
	case ssaop.OpAMD64VCVTQQ2PD128:
		return rewriteValue_OpAMD64VCVTQQ2PD128(v)
	case ssaop.OpAMD64VCVTQQ2PD256:
		return rewriteValue_OpAMD64VCVTQQ2PD256(v)
	case ssaop.OpAMD64VCVTQQ2PD512:
		return rewriteValue_OpAMD64VCVTQQ2PD512(v)
	case ssaop.OpAMD64VCVTQQ2PDMasked128:
		return rewriteValue_OpAMD64VCVTQQ2PDMasked128(v)
	case ssaop.OpAMD64VCVTQQ2PDMasked256:
		return rewriteValue_OpAMD64VCVTQQ2PDMasked256(v)
	case ssaop.OpAMD64VCVTQQ2PDMasked512:
		return rewriteValue_OpAMD64VCVTQQ2PDMasked512(v)
	case ssaop.OpAMD64VCVTQQ2PS256:
		return rewriteValue_OpAMD64VCVTQQ2PS256(v)
	case ssaop.OpAMD64VCVTQQ2PSMasked256:
		return rewriteValue_OpAMD64VCVTQQ2PSMasked256(v)
	case ssaop.OpAMD64VCVTQQ2PSX128:
		return rewriteValue_OpAMD64VCVTQQ2PSX128(v)
	case ssaop.OpAMD64VCVTQQ2PSXMasked128:
		return rewriteValue_OpAMD64VCVTQQ2PSXMasked128(v)
	case ssaop.OpAMD64VCVTQQ2PSY128:
		return rewriteValue_OpAMD64VCVTQQ2PSY128(v)
	case ssaop.OpAMD64VCVTQQ2PSYMasked128:
		return rewriteValue_OpAMD64VCVTQQ2PSYMasked128(v)
	case ssaop.OpAMD64VCVTTPD2DQ256:
		return rewriteValue_OpAMD64VCVTTPD2DQ256(v)
	case ssaop.OpAMD64VCVTTPD2DQMasked256:
		return rewriteValue_OpAMD64VCVTTPD2DQMasked256(v)
	case ssaop.OpAMD64VCVTTPD2DQX128:
		return rewriteValue_OpAMD64VCVTTPD2DQX128(v)
	case ssaop.OpAMD64VCVTTPD2DQXMasked128:
		return rewriteValue_OpAMD64VCVTTPD2DQXMasked128(v)
	case ssaop.OpAMD64VCVTTPD2DQY128:
		return rewriteValue_OpAMD64VCVTTPD2DQY128(v)
	case ssaop.OpAMD64VCVTTPD2DQYMasked128:
		return rewriteValue_OpAMD64VCVTTPD2DQYMasked128(v)
	case ssaop.OpAMD64VCVTTPD2QQ128:
		return rewriteValue_OpAMD64VCVTTPD2QQ128(v)
	case ssaop.OpAMD64VCVTTPD2QQ256:
		return rewriteValue_OpAMD64VCVTTPD2QQ256(v)
	case ssaop.OpAMD64VCVTTPD2QQ512:
		return rewriteValue_OpAMD64VCVTTPD2QQ512(v)
	case ssaop.OpAMD64VCVTTPD2QQMasked128:
		return rewriteValue_OpAMD64VCVTTPD2QQMasked128(v)
	case ssaop.OpAMD64VCVTTPD2QQMasked256:
		return rewriteValue_OpAMD64VCVTTPD2QQMasked256(v)
	case ssaop.OpAMD64VCVTTPD2QQMasked512:
		return rewriteValue_OpAMD64VCVTTPD2QQMasked512(v)
	case ssaop.OpAMD64VCVTTPD2UDQ256:
		return rewriteValue_OpAMD64VCVTTPD2UDQ256(v)
	case ssaop.OpAMD64VCVTTPD2UDQMasked256:
		return rewriteValue_OpAMD64VCVTTPD2UDQMasked256(v)
	case ssaop.OpAMD64VCVTTPD2UDQX128:
		return rewriteValue_OpAMD64VCVTTPD2UDQX128(v)
	case ssaop.OpAMD64VCVTTPD2UDQXMasked128:
		return rewriteValue_OpAMD64VCVTTPD2UDQXMasked128(v)
	case ssaop.OpAMD64VCVTTPD2UDQY128:
		return rewriteValue_OpAMD64VCVTTPD2UDQY128(v)
	case ssaop.OpAMD64VCVTTPD2UDQYMasked128:
		return rewriteValue_OpAMD64VCVTTPD2UDQYMasked128(v)
	case ssaop.OpAMD64VCVTTPD2UQQ128:
		return rewriteValue_OpAMD64VCVTTPD2UQQ128(v)
	case ssaop.OpAMD64VCVTTPD2UQQ256:
		return rewriteValue_OpAMD64VCVTTPD2UQQ256(v)
	case ssaop.OpAMD64VCVTTPD2UQQ512:
		return rewriteValue_OpAMD64VCVTTPD2UQQ512(v)
	case ssaop.OpAMD64VCVTTPD2UQQMasked128:
		return rewriteValue_OpAMD64VCVTTPD2UQQMasked128(v)
	case ssaop.OpAMD64VCVTTPD2UQQMasked256:
		return rewriteValue_OpAMD64VCVTTPD2UQQMasked256(v)
	case ssaop.OpAMD64VCVTTPD2UQQMasked512:
		return rewriteValue_OpAMD64VCVTTPD2UQQMasked512(v)
	case ssaop.OpAMD64VCVTTPS2DQ128:
		return rewriteValue_OpAMD64VCVTTPS2DQ128(v)
	case ssaop.OpAMD64VCVTTPS2DQ256:
		return rewriteValue_OpAMD64VCVTTPS2DQ256(v)
	case ssaop.OpAMD64VCVTTPS2DQ512:
		return rewriteValue_OpAMD64VCVTTPS2DQ512(v)
	case ssaop.OpAMD64VCVTTPS2DQMasked128:
		return rewriteValue_OpAMD64VCVTTPS2DQMasked128(v)
	case ssaop.OpAMD64VCVTTPS2DQMasked256:
		return rewriteValue_OpAMD64VCVTTPS2DQMasked256(v)
	case ssaop.OpAMD64VCVTTPS2DQMasked512:
		return rewriteValue_OpAMD64VCVTTPS2DQMasked512(v)
	case ssaop.OpAMD64VCVTTPS2QQ256:
		return rewriteValue_OpAMD64VCVTTPS2QQ256(v)
	case ssaop.OpAMD64VCVTTPS2QQ512:
		return rewriteValue_OpAMD64VCVTTPS2QQ512(v)
	case ssaop.OpAMD64VCVTTPS2QQMasked256:
		return rewriteValue_OpAMD64VCVTTPS2QQMasked256(v)
	case ssaop.OpAMD64VCVTTPS2QQMasked512:
		return rewriteValue_OpAMD64VCVTTPS2QQMasked512(v)
	case ssaop.OpAMD64VCVTTPS2UDQ128:
		return rewriteValue_OpAMD64VCVTTPS2UDQ128(v)
	case ssaop.OpAMD64VCVTTPS2UDQ256:
		return rewriteValue_OpAMD64VCVTTPS2UDQ256(v)
	case ssaop.OpAMD64VCVTTPS2UDQ512:
		return rewriteValue_OpAMD64VCVTTPS2UDQ512(v)
	case ssaop.OpAMD64VCVTTPS2UDQMasked128:
		return rewriteValue_OpAMD64VCVTTPS2UDQMasked128(v)
	case ssaop.OpAMD64VCVTTPS2UDQMasked256:
		return rewriteValue_OpAMD64VCVTTPS2UDQMasked256(v)
	case ssaop.OpAMD64VCVTTPS2UDQMasked512:
		return rewriteValue_OpAMD64VCVTTPS2UDQMasked512(v)
	case ssaop.OpAMD64VCVTTPS2UQQ256:
		return rewriteValue_OpAMD64VCVTTPS2UQQ256(v)
	case ssaop.OpAMD64VCVTTPS2UQQ512:
		return rewriteValue_OpAMD64VCVTTPS2UQQ512(v)
	case ssaop.OpAMD64VCVTTPS2UQQMasked256:
		return rewriteValue_OpAMD64VCVTTPS2UQQMasked256(v)
	case ssaop.OpAMD64VCVTTPS2UQQMasked512:
		return rewriteValue_OpAMD64VCVTTPS2UQQMasked512(v)
	case ssaop.OpAMD64VCVTUDQ2PD256:
		return rewriteValue_OpAMD64VCVTUDQ2PD256(v)
	case ssaop.OpAMD64VCVTUDQ2PD512:
		return rewriteValue_OpAMD64VCVTUDQ2PD512(v)
	case ssaop.OpAMD64VCVTUDQ2PDMasked256:
		return rewriteValue_OpAMD64VCVTUDQ2PDMasked256(v)
	case ssaop.OpAMD64VCVTUDQ2PDMasked512:
		return rewriteValue_OpAMD64VCVTUDQ2PDMasked512(v)
	case ssaop.OpAMD64VCVTUDQ2PS128:
		return rewriteValue_OpAMD64VCVTUDQ2PS128(v)
	case ssaop.OpAMD64VCVTUDQ2PS256:
		return rewriteValue_OpAMD64VCVTUDQ2PS256(v)
	case ssaop.OpAMD64VCVTUDQ2PS512:
		return rewriteValue_OpAMD64VCVTUDQ2PS512(v)
	case ssaop.OpAMD64VCVTUDQ2PSMasked128:
		return rewriteValue_OpAMD64VCVTUDQ2PSMasked128(v)
	case ssaop.OpAMD64VCVTUDQ2PSMasked256:
		return rewriteValue_OpAMD64VCVTUDQ2PSMasked256(v)
	case ssaop.OpAMD64VCVTUDQ2PSMasked512:
		return rewriteValue_OpAMD64VCVTUDQ2PSMasked512(v)
	case ssaop.OpAMD64VCVTUQQ2PD128:
		return rewriteValue_OpAMD64VCVTUQQ2PD128(v)
	case ssaop.OpAMD64VCVTUQQ2PD256:
		return rewriteValue_OpAMD64VCVTUQQ2PD256(v)
	case ssaop.OpAMD64VCVTUQQ2PD512:
		return rewriteValue_OpAMD64VCVTUQQ2PD512(v)
	case ssaop.OpAMD64VCVTUQQ2PDMasked128:
		return rewriteValue_OpAMD64VCVTUQQ2PDMasked128(v)
	case ssaop.OpAMD64VCVTUQQ2PDMasked256:
		return rewriteValue_OpAMD64VCVTUQQ2PDMasked256(v)
	case ssaop.OpAMD64VCVTUQQ2PDMasked512:
		return rewriteValue_OpAMD64VCVTUQQ2PDMasked512(v)
	case ssaop.OpAMD64VCVTUQQ2PS256:
		return rewriteValue_OpAMD64VCVTUQQ2PS256(v)
	case ssaop.OpAMD64VCVTUQQ2PSMasked256:
		return rewriteValue_OpAMD64VCVTUQQ2PSMasked256(v)
	case ssaop.OpAMD64VCVTUQQ2PSX128:
		return rewriteValue_OpAMD64VCVTUQQ2PSX128(v)
	case ssaop.OpAMD64VCVTUQQ2PSXMasked128:
		return rewriteValue_OpAMD64VCVTUQQ2PSXMasked128(v)
	case ssaop.OpAMD64VCVTUQQ2PSY128:
		return rewriteValue_OpAMD64VCVTUQQ2PSY128(v)
	case ssaop.OpAMD64VCVTUQQ2PSYMasked128:
		return rewriteValue_OpAMD64VCVTUQQ2PSYMasked128(v)
	case ssaop.OpAMD64VDIVPD128:
		return rewriteValue_OpAMD64VDIVPD128(v)
	case ssaop.OpAMD64VDIVPD256:
		return rewriteValue_OpAMD64VDIVPD256(v)
	case ssaop.OpAMD64VDIVPD512:
		return rewriteValue_OpAMD64VDIVPD512(v)
	case ssaop.OpAMD64VDIVPDMasked128:
		return rewriteValue_OpAMD64VDIVPDMasked128(v)
	case ssaop.OpAMD64VDIVPDMasked256:
		return rewriteValue_OpAMD64VDIVPDMasked256(v)
	case ssaop.OpAMD64VDIVPDMasked512:
		return rewriteValue_OpAMD64VDIVPDMasked512(v)
	case ssaop.OpAMD64VDIVPS128:
		return rewriteValue_OpAMD64VDIVPS128(v)
	case ssaop.OpAMD64VDIVPS256:
		return rewriteValue_OpAMD64VDIVPS256(v)
	case ssaop.OpAMD64VDIVPS512:
		return rewriteValue_OpAMD64VDIVPS512(v)
	case ssaop.OpAMD64VDIVPSMasked128:
		return rewriteValue_OpAMD64VDIVPSMasked128(v)
	case ssaop.OpAMD64VDIVPSMasked256:
		return rewriteValue_OpAMD64VDIVPSMasked256(v)
	case ssaop.OpAMD64VDIVPSMasked512:
		return rewriteValue_OpAMD64VDIVPSMasked512(v)
	case ssaop.OpAMD64VEXPANDPDMasked128:
		return rewriteValue_OpAMD64VEXPANDPDMasked128(v)
	case ssaop.OpAMD64VEXPANDPDMasked256:
		return rewriteValue_OpAMD64VEXPANDPDMasked256(v)
	case ssaop.OpAMD64VEXPANDPSMasked128:
		return rewriteValue_OpAMD64VEXPANDPSMasked128(v)
	case ssaop.OpAMD64VEXPANDPSMasked256:
		return rewriteValue_OpAMD64VEXPANDPSMasked256(v)
	case ssaop.OpAMD64VFMADD213PD128:
		return rewriteValue_OpAMD64VFMADD213PD128(v)
	case ssaop.OpAMD64VFMADD213PD256:
		return rewriteValue_OpAMD64VFMADD213PD256(v)
	case ssaop.OpAMD64VFMADD213PD512:
		return rewriteValue_OpAMD64VFMADD213PD512(v)
	case ssaop.OpAMD64VFMADD213PDMasked128:
		return rewriteValue_OpAMD64VFMADD213PDMasked128(v)
	case ssaop.OpAMD64VFMADD213PDMasked256:
		return rewriteValue_OpAMD64VFMADD213PDMasked256(v)
	case ssaop.OpAMD64VFMADD213PDMasked512:
		return rewriteValue_OpAMD64VFMADD213PDMasked512(v)
	case ssaop.OpAMD64VFMADD213PS128:
		return rewriteValue_OpAMD64VFMADD213PS128(v)
	case ssaop.OpAMD64VFMADD213PS256:
		return rewriteValue_OpAMD64VFMADD213PS256(v)
	case ssaop.OpAMD64VFMADD213PS512:
		return rewriteValue_OpAMD64VFMADD213PS512(v)
	case ssaop.OpAMD64VFMADD213PSMasked128:
		return rewriteValue_OpAMD64VFMADD213PSMasked128(v)
	case ssaop.OpAMD64VFMADD213PSMasked256:
		return rewriteValue_OpAMD64VFMADD213PSMasked256(v)
	case ssaop.OpAMD64VFMADD213PSMasked512:
		return rewriteValue_OpAMD64VFMADD213PSMasked512(v)
	case ssaop.OpAMD64VFMADDSUB213PD128:
		return rewriteValue_OpAMD64VFMADDSUB213PD128(v)
	case ssaop.OpAMD64VFMADDSUB213PD256:
		return rewriteValue_OpAMD64VFMADDSUB213PD256(v)
	case ssaop.OpAMD64VFMADDSUB213PD512:
		return rewriteValue_OpAMD64VFMADDSUB213PD512(v)
	case ssaop.OpAMD64VFMADDSUB213PDMasked128:
		return rewriteValue_OpAMD64VFMADDSUB213PDMasked128(v)
	case ssaop.OpAMD64VFMADDSUB213PDMasked256:
		return rewriteValue_OpAMD64VFMADDSUB213PDMasked256(v)
	case ssaop.OpAMD64VFMADDSUB213PDMasked512:
		return rewriteValue_OpAMD64VFMADDSUB213PDMasked512(v)
	case ssaop.OpAMD64VFMADDSUB213PS128:
		return rewriteValue_OpAMD64VFMADDSUB213PS128(v)
	case ssaop.OpAMD64VFMADDSUB213PS256:
		return rewriteValue_OpAMD64VFMADDSUB213PS256(v)
	case ssaop.OpAMD64VFMADDSUB213PS512:
		return rewriteValue_OpAMD64VFMADDSUB213PS512(v)
	case ssaop.OpAMD64VFMADDSUB213PSMasked128:
		return rewriteValue_OpAMD64VFMADDSUB213PSMasked128(v)
	case ssaop.OpAMD64VFMADDSUB213PSMasked256:
		return rewriteValue_OpAMD64VFMADDSUB213PSMasked256(v)
	case ssaop.OpAMD64VFMADDSUB213PSMasked512:
		return rewriteValue_OpAMD64VFMADDSUB213PSMasked512(v)
	case ssaop.OpAMD64VFMSUBADD213PD128:
		return rewriteValue_OpAMD64VFMSUBADD213PD128(v)
	case ssaop.OpAMD64VFMSUBADD213PD256:
		return rewriteValue_OpAMD64VFMSUBADD213PD256(v)
	case ssaop.OpAMD64VFMSUBADD213PD512:
		return rewriteValue_OpAMD64VFMSUBADD213PD512(v)
	case ssaop.OpAMD64VFMSUBADD213PDMasked128:
		return rewriteValue_OpAMD64VFMSUBADD213PDMasked128(v)
	case ssaop.OpAMD64VFMSUBADD213PDMasked256:
		return rewriteValue_OpAMD64VFMSUBADD213PDMasked256(v)
	case ssaop.OpAMD64VFMSUBADD213PDMasked512:
		return rewriteValue_OpAMD64VFMSUBADD213PDMasked512(v)
	case ssaop.OpAMD64VFMSUBADD213PS128:
		return rewriteValue_OpAMD64VFMSUBADD213PS128(v)
	case ssaop.OpAMD64VFMSUBADD213PS256:
		return rewriteValue_OpAMD64VFMSUBADD213PS256(v)
	case ssaop.OpAMD64VFMSUBADD213PS512:
		return rewriteValue_OpAMD64VFMSUBADD213PS512(v)
	case ssaop.OpAMD64VFMSUBADD213PSMasked128:
		return rewriteValue_OpAMD64VFMSUBADD213PSMasked128(v)
	case ssaop.OpAMD64VFMSUBADD213PSMasked256:
		return rewriteValue_OpAMD64VFMSUBADD213PSMasked256(v)
	case ssaop.OpAMD64VFMSUBADD213PSMasked512:
		return rewriteValue_OpAMD64VFMSUBADD213PSMasked512(v)
	case ssaop.OpAMD64VGF2P8AFFINEINVQB128:
		return rewriteValue_OpAMD64VGF2P8AFFINEINVQB128(v)
	case ssaop.OpAMD64VGF2P8AFFINEINVQB256:
		return rewriteValue_OpAMD64VGF2P8AFFINEINVQB256(v)
	case ssaop.OpAMD64VGF2P8AFFINEINVQB512:
		return rewriteValue_OpAMD64VGF2P8AFFINEINVQB512(v)
	case ssaop.OpAMD64VGF2P8AFFINEINVQBMasked128:
		return rewriteValue_OpAMD64VGF2P8AFFINEINVQBMasked128(v)
	case ssaop.OpAMD64VGF2P8AFFINEINVQBMasked256:
		return rewriteValue_OpAMD64VGF2P8AFFINEINVQBMasked256(v)
	case ssaop.OpAMD64VGF2P8AFFINEINVQBMasked512:
		return rewriteValue_OpAMD64VGF2P8AFFINEINVQBMasked512(v)
	case ssaop.OpAMD64VGF2P8AFFINEQB128:
		return rewriteValue_OpAMD64VGF2P8AFFINEQB128(v)
	case ssaop.OpAMD64VGF2P8AFFINEQB256:
		return rewriteValue_OpAMD64VGF2P8AFFINEQB256(v)
	case ssaop.OpAMD64VGF2P8AFFINEQB512:
		return rewriteValue_OpAMD64VGF2P8AFFINEQB512(v)
	case ssaop.OpAMD64VGF2P8AFFINEQBMasked128:
		return rewriteValue_OpAMD64VGF2P8AFFINEQBMasked128(v)
	case ssaop.OpAMD64VGF2P8AFFINEQBMasked256:
		return rewriteValue_OpAMD64VGF2P8AFFINEQBMasked256(v)
	case ssaop.OpAMD64VGF2P8AFFINEQBMasked512:
		return rewriteValue_OpAMD64VGF2P8AFFINEQBMasked512(v)
	case ssaop.OpAMD64VGF2P8MULB128:
		return rewriteValue_OpAMD64VGF2P8MULB128(v)
	case ssaop.OpAMD64VGF2P8MULB256:
		return rewriteValue_OpAMD64VGF2P8MULB256(v)
	case ssaop.OpAMD64VGF2P8MULBMasked128:
		return rewriteValue_OpAMD64VGF2P8MULBMasked128(v)
	case ssaop.OpAMD64VGF2P8MULBMasked256:
		return rewriteValue_OpAMD64VGF2P8MULBMasked256(v)
	case ssaop.OpAMD64VHADDPD128:
		return rewriteValue_OpAMD64VHADDPD128(v)
	case ssaop.OpAMD64VHADDPD256:
		return rewriteValue_OpAMD64VHADDPD256(v)
	case ssaop.OpAMD64VHADDPS128:
		return rewriteValue_OpAMD64VHADDPS128(v)
	case ssaop.OpAMD64VHADDPS256:
		return rewriteValue_OpAMD64VHADDPS256(v)
	case ssaop.OpAMD64VHSUBPD128:
		return rewriteValue_OpAMD64VHSUBPD128(v)
	case ssaop.OpAMD64VHSUBPD256:
		return rewriteValue_OpAMD64VHSUBPD256(v)
	case ssaop.OpAMD64VHSUBPS128:
		return rewriteValue_OpAMD64VHSUBPS128(v)
	case ssaop.OpAMD64VHSUBPS256:
		return rewriteValue_OpAMD64VHSUBPS256(v)
	case ssaop.OpAMD64VINSERTF128256:
		return rewriteValue_OpAMD64VINSERTF128256(v)
	case ssaop.OpAMD64VINSERTF64X4512:
		return rewriteValue_OpAMD64VINSERTF64X4512(v)
	case ssaop.OpAMD64VINSERTI128256:
		return rewriteValue_OpAMD64VINSERTI128256(v)
	case ssaop.OpAMD64VINSERTI64X4512:
		return rewriteValue_OpAMD64VINSERTI64X4512(v)
	case ssaop.OpAMD64VMAXPD128:
		return rewriteValue_OpAMD64VMAXPD128(v)
	case ssaop.OpAMD64VMAXPD256:
		return rewriteValue_OpAMD64VMAXPD256(v)
	case ssaop.OpAMD64VMAXPD512:
		return rewriteValue_OpAMD64VMAXPD512(v)
	case ssaop.OpAMD64VMAXPDMasked128:
		return rewriteValue_OpAMD64VMAXPDMasked128(v)
	case ssaop.OpAMD64VMAXPDMasked256:
		return rewriteValue_OpAMD64VMAXPDMasked256(v)
	case ssaop.OpAMD64VMAXPDMasked512:
		return rewriteValue_OpAMD64VMAXPDMasked512(v)
	case ssaop.OpAMD64VMAXPS128:
		return rewriteValue_OpAMD64VMAXPS128(v)
	case ssaop.OpAMD64VMAXPS256:
		return rewriteValue_OpAMD64VMAXPS256(v)
	case ssaop.OpAMD64VMAXPS512:
		return rewriteValue_OpAMD64VMAXPS512(v)
	case ssaop.OpAMD64VMAXPSMasked128:
		return rewriteValue_OpAMD64VMAXPSMasked128(v)
	case ssaop.OpAMD64VMAXPSMasked256:
		return rewriteValue_OpAMD64VMAXPSMasked256(v)
	case ssaop.OpAMD64VMAXPSMasked512:
		return rewriteValue_OpAMD64VMAXPSMasked512(v)
	case ssaop.OpAMD64VMINPD128:
		return rewriteValue_OpAMD64VMINPD128(v)
	case ssaop.OpAMD64VMINPD256:
		return rewriteValue_OpAMD64VMINPD256(v)
	case ssaop.OpAMD64VMINPD512:
		return rewriteValue_OpAMD64VMINPD512(v)
	case ssaop.OpAMD64VMINPDMasked128:
		return rewriteValue_OpAMD64VMINPDMasked128(v)
	case ssaop.OpAMD64VMINPDMasked256:
		return rewriteValue_OpAMD64VMINPDMasked256(v)
	case ssaop.OpAMD64VMINPDMasked512:
		return rewriteValue_OpAMD64VMINPDMasked512(v)
	case ssaop.OpAMD64VMINPS128:
		return rewriteValue_OpAMD64VMINPS128(v)
	case ssaop.OpAMD64VMINPS256:
		return rewriteValue_OpAMD64VMINPS256(v)
	case ssaop.OpAMD64VMINPS512:
		return rewriteValue_OpAMD64VMINPS512(v)
	case ssaop.OpAMD64VMINPSMasked128:
		return rewriteValue_OpAMD64VMINPSMasked128(v)
	case ssaop.OpAMD64VMINPSMasked256:
		return rewriteValue_OpAMD64VMINPSMasked256(v)
	case ssaop.OpAMD64VMINPSMasked512:
		return rewriteValue_OpAMD64VMINPSMasked512(v)
	case ssaop.OpAMD64VMOVD:
		return rewriteValue_OpAMD64VMOVD(v)
	case ssaop.OpAMD64VMOVDQU16Masked128:
		return rewriteValue_OpAMD64VMOVDQU16Masked128(v)
	case ssaop.OpAMD64VMOVDQU16Masked256:
		return rewriteValue_OpAMD64VMOVDQU16Masked256(v)
	case ssaop.OpAMD64VMOVDQU16Masked512:
		return rewriteValue_OpAMD64VMOVDQU16Masked512(v)
	case ssaop.OpAMD64VMOVDQU32Masked128:
		return rewriteValue_OpAMD64VMOVDQU32Masked128(v)
	case ssaop.OpAMD64VMOVDQU32Masked256:
		return rewriteValue_OpAMD64VMOVDQU32Masked256(v)
	case ssaop.OpAMD64VMOVDQU32Masked512:
		return rewriteValue_OpAMD64VMOVDQU32Masked512(v)
	case ssaop.OpAMD64VMOVDQU64Masked128:
		return rewriteValue_OpAMD64VMOVDQU64Masked128(v)
	case ssaop.OpAMD64VMOVDQU64Masked256:
		return rewriteValue_OpAMD64VMOVDQU64Masked256(v)
	case ssaop.OpAMD64VMOVDQU64Masked512:
		return rewriteValue_OpAMD64VMOVDQU64Masked512(v)
	case ssaop.OpAMD64VMOVDQU8Masked128:
		return rewriteValue_OpAMD64VMOVDQU8Masked128(v)
	case ssaop.OpAMD64VMOVDQU8Masked256:
		return rewriteValue_OpAMD64VMOVDQU8Masked256(v)
	case ssaop.OpAMD64VMOVDQU8Masked512:
		return rewriteValue_OpAMD64VMOVDQU8Masked512(v)
	case ssaop.OpAMD64VMOVDQUload128:
		return rewriteValue_OpAMD64VMOVDQUload128(v)
	case ssaop.OpAMD64VMOVDQUload256:
		return rewriteValue_OpAMD64VMOVDQUload256(v)
	case ssaop.OpAMD64VMOVDQUload512:
		return rewriteValue_OpAMD64VMOVDQUload512(v)
	case ssaop.OpAMD64VMOVDQUstore128:
		return rewriteValue_OpAMD64VMOVDQUstore128(v)
	case ssaop.OpAMD64VMOVDQUstore256:
		return rewriteValue_OpAMD64VMOVDQUstore256(v)
	case ssaop.OpAMD64VMOVDQUstore512:
		return rewriteValue_OpAMD64VMOVDQUstore512(v)
	case ssaop.OpAMD64VMOVQ:
		return rewriteValue_OpAMD64VMOVQ(v)
	case ssaop.OpAMD64VMOVSDf2v:
		return rewriteValue_OpAMD64VMOVSDf2v(v)
	case ssaop.OpAMD64VMOVSSf2v:
		return rewriteValue_OpAMD64VMOVSSf2v(v)
	case ssaop.OpAMD64VMULPD128:
		return rewriteValue_OpAMD64VMULPD128(v)
	case ssaop.OpAMD64VMULPD256:
		return rewriteValue_OpAMD64VMULPD256(v)
	case ssaop.OpAMD64VMULPD512:
		return rewriteValue_OpAMD64VMULPD512(v)
	case ssaop.OpAMD64VMULPDMasked128:
		return rewriteValue_OpAMD64VMULPDMasked128(v)
	case ssaop.OpAMD64VMULPDMasked256:
		return rewriteValue_OpAMD64VMULPDMasked256(v)
	case ssaop.OpAMD64VMULPDMasked512:
		return rewriteValue_OpAMD64VMULPDMasked512(v)
	case ssaop.OpAMD64VMULPS128:
		return rewriteValue_OpAMD64VMULPS128(v)
	case ssaop.OpAMD64VMULPS256:
		return rewriteValue_OpAMD64VMULPS256(v)
	case ssaop.OpAMD64VMULPS512:
		return rewriteValue_OpAMD64VMULPS512(v)
	case ssaop.OpAMD64VMULPSMasked128:
		return rewriteValue_OpAMD64VMULPSMasked128(v)
	case ssaop.OpAMD64VMULPSMasked256:
		return rewriteValue_OpAMD64VMULPSMasked256(v)
	case ssaop.OpAMD64VMULPSMasked512:
		return rewriteValue_OpAMD64VMULPSMasked512(v)
	case ssaop.OpAMD64VPABSB128:
		return rewriteValue_OpAMD64VPABSB128(v)
	case ssaop.OpAMD64VPABSB256:
		return rewriteValue_OpAMD64VPABSB256(v)
	case ssaop.OpAMD64VPABSBMasked128:
		return rewriteValue_OpAMD64VPABSBMasked128(v)
	case ssaop.OpAMD64VPABSBMasked256:
		return rewriteValue_OpAMD64VPABSBMasked256(v)
	case ssaop.OpAMD64VPABSD128:
		return rewriteValue_OpAMD64VPABSD128(v)
	case ssaop.OpAMD64VPABSD256:
		return rewriteValue_OpAMD64VPABSD256(v)
	case ssaop.OpAMD64VPABSD512:
		return rewriteValue_OpAMD64VPABSD512(v)
	case ssaop.OpAMD64VPABSDMasked128:
		return rewriteValue_OpAMD64VPABSDMasked128(v)
	case ssaop.OpAMD64VPABSDMasked256:
		return rewriteValue_OpAMD64VPABSDMasked256(v)
	case ssaop.OpAMD64VPABSDMasked512:
		return rewriteValue_OpAMD64VPABSDMasked512(v)
	case ssaop.OpAMD64VPABSQ128:
		return rewriteValue_OpAMD64VPABSQ128(v)
	case ssaop.OpAMD64VPABSQ256:
		return rewriteValue_OpAMD64VPABSQ256(v)
	case ssaop.OpAMD64VPABSQ512:
		return rewriteValue_OpAMD64VPABSQ512(v)
	case ssaop.OpAMD64VPABSQMasked128:
		return rewriteValue_OpAMD64VPABSQMasked128(v)
	case ssaop.OpAMD64VPABSQMasked256:
		return rewriteValue_OpAMD64VPABSQMasked256(v)
	case ssaop.OpAMD64VPABSQMasked512:
		return rewriteValue_OpAMD64VPABSQMasked512(v)
	case ssaop.OpAMD64VPABSW128:
		return rewriteValue_OpAMD64VPABSW128(v)
	case ssaop.OpAMD64VPABSW256:
		return rewriteValue_OpAMD64VPABSW256(v)
	case ssaop.OpAMD64VPABSWMasked128:
		return rewriteValue_OpAMD64VPABSWMasked128(v)
	case ssaop.OpAMD64VPABSWMasked256:
		return rewriteValue_OpAMD64VPABSWMasked256(v)
	case ssaop.OpAMD64VPACKSSDW128:
		return rewriteValue_OpAMD64VPACKSSDW128(v)
	case ssaop.OpAMD64VPACKSSDW256:
		return rewriteValue_OpAMD64VPACKSSDW256(v)
	case ssaop.OpAMD64VPACKSSDW512:
		return rewriteValue_OpAMD64VPACKSSDW512(v)
	case ssaop.OpAMD64VPACKSSDWMasked128:
		return rewriteValue_OpAMD64VPACKSSDWMasked128(v)
	case ssaop.OpAMD64VPACKSSDWMasked256:
		return rewriteValue_OpAMD64VPACKSSDWMasked256(v)
	case ssaop.OpAMD64VPACKSSDWMasked512:
		return rewriteValue_OpAMD64VPACKSSDWMasked512(v)
	case ssaop.OpAMD64VPACKUSDW128:
		return rewriteValue_OpAMD64VPACKUSDW128(v)
	case ssaop.OpAMD64VPACKUSDW256:
		return rewriteValue_OpAMD64VPACKUSDW256(v)
	case ssaop.OpAMD64VPACKUSDW512:
		return rewriteValue_OpAMD64VPACKUSDW512(v)
	case ssaop.OpAMD64VPACKUSDWMasked128:
		return rewriteValue_OpAMD64VPACKUSDWMasked128(v)
	case ssaop.OpAMD64VPACKUSDWMasked256:
		return rewriteValue_OpAMD64VPACKUSDWMasked256(v)
	case ssaop.OpAMD64VPACKUSDWMasked512:
		return rewriteValue_OpAMD64VPACKUSDWMasked512(v)
	case ssaop.OpAMD64VPADDB128:
		return rewriteValue_OpAMD64VPADDB128(v)
	case ssaop.OpAMD64VPADDB256:
		return rewriteValue_OpAMD64VPADDB256(v)
	case ssaop.OpAMD64VPADDBMasked128:
		return rewriteValue_OpAMD64VPADDBMasked128(v)
	case ssaop.OpAMD64VPADDBMasked256:
		return rewriteValue_OpAMD64VPADDBMasked256(v)
	case ssaop.OpAMD64VPADDD128:
		return rewriteValue_OpAMD64VPADDD128(v)
	case ssaop.OpAMD64VPADDD256:
		return rewriteValue_OpAMD64VPADDD256(v)
	case ssaop.OpAMD64VPADDD512:
		return rewriteValue_OpAMD64VPADDD512(v)
	case ssaop.OpAMD64VPADDDMasked128:
		return rewriteValue_OpAMD64VPADDDMasked128(v)
	case ssaop.OpAMD64VPADDDMasked256:
		return rewriteValue_OpAMD64VPADDDMasked256(v)
	case ssaop.OpAMD64VPADDDMasked512:
		return rewriteValue_OpAMD64VPADDDMasked512(v)
	case ssaop.OpAMD64VPADDQ128:
		return rewriteValue_OpAMD64VPADDQ128(v)
	case ssaop.OpAMD64VPADDQ256:
		return rewriteValue_OpAMD64VPADDQ256(v)
	case ssaop.OpAMD64VPADDQ512:
		return rewriteValue_OpAMD64VPADDQ512(v)
	case ssaop.OpAMD64VPADDQMasked128:
		return rewriteValue_OpAMD64VPADDQMasked128(v)
	case ssaop.OpAMD64VPADDQMasked256:
		return rewriteValue_OpAMD64VPADDQMasked256(v)
	case ssaop.OpAMD64VPADDQMasked512:
		return rewriteValue_OpAMD64VPADDQMasked512(v)
	case ssaop.OpAMD64VPADDSB128:
		return rewriteValue_OpAMD64VPADDSB128(v)
	case ssaop.OpAMD64VPADDSB256:
		return rewriteValue_OpAMD64VPADDSB256(v)
	case ssaop.OpAMD64VPADDSBMasked128:
		return rewriteValue_OpAMD64VPADDSBMasked128(v)
	case ssaop.OpAMD64VPADDSBMasked256:
		return rewriteValue_OpAMD64VPADDSBMasked256(v)
	case ssaop.OpAMD64VPADDSW128:
		return rewriteValue_OpAMD64VPADDSW128(v)
	case ssaop.OpAMD64VPADDSW256:
		return rewriteValue_OpAMD64VPADDSW256(v)
	case ssaop.OpAMD64VPADDSWMasked128:
		return rewriteValue_OpAMD64VPADDSWMasked128(v)
	case ssaop.OpAMD64VPADDSWMasked256:
		return rewriteValue_OpAMD64VPADDSWMasked256(v)
	case ssaop.OpAMD64VPADDUSB128:
		return rewriteValue_OpAMD64VPADDUSB128(v)
	case ssaop.OpAMD64VPADDUSB256:
		return rewriteValue_OpAMD64VPADDUSB256(v)
	case ssaop.OpAMD64VPADDUSBMasked128:
		return rewriteValue_OpAMD64VPADDUSBMasked128(v)
	case ssaop.OpAMD64VPADDUSBMasked256:
		return rewriteValue_OpAMD64VPADDUSBMasked256(v)
	case ssaop.OpAMD64VPADDUSW128:
		return rewriteValue_OpAMD64VPADDUSW128(v)
	case ssaop.OpAMD64VPADDUSW256:
		return rewriteValue_OpAMD64VPADDUSW256(v)
	case ssaop.OpAMD64VPADDUSWMasked128:
		return rewriteValue_OpAMD64VPADDUSWMasked128(v)
	case ssaop.OpAMD64VPADDUSWMasked256:
		return rewriteValue_OpAMD64VPADDUSWMasked256(v)
	case ssaop.OpAMD64VPADDW128:
		return rewriteValue_OpAMD64VPADDW128(v)
	case ssaop.OpAMD64VPADDW256:
		return rewriteValue_OpAMD64VPADDW256(v)
	case ssaop.OpAMD64VPADDWMasked128:
		return rewriteValue_OpAMD64VPADDWMasked128(v)
	case ssaop.OpAMD64VPADDWMasked256:
		return rewriteValue_OpAMD64VPADDWMasked256(v)
	case ssaop.OpAMD64VPALIGNR128:
		return rewriteValue_OpAMD64VPALIGNR128(v)
	case ssaop.OpAMD64VPALIGNR256:
		return rewriteValue_OpAMD64VPALIGNR256(v)
	case ssaop.OpAMD64VPALIGNRMasked128:
		return rewriteValue_OpAMD64VPALIGNRMasked128(v)
	case ssaop.OpAMD64VPALIGNRMasked256:
		return rewriteValue_OpAMD64VPALIGNRMasked256(v)
	case ssaop.OpAMD64VPAND128:
		return rewriteValue_OpAMD64VPAND128(v)
	case ssaop.OpAMD64VPAND256:
		return rewriteValue_OpAMD64VPAND256(v)
	case ssaop.OpAMD64VPANDD512:
		return rewriteValue_OpAMD64VPANDD512(v)
	case ssaop.OpAMD64VPANDDMasked128:
		return rewriteValue_OpAMD64VPANDDMasked128(v)
	case ssaop.OpAMD64VPANDDMasked256:
		return rewriteValue_OpAMD64VPANDDMasked256(v)
	case ssaop.OpAMD64VPANDDMasked512:
		return rewriteValue_OpAMD64VPANDDMasked512(v)
	case ssaop.OpAMD64VPANDN128:
		return rewriteValue_OpAMD64VPANDN128(v)
	case ssaop.OpAMD64VPANDN256:
		return rewriteValue_OpAMD64VPANDN256(v)
	case ssaop.OpAMD64VPANDND512:
		return rewriteValue_OpAMD64VPANDND512(v)
	case ssaop.OpAMD64VPANDNDMasked128:
		return rewriteValue_OpAMD64VPANDNDMasked128(v)
	case ssaop.OpAMD64VPANDNDMasked256:
		return rewriteValue_OpAMD64VPANDNDMasked256(v)
	case ssaop.OpAMD64VPANDNDMasked512:
		return rewriteValue_OpAMD64VPANDNDMasked512(v)
	case ssaop.OpAMD64VPANDNQ512:
		return rewriteValue_OpAMD64VPANDNQ512(v)
	case ssaop.OpAMD64VPANDNQMasked128:
		return rewriteValue_OpAMD64VPANDNQMasked128(v)
	case ssaop.OpAMD64VPANDNQMasked256:
		return rewriteValue_OpAMD64VPANDNQMasked256(v)
	case ssaop.OpAMD64VPANDNQMasked512:
		return rewriteValue_OpAMD64VPANDNQMasked512(v)
	case ssaop.OpAMD64VPANDQ512:
		return rewriteValue_OpAMD64VPANDQ512(v)
	case ssaop.OpAMD64VPANDQMasked128:
		return rewriteValue_OpAMD64VPANDQMasked128(v)
	case ssaop.OpAMD64VPANDQMasked256:
		return rewriteValue_OpAMD64VPANDQMasked256(v)
	case ssaop.OpAMD64VPANDQMasked512:
		return rewriteValue_OpAMD64VPANDQMasked512(v)
	case ssaop.OpAMD64VPAVGB128:
		return rewriteValue_OpAMD64VPAVGB128(v)
	case ssaop.OpAMD64VPAVGB256:
		return rewriteValue_OpAMD64VPAVGB256(v)
	case ssaop.OpAMD64VPAVGBMasked128:
		return rewriteValue_OpAMD64VPAVGBMasked128(v)
	case ssaop.OpAMD64VPAVGBMasked256:
		return rewriteValue_OpAMD64VPAVGBMasked256(v)
	case ssaop.OpAMD64VPAVGW128:
		return rewriteValue_OpAMD64VPAVGW128(v)
	case ssaop.OpAMD64VPAVGW256:
		return rewriteValue_OpAMD64VPAVGW256(v)
	case ssaop.OpAMD64VPAVGWMasked128:
		return rewriteValue_OpAMD64VPAVGWMasked128(v)
	case ssaop.OpAMD64VPAVGWMasked256:
		return rewriteValue_OpAMD64VPAVGWMasked256(v)
	case ssaop.OpAMD64VPBLENDMBMasked512:
		return rewriteValue_OpAMD64VPBLENDMBMasked512(v)
	case ssaop.OpAMD64VPBLENDMDMasked512:
		return rewriteValue_OpAMD64VPBLENDMDMasked512(v)
	case ssaop.OpAMD64VPBLENDMQMasked512:
		return rewriteValue_OpAMD64VPBLENDMQMasked512(v)
	case ssaop.OpAMD64VPBLENDMWMasked512:
		return rewriteValue_OpAMD64VPBLENDMWMasked512(v)
	case ssaop.OpAMD64VPBLENDVB128:
		return rewriteValue_OpAMD64VPBLENDVB128(v)
	case ssaop.OpAMD64VPBLENDVB256:
		return rewriteValue_OpAMD64VPBLENDVB256(v)
	case ssaop.OpAMD64VPBROADCASTB128:
		return rewriteValue_OpAMD64VPBROADCASTB128(v)
	case ssaop.OpAMD64VPBROADCASTB256:
		return rewriteValue_OpAMD64VPBROADCASTB256(v)
	case ssaop.OpAMD64VPBROADCASTB512:
		return rewriteValue_OpAMD64VPBROADCASTB512(v)
	case ssaop.OpAMD64VPBROADCASTBMasked128:
		return rewriteValue_OpAMD64VPBROADCASTBMasked128(v)
	case ssaop.OpAMD64VPBROADCASTBMasked256:
		return rewriteValue_OpAMD64VPBROADCASTBMasked256(v)
	case ssaop.OpAMD64VPBROADCASTBMasked512:
		return rewriteValue_OpAMD64VPBROADCASTBMasked512(v)
	case ssaop.OpAMD64VPBROADCASTD128:
		return rewriteValue_OpAMD64VPBROADCASTD128(v)
	case ssaop.OpAMD64VPBROADCASTD256:
		return rewriteValue_OpAMD64VPBROADCASTD256(v)
	case ssaop.OpAMD64VPBROADCASTD512:
		return rewriteValue_OpAMD64VPBROADCASTD512(v)
	case ssaop.OpAMD64VPBROADCASTDMasked128:
		return rewriteValue_OpAMD64VPBROADCASTDMasked128(v)
	case ssaop.OpAMD64VPBROADCASTDMasked256:
		return rewriteValue_OpAMD64VPBROADCASTDMasked256(v)
	case ssaop.OpAMD64VPBROADCASTDMasked512:
		return rewriteValue_OpAMD64VPBROADCASTDMasked512(v)
	case ssaop.OpAMD64VPBROADCASTQ128:
		return rewriteValue_OpAMD64VPBROADCASTQ128(v)
	case ssaop.OpAMD64VPBROADCASTQ256:
		return rewriteValue_OpAMD64VPBROADCASTQ256(v)
	case ssaop.OpAMD64VPBROADCASTQ512:
		return rewriteValue_OpAMD64VPBROADCASTQ512(v)
	case ssaop.OpAMD64VPBROADCASTQMasked128:
		return rewriteValue_OpAMD64VPBROADCASTQMasked128(v)
	case ssaop.OpAMD64VPBROADCASTQMasked256:
		return rewriteValue_OpAMD64VPBROADCASTQMasked256(v)
	case ssaop.OpAMD64VPBROADCASTQMasked512:
		return rewriteValue_OpAMD64VPBROADCASTQMasked512(v)
	case ssaop.OpAMD64VPBROADCASTW128:
		return rewriteValue_OpAMD64VPBROADCASTW128(v)
	case ssaop.OpAMD64VPBROADCASTW256:
		return rewriteValue_OpAMD64VPBROADCASTW256(v)
	case ssaop.OpAMD64VPBROADCASTW512:
		return rewriteValue_OpAMD64VPBROADCASTW512(v)
	case ssaop.OpAMD64VPCLMULQDQ128:
		return rewriteValue_OpAMD64VPCLMULQDQ128(v)
	case ssaop.OpAMD64VPCLMULQDQ256:
		return rewriteValue_OpAMD64VPCLMULQDQ256(v)
	case ssaop.OpAMD64VPCMPBMasked128:
		return rewriteValue_OpAMD64VPCMPBMasked128(v)
	case ssaop.OpAMD64VPCMPBMasked256:
		return rewriteValue_OpAMD64VPCMPBMasked256(v)
	case ssaop.OpAMD64VPCMPD512:
		return rewriteValue_OpAMD64VPCMPD512(v)
	case ssaop.OpAMD64VPCMPDMasked128:
		return rewriteValue_OpAMD64VPCMPDMasked128(v)
	case ssaop.OpAMD64VPCMPDMasked256:
		return rewriteValue_OpAMD64VPCMPDMasked256(v)
	case ssaop.OpAMD64VPCMPDMasked512:
		return rewriteValue_OpAMD64VPCMPDMasked512(v)
	case ssaop.OpAMD64VPCMPEQB128:
		return rewriteValue_OpAMD64VPCMPEQB128(v)
	case ssaop.OpAMD64VPCMPEQB256:
		return rewriteValue_OpAMD64VPCMPEQB256(v)
	case ssaop.OpAMD64VPCMPEQD128:
		return rewriteValue_OpAMD64VPCMPEQD128(v)
	case ssaop.OpAMD64VPCMPEQD256:
		return rewriteValue_OpAMD64VPCMPEQD256(v)
	case ssaop.OpAMD64VPCMPEQD512:
		return rewriteValue_OpAMD64VPCMPEQD512(v)
	case ssaop.OpAMD64VPCMPEQQ128:
		return rewriteValue_OpAMD64VPCMPEQQ128(v)
	case ssaop.OpAMD64VPCMPEQQ256:
		return rewriteValue_OpAMD64VPCMPEQQ256(v)
	case ssaop.OpAMD64VPCMPEQQ512:
		return rewriteValue_OpAMD64VPCMPEQQ512(v)
	case ssaop.OpAMD64VPCMPEQW128:
		return rewriteValue_OpAMD64VPCMPEQW128(v)
	case ssaop.OpAMD64VPCMPEQW256:
		return rewriteValue_OpAMD64VPCMPEQW256(v)
	case ssaop.OpAMD64VPCMPGTB128:
		return rewriteValue_OpAMD64VPCMPGTB128(v)
	case ssaop.OpAMD64VPCMPGTB256:
		return rewriteValue_OpAMD64VPCMPGTB256(v)
	case ssaop.OpAMD64VPCMPGTD128:
		return rewriteValue_OpAMD64VPCMPGTD128(v)
	case ssaop.OpAMD64VPCMPGTD256:
		return rewriteValue_OpAMD64VPCMPGTD256(v)
	case ssaop.OpAMD64VPCMPGTD512:
		return rewriteValue_OpAMD64VPCMPGTD512(v)
	case ssaop.OpAMD64VPCMPGTQ128:
		return rewriteValue_OpAMD64VPCMPGTQ128(v)
	case ssaop.OpAMD64VPCMPGTQ256:
		return rewriteValue_OpAMD64VPCMPGTQ256(v)
	case ssaop.OpAMD64VPCMPGTQ512:
		return rewriteValue_OpAMD64VPCMPGTQ512(v)
	case ssaop.OpAMD64VPCMPGTW128:
		return rewriteValue_OpAMD64VPCMPGTW128(v)
	case ssaop.OpAMD64VPCMPGTW256:
		return rewriteValue_OpAMD64VPCMPGTW256(v)
	case ssaop.OpAMD64VPCMPQ512:
		return rewriteValue_OpAMD64VPCMPQ512(v)
	case ssaop.OpAMD64VPCMPQMasked128:
		return rewriteValue_OpAMD64VPCMPQMasked128(v)
	case ssaop.OpAMD64VPCMPQMasked256:
		return rewriteValue_OpAMD64VPCMPQMasked256(v)
	case ssaop.OpAMD64VPCMPQMasked512:
		return rewriteValue_OpAMD64VPCMPQMasked512(v)
	case ssaop.OpAMD64VPCMPUBMasked128:
		return rewriteValue_OpAMD64VPCMPUBMasked128(v)
	case ssaop.OpAMD64VPCMPUBMasked256:
		return rewriteValue_OpAMD64VPCMPUBMasked256(v)
	case ssaop.OpAMD64VPCMPUD512:
		return rewriteValue_OpAMD64VPCMPUD512(v)
	case ssaop.OpAMD64VPCMPUDMasked128:
		return rewriteValue_OpAMD64VPCMPUDMasked128(v)
	case ssaop.OpAMD64VPCMPUDMasked256:
		return rewriteValue_OpAMD64VPCMPUDMasked256(v)
	case ssaop.OpAMD64VPCMPUDMasked512:
		return rewriteValue_OpAMD64VPCMPUDMasked512(v)
	case ssaop.OpAMD64VPCMPUQ512:
		return rewriteValue_OpAMD64VPCMPUQ512(v)
	case ssaop.OpAMD64VPCMPUQMasked128:
		return rewriteValue_OpAMD64VPCMPUQMasked128(v)
	case ssaop.OpAMD64VPCMPUQMasked256:
		return rewriteValue_OpAMD64VPCMPUQMasked256(v)
	case ssaop.OpAMD64VPCMPUQMasked512:
		return rewriteValue_OpAMD64VPCMPUQMasked512(v)
	case ssaop.OpAMD64VPCMPUWMasked128:
		return rewriteValue_OpAMD64VPCMPUWMasked128(v)
	case ssaop.OpAMD64VPCMPUWMasked256:
		return rewriteValue_OpAMD64VPCMPUWMasked256(v)
	case ssaop.OpAMD64VPCMPWMasked128:
		return rewriteValue_OpAMD64VPCMPWMasked128(v)
	case ssaop.OpAMD64VPCMPWMasked256:
		return rewriteValue_OpAMD64VPCMPWMasked256(v)
	case ssaop.OpAMD64VPDPWSSD128:
		return rewriteValue_OpAMD64VPDPWSSD128(v)
	case ssaop.OpAMD64VPDPWSSD256:
		return rewriteValue_OpAMD64VPDPWSSD256(v)
	case ssaop.OpAMD64VPDPWSSD512:
		return rewriteValue_OpAMD64VPDPWSSD512(v)
	case ssaop.OpAMD64VPDPWSSDMasked128:
		return rewriteValue_OpAMD64VPDPWSSDMasked128(v)
	case ssaop.OpAMD64VPDPWSSDMasked256:
		return rewriteValue_OpAMD64VPDPWSSDMasked256(v)
	case ssaop.OpAMD64VPDPWSSDMasked512:
		return rewriteValue_OpAMD64VPDPWSSDMasked512(v)
	case ssaop.OpAMD64VPERM2F128256:
		return rewriteValue_OpAMD64VPERM2F128256(v)
	case ssaop.OpAMD64VPERM2I128256:
		return rewriteValue_OpAMD64VPERM2I128256(v)
	case ssaop.OpAMD64VPERMB128:
		return rewriteValue_OpAMD64VPERMB128(v)
	case ssaop.OpAMD64VPERMB256:
		return rewriteValue_OpAMD64VPERMB256(v)
	case ssaop.OpAMD64VPERMBMasked128:
		return rewriteValue_OpAMD64VPERMBMasked128(v)
	case ssaop.OpAMD64VPERMBMasked256:
		return rewriteValue_OpAMD64VPERMBMasked256(v)
	case ssaop.OpAMD64VPERMD256:
		return rewriteValue_OpAMD64VPERMD256(v)
	case ssaop.OpAMD64VPERMD512:
		return rewriteValue_OpAMD64VPERMD512(v)
	case ssaop.OpAMD64VPERMDMasked256:
		return rewriteValue_OpAMD64VPERMDMasked256(v)
	case ssaop.OpAMD64VPERMDMasked512:
		return rewriteValue_OpAMD64VPERMDMasked512(v)
	case ssaop.OpAMD64VPERMI2B128:
		return rewriteValue_OpAMD64VPERMI2B128(v)
	case ssaop.OpAMD64VPERMI2B256:
		return rewriteValue_OpAMD64VPERMI2B256(v)
	case ssaop.OpAMD64VPERMI2BMasked128:
		return rewriteValue_OpAMD64VPERMI2BMasked128(v)
	case ssaop.OpAMD64VPERMI2BMasked256:
		return rewriteValue_OpAMD64VPERMI2BMasked256(v)
	case ssaop.OpAMD64VPERMI2D128:
		return rewriteValue_OpAMD64VPERMI2D128(v)
	case ssaop.OpAMD64VPERMI2D256:
		return rewriteValue_OpAMD64VPERMI2D256(v)
	case ssaop.OpAMD64VPERMI2D512:
		return rewriteValue_OpAMD64VPERMI2D512(v)
	case ssaop.OpAMD64VPERMI2DMasked128:
		return rewriteValue_OpAMD64VPERMI2DMasked128(v)
	case ssaop.OpAMD64VPERMI2DMasked256:
		return rewriteValue_OpAMD64VPERMI2DMasked256(v)
	case ssaop.OpAMD64VPERMI2DMasked512:
		return rewriteValue_OpAMD64VPERMI2DMasked512(v)
	case ssaop.OpAMD64VPERMI2PD128:
		return rewriteValue_OpAMD64VPERMI2PD128(v)
	case ssaop.OpAMD64VPERMI2PD256:
		return rewriteValue_OpAMD64VPERMI2PD256(v)
	case ssaop.OpAMD64VPERMI2PD512:
		return rewriteValue_OpAMD64VPERMI2PD512(v)
	case ssaop.OpAMD64VPERMI2PDMasked128:
		return rewriteValue_OpAMD64VPERMI2PDMasked128(v)
	case ssaop.OpAMD64VPERMI2PDMasked256:
		return rewriteValue_OpAMD64VPERMI2PDMasked256(v)
	case ssaop.OpAMD64VPERMI2PDMasked512:
		return rewriteValue_OpAMD64VPERMI2PDMasked512(v)
	case ssaop.OpAMD64VPERMI2PS128:
		return rewriteValue_OpAMD64VPERMI2PS128(v)
	case ssaop.OpAMD64VPERMI2PS256:
		return rewriteValue_OpAMD64VPERMI2PS256(v)
	case ssaop.OpAMD64VPERMI2PS512:
		return rewriteValue_OpAMD64VPERMI2PS512(v)
	case ssaop.OpAMD64VPERMI2PSMasked128:
		return rewriteValue_OpAMD64VPERMI2PSMasked128(v)
	case ssaop.OpAMD64VPERMI2PSMasked256:
		return rewriteValue_OpAMD64VPERMI2PSMasked256(v)
	case ssaop.OpAMD64VPERMI2PSMasked512:
		return rewriteValue_OpAMD64VPERMI2PSMasked512(v)
	case ssaop.OpAMD64VPERMI2Q128:
		return rewriteValue_OpAMD64VPERMI2Q128(v)
	case ssaop.OpAMD64VPERMI2Q256:
		return rewriteValue_OpAMD64VPERMI2Q256(v)
	case ssaop.OpAMD64VPERMI2Q512:
		return rewriteValue_OpAMD64VPERMI2Q512(v)
	case ssaop.OpAMD64VPERMI2QMasked128:
		return rewriteValue_OpAMD64VPERMI2QMasked128(v)
	case ssaop.OpAMD64VPERMI2QMasked256:
		return rewriteValue_OpAMD64VPERMI2QMasked256(v)
	case ssaop.OpAMD64VPERMI2QMasked512:
		return rewriteValue_OpAMD64VPERMI2QMasked512(v)
	case ssaop.OpAMD64VPERMI2W128:
		return rewriteValue_OpAMD64VPERMI2W128(v)
	case ssaop.OpAMD64VPERMI2W256:
		return rewriteValue_OpAMD64VPERMI2W256(v)
	case ssaop.OpAMD64VPERMI2WMasked128:
		return rewriteValue_OpAMD64VPERMI2WMasked128(v)
	case ssaop.OpAMD64VPERMI2WMasked256:
		return rewriteValue_OpAMD64VPERMI2WMasked256(v)
	case ssaop.OpAMD64VPERMPD256:
		return rewriteValue_OpAMD64VPERMPD256(v)
	case ssaop.OpAMD64VPERMPD512:
		return rewriteValue_OpAMD64VPERMPD512(v)
	case ssaop.OpAMD64VPERMPDMasked256:
		return rewriteValue_OpAMD64VPERMPDMasked256(v)
	case ssaop.OpAMD64VPERMPDMasked512:
		return rewriteValue_OpAMD64VPERMPDMasked512(v)
	case ssaop.OpAMD64VPERMPS256:
		return rewriteValue_OpAMD64VPERMPS256(v)
	case ssaop.OpAMD64VPERMPS512:
		return rewriteValue_OpAMD64VPERMPS512(v)
	case ssaop.OpAMD64VPERMPSMasked256:
		return rewriteValue_OpAMD64VPERMPSMasked256(v)
	case ssaop.OpAMD64VPERMPSMasked512:
		return rewriteValue_OpAMD64VPERMPSMasked512(v)
	case ssaop.OpAMD64VPERMQ256:
		return rewriteValue_OpAMD64VPERMQ256(v)
	case ssaop.OpAMD64VPERMQ512:
		return rewriteValue_OpAMD64VPERMQ512(v)
	case ssaop.OpAMD64VPERMQMasked256:
		return rewriteValue_OpAMD64VPERMQMasked256(v)
	case ssaop.OpAMD64VPERMQMasked512:
		return rewriteValue_OpAMD64VPERMQMasked512(v)
	case ssaop.OpAMD64VPERMW128:
		return rewriteValue_OpAMD64VPERMW128(v)
	case ssaop.OpAMD64VPERMW256:
		return rewriteValue_OpAMD64VPERMW256(v)
	case ssaop.OpAMD64VPERMWMasked128:
		return rewriteValue_OpAMD64VPERMWMasked128(v)
	case ssaop.OpAMD64VPERMWMasked256:
		return rewriteValue_OpAMD64VPERMWMasked256(v)
	case ssaop.OpAMD64VPEXPANDBMasked128:
		return rewriteValue_OpAMD64VPEXPANDBMasked128(v)
	case ssaop.OpAMD64VPEXPANDBMasked256:
		return rewriteValue_OpAMD64VPEXPANDBMasked256(v)
	case ssaop.OpAMD64VPEXPANDDMasked128:
		return rewriteValue_OpAMD64VPEXPANDDMasked128(v)
	case ssaop.OpAMD64VPEXPANDDMasked256:
		return rewriteValue_OpAMD64VPEXPANDDMasked256(v)
	case ssaop.OpAMD64VPEXPANDQMasked128:
		return rewriteValue_OpAMD64VPEXPANDQMasked128(v)
	case ssaop.OpAMD64VPEXPANDQMasked256:
		return rewriteValue_OpAMD64VPEXPANDQMasked256(v)
	case ssaop.OpAMD64VPEXPANDWMasked128:
		return rewriteValue_OpAMD64VPEXPANDWMasked128(v)
	case ssaop.OpAMD64VPEXPANDWMasked256:
		return rewriteValue_OpAMD64VPEXPANDWMasked256(v)
	case ssaop.OpAMD64VPHADDD128:
		return rewriteValue_OpAMD64VPHADDD128(v)
	case ssaop.OpAMD64VPHADDD256:
		return rewriteValue_OpAMD64VPHADDD256(v)
	case ssaop.OpAMD64VPHADDSW128:
		return rewriteValue_OpAMD64VPHADDSW128(v)
	case ssaop.OpAMD64VPHADDSW256:
		return rewriteValue_OpAMD64VPHADDSW256(v)
	case ssaop.OpAMD64VPHADDW128:
		return rewriteValue_OpAMD64VPHADDW128(v)
	case ssaop.OpAMD64VPHADDW256:
		return rewriteValue_OpAMD64VPHADDW256(v)
	case ssaop.OpAMD64VPHSUBD128:
		return rewriteValue_OpAMD64VPHSUBD128(v)
	case ssaop.OpAMD64VPHSUBD256:
		return rewriteValue_OpAMD64VPHSUBD256(v)
	case ssaop.OpAMD64VPHSUBSW128:
		return rewriteValue_OpAMD64VPHSUBSW128(v)
	case ssaop.OpAMD64VPHSUBSW256:
		return rewriteValue_OpAMD64VPHSUBSW256(v)
	case ssaop.OpAMD64VPHSUBW128:
		return rewriteValue_OpAMD64VPHSUBW128(v)
	case ssaop.OpAMD64VPHSUBW256:
		return rewriteValue_OpAMD64VPHSUBW256(v)
	case ssaop.OpAMD64VPINSRD128:
		return rewriteValue_OpAMD64VPINSRD128(v)
	case ssaop.OpAMD64VPINSRQ128:
		return rewriteValue_OpAMD64VPINSRQ128(v)
	case ssaop.OpAMD64VPLZCNTD128:
		return rewriteValue_OpAMD64VPLZCNTD128(v)
	case ssaop.OpAMD64VPLZCNTD256:
		return rewriteValue_OpAMD64VPLZCNTD256(v)
	case ssaop.OpAMD64VPLZCNTD512:
		return rewriteValue_OpAMD64VPLZCNTD512(v)
	case ssaop.OpAMD64VPLZCNTDMasked128:
		return rewriteValue_OpAMD64VPLZCNTDMasked128(v)
	case ssaop.OpAMD64VPLZCNTDMasked256:
		return rewriteValue_OpAMD64VPLZCNTDMasked256(v)
	case ssaop.OpAMD64VPLZCNTDMasked512:
		return rewriteValue_OpAMD64VPLZCNTDMasked512(v)
	case ssaop.OpAMD64VPLZCNTQ128:
		return rewriteValue_OpAMD64VPLZCNTQ128(v)
	case ssaop.OpAMD64VPLZCNTQ256:
		return rewriteValue_OpAMD64VPLZCNTQ256(v)
	case ssaop.OpAMD64VPLZCNTQ512:
		return rewriteValue_OpAMD64VPLZCNTQ512(v)
	case ssaop.OpAMD64VPLZCNTQMasked128:
		return rewriteValue_OpAMD64VPLZCNTQMasked128(v)
	case ssaop.OpAMD64VPLZCNTQMasked256:
		return rewriteValue_OpAMD64VPLZCNTQMasked256(v)
	case ssaop.OpAMD64VPLZCNTQMasked512:
		return rewriteValue_OpAMD64VPLZCNTQMasked512(v)
	case ssaop.OpAMD64VPMADDUBSW128:
		return rewriteValue_OpAMD64VPMADDUBSW128(v)
	case ssaop.OpAMD64VPMADDUBSW256:
		return rewriteValue_OpAMD64VPMADDUBSW256(v)
	case ssaop.OpAMD64VPMADDUBSWMasked128:
		return rewriteValue_OpAMD64VPMADDUBSWMasked128(v)
	case ssaop.OpAMD64VPMADDUBSWMasked256:
		return rewriteValue_OpAMD64VPMADDUBSWMasked256(v)
	case ssaop.OpAMD64VPMADDWD128:
		return rewriteValue_OpAMD64VPMADDWD128(v)
	case ssaop.OpAMD64VPMADDWD256:
		return rewriteValue_OpAMD64VPMADDWD256(v)
	case ssaop.OpAMD64VPMADDWDMasked128:
		return rewriteValue_OpAMD64VPMADDWDMasked128(v)
	case ssaop.OpAMD64VPMADDWDMasked256:
		return rewriteValue_OpAMD64VPMADDWDMasked256(v)
	case ssaop.OpAMD64VPMAXSB128:
		return rewriteValue_OpAMD64VPMAXSB128(v)
	case ssaop.OpAMD64VPMAXSB256:
		return rewriteValue_OpAMD64VPMAXSB256(v)
	case ssaop.OpAMD64VPMAXSBMasked128:
		return rewriteValue_OpAMD64VPMAXSBMasked128(v)
	case ssaop.OpAMD64VPMAXSBMasked256:
		return rewriteValue_OpAMD64VPMAXSBMasked256(v)
	case ssaop.OpAMD64VPMAXSD128:
		return rewriteValue_OpAMD64VPMAXSD128(v)
	case ssaop.OpAMD64VPMAXSD256:
		return rewriteValue_OpAMD64VPMAXSD256(v)
	case ssaop.OpAMD64VPMAXSD512:
		return rewriteValue_OpAMD64VPMAXSD512(v)
	case ssaop.OpAMD64VPMAXSDMasked128:
		return rewriteValue_OpAMD64VPMAXSDMasked128(v)
	case ssaop.OpAMD64VPMAXSDMasked256:
		return rewriteValue_OpAMD64VPMAXSDMasked256(v)
	case ssaop.OpAMD64VPMAXSDMasked512:
		return rewriteValue_OpAMD64VPMAXSDMasked512(v)
	case ssaop.OpAMD64VPMAXSQ128:
		return rewriteValue_OpAMD64VPMAXSQ128(v)
	case ssaop.OpAMD64VPMAXSQ256:
		return rewriteValue_OpAMD64VPMAXSQ256(v)
	case ssaop.OpAMD64VPMAXSQ512:
		return rewriteValue_OpAMD64VPMAXSQ512(v)
	case ssaop.OpAMD64VPMAXSQMasked128:
		return rewriteValue_OpAMD64VPMAXSQMasked128(v)
	case ssaop.OpAMD64VPMAXSQMasked256:
		return rewriteValue_OpAMD64VPMAXSQMasked256(v)
	case ssaop.OpAMD64VPMAXSQMasked512:
		return rewriteValue_OpAMD64VPMAXSQMasked512(v)
	case ssaop.OpAMD64VPMAXSW128:
		return rewriteValue_OpAMD64VPMAXSW128(v)
	case ssaop.OpAMD64VPMAXSW256:
		return rewriteValue_OpAMD64VPMAXSW256(v)
	case ssaop.OpAMD64VPMAXSWMasked128:
		return rewriteValue_OpAMD64VPMAXSWMasked128(v)
	case ssaop.OpAMD64VPMAXSWMasked256:
		return rewriteValue_OpAMD64VPMAXSWMasked256(v)
	case ssaop.OpAMD64VPMAXUB128:
		return rewriteValue_OpAMD64VPMAXUB128(v)
	case ssaop.OpAMD64VPMAXUB256:
		return rewriteValue_OpAMD64VPMAXUB256(v)
	case ssaop.OpAMD64VPMAXUBMasked128:
		return rewriteValue_OpAMD64VPMAXUBMasked128(v)
	case ssaop.OpAMD64VPMAXUBMasked256:
		return rewriteValue_OpAMD64VPMAXUBMasked256(v)
	case ssaop.OpAMD64VPMAXUD128:
		return rewriteValue_OpAMD64VPMAXUD128(v)
	case ssaop.OpAMD64VPMAXUD256:
		return rewriteValue_OpAMD64VPMAXUD256(v)
	case ssaop.OpAMD64VPMAXUD512:
		return rewriteValue_OpAMD64VPMAXUD512(v)
	case ssaop.OpAMD64VPMAXUDMasked128:
		return rewriteValue_OpAMD64VPMAXUDMasked128(v)
	case ssaop.OpAMD64VPMAXUDMasked256:
		return rewriteValue_OpAMD64VPMAXUDMasked256(v)
	case ssaop.OpAMD64VPMAXUDMasked512:
		return rewriteValue_OpAMD64VPMAXUDMasked512(v)
	case ssaop.OpAMD64VPMAXUQ128:
		return rewriteValue_OpAMD64VPMAXUQ128(v)
	case ssaop.OpAMD64VPMAXUQ256:
		return rewriteValue_OpAMD64VPMAXUQ256(v)
	case ssaop.OpAMD64VPMAXUQ512:
		return rewriteValue_OpAMD64VPMAXUQ512(v)
	case ssaop.OpAMD64VPMAXUQMasked128:
		return rewriteValue_OpAMD64VPMAXUQMasked128(v)
	case ssaop.OpAMD64VPMAXUQMasked256:
		return rewriteValue_OpAMD64VPMAXUQMasked256(v)
	case ssaop.OpAMD64VPMAXUQMasked512:
		return rewriteValue_OpAMD64VPMAXUQMasked512(v)
	case ssaop.OpAMD64VPMAXUW128:
		return rewriteValue_OpAMD64VPMAXUW128(v)
	case ssaop.OpAMD64VPMAXUW256:
		return rewriteValue_OpAMD64VPMAXUW256(v)
	case ssaop.OpAMD64VPMAXUWMasked128:
		return rewriteValue_OpAMD64VPMAXUWMasked128(v)
	case ssaop.OpAMD64VPMAXUWMasked256:
		return rewriteValue_OpAMD64VPMAXUWMasked256(v)
	case ssaop.OpAMD64VPMINSB128:
		return rewriteValue_OpAMD64VPMINSB128(v)
	case ssaop.OpAMD64VPMINSB256:
		return rewriteValue_OpAMD64VPMINSB256(v)
	case ssaop.OpAMD64VPMINSBMasked128:
		return rewriteValue_OpAMD64VPMINSBMasked128(v)
	case ssaop.OpAMD64VPMINSBMasked256:
		return rewriteValue_OpAMD64VPMINSBMasked256(v)
	case ssaop.OpAMD64VPMINSD128:
		return rewriteValue_OpAMD64VPMINSD128(v)
	case ssaop.OpAMD64VPMINSD256:
		return rewriteValue_OpAMD64VPMINSD256(v)
	case ssaop.OpAMD64VPMINSD512:
		return rewriteValue_OpAMD64VPMINSD512(v)
	case ssaop.OpAMD64VPMINSDMasked128:
		return rewriteValue_OpAMD64VPMINSDMasked128(v)
	case ssaop.OpAMD64VPMINSDMasked256:
		return rewriteValue_OpAMD64VPMINSDMasked256(v)
	case ssaop.OpAMD64VPMINSDMasked512:
		return rewriteValue_OpAMD64VPMINSDMasked512(v)
	case ssaop.OpAMD64VPMINSQ128:
		return rewriteValue_OpAMD64VPMINSQ128(v)
	case ssaop.OpAMD64VPMINSQ256:
		return rewriteValue_OpAMD64VPMINSQ256(v)
	case ssaop.OpAMD64VPMINSQ512:
		return rewriteValue_OpAMD64VPMINSQ512(v)
	case ssaop.OpAMD64VPMINSQMasked128:
		return rewriteValue_OpAMD64VPMINSQMasked128(v)
	case ssaop.OpAMD64VPMINSQMasked256:
		return rewriteValue_OpAMD64VPMINSQMasked256(v)
	case ssaop.OpAMD64VPMINSQMasked512:
		return rewriteValue_OpAMD64VPMINSQMasked512(v)
	case ssaop.OpAMD64VPMINSW128:
		return rewriteValue_OpAMD64VPMINSW128(v)
	case ssaop.OpAMD64VPMINSW256:
		return rewriteValue_OpAMD64VPMINSW256(v)
	case ssaop.OpAMD64VPMINSWMasked128:
		return rewriteValue_OpAMD64VPMINSWMasked128(v)
	case ssaop.OpAMD64VPMINSWMasked256:
		return rewriteValue_OpAMD64VPMINSWMasked256(v)
	case ssaop.OpAMD64VPMINUB128:
		return rewriteValue_OpAMD64VPMINUB128(v)
	case ssaop.OpAMD64VPMINUB256:
		return rewriteValue_OpAMD64VPMINUB256(v)
	case ssaop.OpAMD64VPMINUBMasked128:
		return rewriteValue_OpAMD64VPMINUBMasked128(v)
	case ssaop.OpAMD64VPMINUBMasked256:
		return rewriteValue_OpAMD64VPMINUBMasked256(v)
	case ssaop.OpAMD64VPMINUD128:
		return rewriteValue_OpAMD64VPMINUD128(v)
	case ssaop.OpAMD64VPMINUD256:
		return rewriteValue_OpAMD64VPMINUD256(v)
	case ssaop.OpAMD64VPMINUD512:
		return rewriteValue_OpAMD64VPMINUD512(v)
	case ssaop.OpAMD64VPMINUDMasked128:
		return rewriteValue_OpAMD64VPMINUDMasked128(v)
	case ssaop.OpAMD64VPMINUDMasked256:
		return rewriteValue_OpAMD64VPMINUDMasked256(v)
	case ssaop.OpAMD64VPMINUDMasked512:
		return rewriteValue_OpAMD64VPMINUDMasked512(v)
	case ssaop.OpAMD64VPMINUQ128:
		return rewriteValue_OpAMD64VPMINUQ128(v)
	case ssaop.OpAMD64VPMINUQ256:
		return rewriteValue_OpAMD64VPMINUQ256(v)
	case ssaop.OpAMD64VPMINUQ512:
		return rewriteValue_OpAMD64VPMINUQ512(v)
	case ssaop.OpAMD64VPMINUQMasked128:
		return rewriteValue_OpAMD64VPMINUQMasked128(v)
	case ssaop.OpAMD64VPMINUQMasked256:
		return rewriteValue_OpAMD64VPMINUQMasked256(v)
	case ssaop.OpAMD64VPMINUQMasked512:
		return rewriteValue_OpAMD64VPMINUQMasked512(v)
	case ssaop.OpAMD64VPMINUW128:
		return rewriteValue_OpAMD64VPMINUW128(v)
	case ssaop.OpAMD64VPMINUW256:
		return rewriteValue_OpAMD64VPMINUW256(v)
	case ssaop.OpAMD64VPMINUWMasked128:
		return rewriteValue_OpAMD64VPMINUWMasked128(v)
	case ssaop.OpAMD64VPMINUWMasked256:
		return rewriteValue_OpAMD64VPMINUWMasked256(v)
	case ssaop.OpAMD64VPMOVSXBD128:
		return rewriteValue_OpAMD64VPMOVSXBD128(v)
	case ssaop.OpAMD64VPMOVSXBD256:
		return rewriteValue_OpAMD64VPMOVSXBD256(v)
	case ssaop.OpAMD64VPMOVSXBD512:
		return rewriteValue_OpAMD64VPMOVSXBD512(v)
	case ssaop.OpAMD64VPMOVSXBDMasked128:
		return rewriteValue_OpAMD64VPMOVSXBDMasked128(v)
	case ssaop.OpAMD64VPMOVSXBDMasked256:
		return rewriteValue_OpAMD64VPMOVSXBDMasked256(v)
	case ssaop.OpAMD64VPMOVSXBDMasked512:
		return rewriteValue_OpAMD64VPMOVSXBDMasked512(v)
	case ssaop.OpAMD64VPMOVSXBQ128:
		return rewriteValue_OpAMD64VPMOVSXBQ128(v)
	case ssaop.OpAMD64VPMOVSXBQ256:
		return rewriteValue_OpAMD64VPMOVSXBQ256(v)
	case ssaop.OpAMD64VPMOVSXBQ512:
		return rewriteValue_OpAMD64VPMOVSXBQ512(v)
	case ssaop.OpAMD64VPMOVSXBQMasked256:
		return rewriteValue_OpAMD64VPMOVSXBQMasked256(v)
	case ssaop.OpAMD64VPMOVSXBQMasked512:
		return rewriteValue_OpAMD64VPMOVSXBQMasked512(v)
	case ssaop.OpAMD64VPMOVSXBW128:
		return rewriteValue_OpAMD64VPMOVSXBW128(v)
	case ssaop.OpAMD64VPMOVSXBW256:
		return rewriteValue_OpAMD64VPMOVSXBW256(v)
	case ssaop.OpAMD64VPMOVSXBW512:
		return rewriteValue_OpAMD64VPMOVSXBW512(v)
	case ssaop.OpAMD64VPMOVSXBWMasked128:
		return rewriteValue_OpAMD64VPMOVSXBWMasked128(v)
	case ssaop.OpAMD64VPMOVSXBWMasked256:
		return rewriteValue_OpAMD64VPMOVSXBWMasked256(v)
	case ssaop.OpAMD64VPMOVSXBWMasked512:
		return rewriteValue_OpAMD64VPMOVSXBWMasked512(v)
	case ssaop.OpAMD64VPMOVSXDQ128:
		return rewriteValue_OpAMD64VPMOVSXDQ128(v)
	case ssaop.OpAMD64VPMOVSXDQ256:
		return rewriteValue_OpAMD64VPMOVSXDQ256(v)
	case ssaop.OpAMD64VPMOVSXDQ512:
		return rewriteValue_OpAMD64VPMOVSXDQ512(v)
	case ssaop.OpAMD64VPMOVSXDQMasked128:
		return rewriteValue_OpAMD64VPMOVSXDQMasked128(v)
	case ssaop.OpAMD64VPMOVSXDQMasked256:
		return rewriteValue_OpAMD64VPMOVSXDQMasked256(v)
	case ssaop.OpAMD64VPMOVSXDQMasked512:
		return rewriteValue_OpAMD64VPMOVSXDQMasked512(v)
	case ssaop.OpAMD64VPMOVSXWD128:
		return rewriteValue_OpAMD64VPMOVSXWD128(v)
	case ssaop.OpAMD64VPMOVSXWD256:
		return rewriteValue_OpAMD64VPMOVSXWD256(v)
	case ssaop.OpAMD64VPMOVSXWD512:
		return rewriteValue_OpAMD64VPMOVSXWD512(v)
	case ssaop.OpAMD64VPMOVSXWDMasked128:
		return rewriteValue_OpAMD64VPMOVSXWDMasked128(v)
	case ssaop.OpAMD64VPMOVSXWDMasked256:
		return rewriteValue_OpAMD64VPMOVSXWDMasked256(v)
	case ssaop.OpAMD64VPMOVSXWDMasked512:
		return rewriteValue_OpAMD64VPMOVSXWDMasked512(v)
	case ssaop.OpAMD64VPMOVSXWQ128:
		return rewriteValue_OpAMD64VPMOVSXWQ128(v)
	case ssaop.OpAMD64VPMOVSXWQ256:
		return rewriteValue_OpAMD64VPMOVSXWQ256(v)
	case ssaop.OpAMD64VPMOVSXWQ512:
		return rewriteValue_OpAMD64VPMOVSXWQ512(v)
	case ssaop.OpAMD64VPMOVSXWQMasked128:
		return rewriteValue_OpAMD64VPMOVSXWQMasked128(v)
	case ssaop.OpAMD64VPMOVSXWQMasked256:
		return rewriteValue_OpAMD64VPMOVSXWQMasked256(v)
	case ssaop.OpAMD64VPMOVSXWQMasked512:
		return rewriteValue_OpAMD64VPMOVSXWQMasked512(v)
	case ssaop.OpAMD64VPMOVVec16x16ToM:
		return rewriteValue_OpAMD64VPMOVVec16x16ToM(v)
	case ssaop.OpAMD64VPMOVVec16x32ToM:
		return rewriteValue_OpAMD64VPMOVVec16x32ToM(v)
	case ssaop.OpAMD64VPMOVVec16x8ToM:
		return rewriteValue_OpAMD64VPMOVVec16x8ToM(v)
	case ssaop.OpAMD64VPMOVVec32x16ToM:
		return rewriteValue_OpAMD64VPMOVVec32x16ToM(v)
	case ssaop.OpAMD64VPMOVVec32x4ToM:
		return rewriteValue_OpAMD64VPMOVVec32x4ToM(v)
	case ssaop.OpAMD64VPMOVVec32x8ToM:
		return rewriteValue_OpAMD64VPMOVVec32x8ToM(v)
	case ssaop.OpAMD64VPMOVVec64x2ToM:
		return rewriteValue_OpAMD64VPMOVVec64x2ToM(v)
	case ssaop.OpAMD64VPMOVVec64x4ToM:
		return rewriteValue_OpAMD64VPMOVVec64x4ToM(v)
	case ssaop.OpAMD64VPMOVVec64x8ToM:
		return rewriteValue_OpAMD64VPMOVVec64x8ToM(v)
	case ssaop.OpAMD64VPMOVVec8x16ToM:
		return rewriteValue_OpAMD64VPMOVVec8x16ToM(v)
	case ssaop.OpAMD64VPMOVVec8x32ToM:
		return rewriteValue_OpAMD64VPMOVVec8x32ToM(v)
	case ssaop.OpAMD64VPMOVVec8x64ToM:
		return rewriteValue_OpAMD64VPMOVVec8x64ToM(v)
	case ssaop.OpAMD64VPMOVZXBD128:
		return rewriteValue_OpAMD64VPMOVZXBD128(v)
	case ssaop.OpAMD64VPMOVZXBD256:
		return rewriteValue_OpAMD64VPMOVZXBD256(v)
	case ssaop.OpAMD64VPMOVZXBD512:
		return rewriteValue_OpAMD64VPMOVZXBD512(v)
	case ssaop.OpAMD64VPMOVZXBDMasked128:
		return rewriteValue_OpAMD64VPMOVZXBDMasked128(v)
	case ssaop.OpAMD64VPMOVZXBDMasked256:
		return rewriteValue_OpAMD64VPMOVZXBDMasked256(v)
	case ssaop.OpAMD64VPMOVZXBDMasked512:
		return rewriteValue_OpAMD64VPMOVZXBDMasked512(v)
	case ssaop.OpAMD64VPMOVZXBQ128:
		return rewriteValue_OpAMD64VPMOVZXBQ128(v)
	case ssaop.OpAMD64VPMOVZXBQ256:
		return rewriteValue_OpAMD64VPMOVZXBQ256(v)
	case ssaop.OpAMD64VPMOVZXBQ512:
		return rewriteValue_OpAMD64VPMOVZXBQ512(v)
	case ssaop.OpAMD64VPMOVZXBQMasked256:
		return rewriteValue_OpAMD64VPMOVZXBQMasked256(v)
	case ssaop.OpAMD64VPMOVZXBQMasked512:
		return rewriteValue_OpAMD64VPMOVZXBQMasked512(v)
	case ssaop.OpAMD64VPMOVZXBW128:
		return rewriteValue_OpAMD64VPMOVZXBW128(v)
	case ssaop.OpAMD64VPMOVZXBW256:
		return rewriteValue_OpAMD64VPMOVZXBW256(v)
	case ssaop.OpAMD64VPMOVZXBW512:
		return rewriteValue_OpAMD64VPMOVZXBW512(v)
	case ssaop.OpAMD64VPMOVZXBWMasked128:
		return rewriteValue_OpAMD64VPMOVZXBWMasked128(v)
	case ssaop.OpAMD64VPMOVZXBWMasked256:
		return rewriteValue_OpAMD64VPMOVZXBWMasked256(v)
	case ssaop.OpAMD64VPMOVZXBWMasked512:
		return rewriteValue_OpAMD64VPMOVZXBWMasked512(v)
	case ssaop.OpAMD64VPMOVZXDQ128:
		return rewriteValue_OpAMD64VPMOVZXDQ128(v)
	case ssaop.OpAMD64VPMOVZXDQ256:
		return rewriteValue_OpAMD64VPMOVZXDQ256(v)
	case ssaop.OpAMD64VPMOVZXDQ512:
		return rewriteValue_OpAMD64VPMOVZXDQ512(v)
	case ssaop.OpAMD64VPMOVZXDQMasked128:
		return rewriteValue_OpAMD64VPMOVZXDQMasked128(v)
	case ssaop.OpAMD64VPMOVZXDQMasked256:
		return rewriteValue_OpAMD64VPMOVZXDQMasked256(v)
	case ssaop.OpAMD64VPMOVZXDQMasked512:
		return rewriteValue_OpAMD64VPMOVZXDQMasked512(v)
	case ssaop.OpAMD64VPMOVZXWD128:
		return rewriteValue_OpAMD64VPMOVZXWD128(v)
	case ssaop.OpAMD64VPMOVZXWD256:
		return rewriteValue_OpAMD64VPMOVZXWD256(v)
	case ssaop.OpAMD64VPMOVZXWD512:
		return rewriteValue_OpAMD64VPMOVZXWD512(v)
	case ssaop.OpAMD64VPMOVZXWDMasked128:
		return rewriteValue_OpAMD64VPMOVZXWDMasked128(v)
	case ssaop.OpAMD64VPMOVZXWDMasked256:
		return rewriteValue_OpAMD64VPMOVZXWDMasked256(v)
	case ssaop.OpAMD64VPMOVZXWDMasked512:
		return rewriteValue_OpAMD64VPMOVZXWDMasked512(v)
	case ssaop.OpAMD64VPMOVZXWQ128:
		return rewriteValue_OpAMD64VPMOVZXWQ128(v)
	case ssaop.OpAMD64VPMOVZXWQ256:
		return rewriteValue_OpAMD64VPMOVZXWQ256(v)
	case ssaop.OpAMD64VPMOVZXWQ512:
		return rewriteValue_OpAMD64VPMOVZXWQ512(v)
	case ssaop.OpAMD64VPMOVZXWQMasked128:
		return rewriteValue_OpAMD64VPMOVZXWQMasked128(v)
	case ssaop.OpAMD64VPMOVZXWQMasked256:
		return rewriteValue_OpAMD64VPMOVZXWQMasked256(v)
	case ssaop.OpAMD64VPMOVZXWQMasked512:
		return rewriteValue_OpAMD64VPMOVZXWQMasked512(v)
	case ssaop.OpAMD64VPMULDQ128:
		return rewriteValue_OpAMD64VPMULDQ128(v)
	case ssaop.OpAMD64VPMULDQ256:
		return rewriteValue_OpAMD64VPMULDQ256(v)
	case ssaop.OpAMD64VPMULHUW128:
		return rewriteValue_OpAMD64VPMULHUW128(v)
	case ssaop.OpAMD64VPMULHUW256:
		return rewriteValue_OpAMD64VPMULHUW256(v)
	case ssaop.OpAMD64VPMULHUWMasked128:
		return rewriteValue_OpAMD64VPMULHUWMasked128(v)
	case ssaop.OpAMD64VPMULHUWMasked256:
		return rewriteValue_OpAMD64VPMULHUWMasked256(v)
	case ssaop.OpAMD64VPMULHW128:
		return rewriteValue_OpAMD64VPMULHW128(v)
	case ssaop.OpAMD64VPMULHW256:
		return rewriteValue_OpAMD64VPMULHW256(v)
	case ssaop.OpAMD64VPMULHWMasked128:
		return rewriteValue_OpAMD64VPMULHWMasked128(v)
	case ssaop.OpAMD64VPMULHWMasked256:
		return rewriteValue_OpAMD64VPMULHWMasked256(v)
	case ssaop.OpAMD64VPMULLD128:
		return rewriteValue_OpAMD64VPMULLD128(v)
	case ssaop.OpAMD64VPMULLD256:
		return rewriteValue_OpAMD64VPMULLD256(v)
	case ssaop.OpAMD64VPMULLD512:
		return rewriteValue_OpAMD64VPMULLD512(v)
	case ssaop.OpAMD64VPMULLDMasked128:
		return rewriteValue_OpAMD64VPMULLDMasked128(v)
	case ssaop.OpAMD64VPMULLDMasked256:
		return rewriteValue_OpAMD64VPMULLDMasked256(v)
	case ssaop.OpAMD64VPMULLDMasked512:
		return rewriteValue_OpAMD64VPMULLDMasked512(v)
	case ssaop.OpAMD64VPMULLQ128:
		return rewriteValue_OpAMD64VPMULLQ128(v)
	case ssaop.OpAMD64VPMULLQ256:
		return rewriteValue_OpAMD64VPMULLQ256(v)
	case ssaop.OpAMD64VPMULLQ512:
		return rewriteValue_OpAMD64VPMULLQ512(v)
	case ssaop.OpAMD64VPMULLQMasked128:
		return rewriteValue_OpAMD64VPMULLQMasked128(v)
	case ssaop.OpAMD64VPMULLQMasked256:
		return rewriteValue_OpAMD64VPMULLQMasked256(v)
	case ssaop.OpAMD64VPMULLQMasked512:
		return rewriteValue_OpAMD64VPMULLQMasked512(v)
	case ssaop.OpAMD64VPMULLW128:
		return rewriteValue_OpAMD64VPMULLW128(v)
	case ssaop.OpAMD64VPMULLW256:
		return rewriteValue_OpAMD64VPMULLW256(v)
	case ssaop.OpAMD64VPMULLW512:
		return rewriteValue_OpAMD64VPMULLW512(v)
	case ssaop.OpAMD64VPMULLWMasked128:
		return rewriteValue_OpAMD64VPMULLWMasked128(v)
	case ssaop.OpAMD64VPMULLWMasked256:
		return rewriteValue_OpAMD64VPMULLWMasked256(v)
	case ssaop.OpAMD64VPMULUDQ128:
		return rewriteValue_OpAMD64VPMULUDQ128(v)
	case ssaop.OpAMD64VPMULUDQ256:
		return rewriteValue_OpAMD64VPMULUDQ256(v)
	case ssaop.OpAMD64VPOPCNTB128:
		return rewriteValue_OpAMD64VPOPCNTB128(v)
	case ssaop.OpAMD64VPOPCNTB256:
		return rewriteValue_OpAMD64VPOPCNTB256(v)
	case ssaop.OpAMD64VPOPCNTBMasked128:
		return rewriteValue_OpAMD64VPOPCNTBMasked128(v)
	case ssaop.OpAMD64VPOPCNTBMasked256:
		return rewriteValue_OpAMD64VPOPCNTBMasked256(v)
	case ssaop.OpAMD64VPOPCNTD128:
		return rewriteValue_OpAMD64VPOPCNTD128(v)
	case ssaop.OpAMD64VPOPCNTD256:
		return rewriteValue_OpAMD64VPOPCNTD256(v)
	case ssaop.OpAMD64VPOPCNTD512:
		return rewriteValue_OpAMD64VPOPCNTD512(v)
	case ssaop.OpAMD64VPOPCNTDMasked128:
		return rewriteValue_OpAMD64VPOPCNTDMasked128(v)
	case ssaop.OpAMD64VPOPCNTDMasked256:
		return rewriteValue_OpAMD64VPOPCNTDMasked256(v)
	case ssaop.OpAMD64VPOPCNTDMasked512:
		return rewriteValue_OpAMD64VPOPCNTDMasked512(v)
	case ssaop.OpAMD64VPOPCNTQ128:
		return rewriteValue_OpAMD64VPOPCNTQ128(v)
	case ssaop.OpAMD64VPOPCNTQ256:
		return rewriteValue_OpAMD64VPOPCNTQ256(v)
	case ssaop.OpAMD64VPOPCNTQ512:
		return rewriteValue_OpAMD64VPOPCNTQ512(v)
	case ssaop.OpAMD64VPOPCNTQMasked128:
		return rewriteValue_OpAMD64VPOPCNTQMasked128(v)
	case ssaop.OpAMD64VPOPCNTQMasked256:
		return rewriteValue_OpAMD64VPOPCNTQMasked256(v)
	case ssaop.OpAMD64VPOPCNTQMasked512:
		return rewriteValue_OpAMD64VPOPCNTQMasked512(v)
	case ssaop.OpAMD64VPOPCNTW128:
		return rewriteValue_OpAMD64VPOPCNTW128(v)
	case ssaop.OpAMD64VPOPCNTW256:
		return rewriteValue_OpAMD64VPOPCNTW256(v)
	case ssaop.OpAMD64VPOPCNTWMasked128:
		return rewriteValue_OpAMD64VPOPCNTWMasked128(v)
	case ssaop.OpAMD64VPOPCNTWMasked256:
		return rewriteValue_OpAMD64VPOPCNTWMasked256(v)
	case ssaop.OpAMD64VPOR128:
		return rewriteValue_OpAMD64VPOR128(v)
	case ssaop.OpAMD64VPOR256:
		return rewriteValue_OpAMD64VPOR256(v)
	case ssaop.OpAMD64VPORD512:
		return rewriteValue_OpAMD64VPORD512(v)
	case ssaop.OpAMD64VPORDMasked128:
		return rewriteValue_OpAMD64VPORDMasked128(v)
	case ssaop.OpAMD64VPORDMasked256:
		return rewriteValue_OpAMD64VPORDMasked256(v)
	case ssaop.OpAMD64VPORDMasked512:
		return rewriteValue_OpAMD64VPORDMasked512(v)
	case ssaop.OpAMD64VPORQ512:
		return rewriteValue_OpAMD64VPORQ512(v)
	case ssaop.OpAMD64VPORQMasked128:
		return rewriteValue_OpAMD64VPORQMasked128(v)
	case ssaop.OpAMD64VPORQMasked256:
		return rewriteValue_OpAMD64VPORQMasked256(v)
	case ssaop.OpAMD64VPORQMasked512:
		return rewriteValue_OpAMD64VPORQMasked512(v)
	case ssaop.OpAMD64VPROLD128:
		return rewriteValue_OpAMD64VPROLD128(v)
	case ssaop.OpAMD64VPROLD256:
		return rewriteValue_OpAMD64VPROLD256(v)
	case ssaop.OpAMD64VPROLD512:
		return rewriteValue_OpAMD64VPROLD512(v)
	case ssaop.OpAMD64VPROLDMasked128:
		return rewriteValue_OpAMD64VPROLDMasked128(v)
	case ssaop.OpAMD64VPROLDMasked256:
		return rewriteValue_OpAMD64VPROLDMasked256(v)
	case ssaop.OpAMD64VPROLDMasked512:
		return rewriteValue_OpAMD64VPROLDMasked512(v)
	case ssaop.OpAMD64VPROLQ128:
		return rewriteValue_OpAMD64VPROLQ128(v)
	case ssaop.OpAMD64VPROLQ256:
		return rewriteValue_OpAMD64VPROLQ256(v)
	case ssaop.OpAMD64VPROLQ512:
		return rewriteValue_OpAMD64VPROLQ512(v)
	case ssaop.OpAMD64VPROLQMasked128:
		return rewriteValue_OpAMD64VPROLQMasked128(v)
	case ssaop.OpAMD64VPROLQMasked256:
		return rewriteValue_OpAMD64VPROLQMasked256(v)
	case ssaop.OpAMD64VPROLQMasked512:
		return rewriteValue_OpAMD64VPROLQMasked512(v)
	case ssaop.OpAMD64VPROLVD128:
		return rewriteValue_OpAMD64VPROLVD128(v)
	case ssaop.OpAMD64VPROLVD256:
		return rewriteValue_OpAMD64VPROLVD256(v)
	case ssaop.OpAMD64VPROLVD512:
		return rewriteValue_OpAMD64VPROLVD512(v)
	case ssaop.OpAMD64VPROLVDMasked128:
		return rewriteValue_OpAMD64VPROLVDMasked128(v)
	case ssaop.OpAMD64VPROLVDMasked256:
		return rewriteValue_OpAMD64VPROLVDMasked256(v)
	case ssaop.OpAMD64VPROLVDMasked512:
		return rewriteValue_OpAMD64VPROLVDMasked512(v)
	case ssaop.OpAMD64VPROLVQ128:
		return rewriteValue_OpAMD64VPROLVQ128(v)
	case ssaop.OpAMD64VPROLVQ256:
		return rewriteValue_OpAMD64VPROLVQ256(v)
	case ssaop.OpAMD64VPROLVQ512:
		return rewriteValue_OpAMD64VPROLVQ512(v)
	case ssaop.OpAMD64VPROLVQMasked128:
		return rewriteValue_OpAMD64VPROLVQMasked128(v)
	case ssaop.OpAMD64VPROLVQMasked256:
		return rewriteValue_OpAMD64VPROLVQMasked256(v)
	case ssaop.OpAMD64VPROLVQMasked512:
		return rewriteValue_OpAMD64VPROLVQMasked512(v)
	case ssaop.OpAMD64VPRORD128:
		return rewriteValue_OpAMD64VPRORD128(v)
	case ssaop.OpAMD64VPRORD256:
		return rewriteValue_OpAMD64VPRORD256(v)
	case ssaop.OpAMD64VPRORD512:
		return rewriteValue_OpAMD64VPRORD512(v)
	case ssaop.OpAMD64VPRORDMasked128:
		return rewriteValue_OpAMD64VPRORDMasked128(v)
	case ssaop.OpAMD64VPRORDMasked256:
		return rewriteValue_OpAMD64VPRORDMasked256(v)
	case ssaop.OpAMD64VPRORDMasked512:
		return rewriteValue_OpAMD64VPRORDMasked512(v)
	case ssaop.OpAMD64VPRORQ128:
		return rewriteValue_OpAMD64VPRORQ128(v)
	case ssaop.OpAMD64VPRORQ256:
		return rewriteValue_OpAMD64VPRORQ256(v)
	case ssaop.OpAMD64VPRORQ512:
		return rewriteValue_OpAMD64VPRORQ512(v)
	case ssaop.OpAMD64VPRORQMasked128:
		return rewriteValue_OpAMD64VPRORQMasked128(v)
	case ssaop.OpAMD64VPRORQMasked256:
		return rewriteValue_OpAMD64VPRORQMasked256(v)
	case ssaop.OpAMD64VPRORQMasked512:
		return rewriteValue_OpAMD64VPRORQMasked512(v)
	case ssaop.OpAMD64VPRORVD128:
		return rewriteValue_OpAMD64VPRORVD128(v)
	case ssaop.OpAMD64VPRORVD256:
		return rewriteValue_OpAMD64VPRORVD256(v)
	case ssaop.OpAMD64VPRORVD512:
		return rewriteValue_OpAMD64VPRORVD512(v)
	case ssaop.OpAMD64VPRORVDMasked128:
		return rewriteValue_OpAMD64VPRORVDMasked128(v)
	case ssaop.OpAMD64VPRORVDMasked256:
		return rewriteValue_OpAMD64VPRORVDMasked256(v)
	case ssaop.OpAMD64VPRORVDMasked512:
		return rewriteValue_OpAMD64VPRORVDMasked512(v)
	case ssaop.OpAMD64VPRORVQ128:
		return rewriteValue_OpAMD64VPRORVQ128(v)
	case ssaop.OpAMD64VPRORVQ256:
		return rewriteValue_OpAMD64VPRORVQ256(v)
	case ssaop.OpAMD64VPRORVQ512:
		return rewriteValue_OpAMD64VPRORVQ512(v)
	case ssaop.OpAMD64VPRORVQMasked128:
		return rewriteValue_OpAMD64VPRORVQMasked128(v)
	case ssaop.OpAMD64VPRORVQMasked256:
		return rewriteValue_OpAMD64VPRORVQMasked256(v)
	case ssaop.OpAMD64VPRORVQMasked512:
		return rewriteValue_OpAMD64VPRORVQMasked512(v)
	case ssaop.OpAMD64VPSADBW128:
		return rewriteValue_OpAMD64VPSADBW128(v)
	case ssaop.OpAMD64VPSADBW256:
		return rewriteValue_OpAMD64VPSADBW256(v)
	case ssaop.OpAMD64VPSHLDD128:
		return rewriteValue_OpAMD64VPSHLDD128(v)
	case ssaop.OpAMD64VPSHLDD256:
		return rewriteValue_OpAMD64VPSHLDD256(v)
	case ssaop.OpAMD64VPSHLDD512:
		return rewriteValue_OpAMD64VPSHLDD512(v)
	case ssaop.OpAMD64VPSHLDDMasked128:
		return rewriteValue_OpAMD64VPSHLDDMasked128(v)
	case ssaop.OpAMD64VPSHLDDMasked256:
		return rewriteValue_OpAMD64VPSHLDDMasked256(v)
	case ssaop.OpAMD64VPSHLDDMasked512:
		return rewriteValue_OpAMD64VPSHLDDMasked512(v)
	case ssaop.OpAMD64VPSHLDQ128:
		return rewriteValue_OpAMD64VPSHLDQ128(v)
	case ssaop.OpAMD64VPSHLDQ256:
		return rewriteValue_OpAMD64VPSHLDQ256(v)
	case ssaop.OpAMD64VPSHLDQ512:
		return rewriteValue_OpAMD64VPSHLDQ512(v)
	case ssaop.OpAMD64VPSHLDQMasked128:
		return rewriteValue_OpAMD64VPSHLDQMasked128(v)
	case ssaop.OpAMD64VPSHLDQMasked256:
		return rewriteValue_OpAMD64VPSHLDQMasked256(v)
	case ssaop.OpAMD64VPSHLDQMasked512:
		return rewriteValue_OpAMD64VPSHLDQMasked512(v)
	case ssaop.OpAMD64VPSHLDVD128:
		return rewriteValue_OpAMD64VPSHLDVD128(v)
	case ssaop.OpAMD64VPSHLDVD256:
		return rewriteValue_OpAMD64VPSHLDVD256(v)
	case ssaop.OpAMD64VPSHLDVD512:
		return rewriteValue_OpAMD64VPSHLDVD512(v)
	case ssaop.OpAMD64VPSHLDVDMasked128:
		return rewriteValue_OpAMD64VPSHLDVDMasked128(v)
	case ssaop.OpAMD64VPSHLDVDMasked256:
		return rewriteValue_OpAMD64VPSHLDVDMasked256(v)
	case ssaop.OpAMD64VPSHLDVDMasked512:
		return rewriteValue_OpAMD64VPSHLDVDMasked512(v)
	case ssaop.OpAMD64VPSHLDVQ128:
		return rewriteValue_OpAMD64VPSHLDVQ128(v)
	case ssaop.OpAMD64VPSHLDVQ256:
		return rewriteValue_OpAMD64VPSHLDVQ256(v)
	case ssaop.OpAMD64VPSHLDVQ512:
		return rewriteValue_OpAMD64VPSHLDVQ512(v)
	case ssaop.OpAMD64VPSHLDVQMasked128:
		return rewriteValue_OpAMD64VPSHLDVQMasked128(v)
	case ssaop.OpAMD64VPSHLDVQMasked256:
		return rewriteValue_OpAMD64VPSHLDVQMasked256(v)
	case ssaop.OpAMD64VPSHLDVQMasked512:
		return rewriteValue_OpAMD64VPSHLDVQMasked512(v)
	case ssaop.OpAMD64VPSHLDVW128:
		return rewriteValue_OpAMD64VPSHLDVW128(v)
	case ssaop.OpAMD64VPSHLDVW256:
		return rewriteValue_OpAMD64VPSHLDVW256(v)
	case ssaop.OpAMD64VPSHLDVWMasked128:
		return rewriteValue_OpAMD64VPSHLDVWMasked128(v)
	case ssaop.OpAMD64VPSHLDVWMasked256:
		return rewriteValue_OpAMD64VPSHLDVWMasked256(v)
	case ssaop.OpAMD64VPSHLDW128:
		return rewriteValue_OpAMD64VPSHLDW128(v)
	case ssaop.OpAMD64VPSHLDW256:
		return rewriteValue_OpAMD64VPSHLDW256(v)
	case ssaop.OpAMD64VPSHLDWMasked128:
		return rewriteValue_OpAMD64VPSHLDWMasked128(v)
	case ssaop.OpAMD64VPSHLDWMasked256:
		return rewriteValue_OpAMD64VPSHLDWMasked256(v)
	case ssaop.OpAMD64VPSHRDD128:
		return rewriteValue_OpAMD64VPSHRDD128(v)
	case ssaop.OpAMD64VPSHRDD256:
		return rewriteValue_OpAMD64VPSHRDD256(v)
	case ssaop.OpAMD64VPSHRDD512:
		return rewriteValue_OpAMD64VPSHRDD512(v)
	case ssaop.OpAMD64VPSHRDDMasked128:
		return rewriteValue_OpAMD64VPSHRDDMasked128(v)
	case ssaop.OpAMD64VPSHRDDMasked256:
		return rewriteValue_OpAMD64VPSHRDDMasked256(v)
	case ssaop.OpAMD64VPSHRDDMasked512:
		return rewriteValue_OpAMD64VPSHRDDMasked512(v)
	case ssaop.OpAMD64VPSHRDQ128:
		return rewriteValue_OpAMD64VPSHRDQ128(v)
	case ssaop.OpAMD64VPSHRDQ256:
		return rewriteValue_OpAMD64VPSHRDQ256(v)
	case ssaop.OpAMD64VPSHRDQ512:
		return rewriteValue_OpAMD64VPSHRDQ512(v)
	case ssaop.OpAMD64VPSHRDQMasked128:
		return rewriteValue_OpAMD64VPSHRDQMasked128(v)
	case ssaop.OpAMD64VPSHRDQMasked256:
		return rewriteValue_OpAMD64VPSHRDQMasked256(v)
	case ssaop.OpAMD64VPSHRDQMasked512:
		return rewriteValue_OpAMD64VPSHRDQMasked512(v)
	case ssaop.OpAMD64VPSHRDVD128:
		return rewriteValue_OpAMD64VPSHRDVD128(v)
	case ssaop.OpAMD64VPSHRDVD256:
		return rewriteValue_OpAMD64VPSHRDVD256(v)
	case ssaop.OpAMD64VPSHRDVD512:
		return rewriteValue_OpAMD64VPSHRDVD512(v)
	case ssaop.OpAMD64VPSHRDVDMasked128:
		return rewriteValue_OpAMD64VPSHRDVDMasked128(v)
	case ssaop.OpAMD64VPSHRDVDMasked256:
		return rewriteValue_OpAMD64VPSHRDVDMasked256(v)
	case ssaop.OpAMD64VPSHRDVDMasked512:
		return rewriteValue_OpAMD64VPSHRDVDMasked512(v)
	case ssaop.OpAMD64VPSHRDVQ128:
		return rewriteValue_OpAMD64VPSHRDVQ128(v)
	case ssaop.OpAMD64VPSHRDVQ256:
		return rewriteValue_OpAMD64VPSHRDVQ256(v)
	case ssaop.OpAMD64VPSHRDVQ512:
		return rewriteValue_OpAMD64VPSHRDVQ512(v)
	case ssaop.OpAMD64VPSHRDVQMasked128:
		return rewriteValue_OpAMD64VPSHRDVQMasked128(v)
	case ssaop.OpAMD64VPSHRDVQMasked256:
		return rewriteValue_OpAMD64VPSHRDVQMasked256(v)
	case ssaop.OpAMD64VPSHRDVQMasked512:
		return rewriteValue_OpAMD64VPSHRDVQMasked512(v)
	case ssaop.OpAMD64VPSHRDVW128:
		return rewriteValue_OpAMD64VPSHRDVW128(v)
	case ssaop.OpAMD64VPSHRDVW256:
		return rewriteValue_OpAMD64VPSHRDVW256(v)
	case ssaop.OpAMD64VPSHRDVWMasked128:
		return rewriteValue_OpAMD64VPSHRDVWMasked128(v)
	case ssaop.OpAMD64VPSHRDVWMasked256:
		return rewriteValue_OpAMD64VPSHRDVWMasked256(v)
	case ssaop.OpAMD64VPSHRDW128:
		return rewriteValue_OpAMD64VPSHRDW128(v)
	case ssaop.OpAMD64VPSHRDW256:
		return rewriteValue_OpAMD64VPSHRDW256(v)
	case ssaop.OpAMD64VPSHRDWMasked128:
		return rewriteValue_OpAMD64VPSHRDWMasked128(v)
	case ssaop.OpAMD64VPSHRDWMasked256:
		return rewriteValue_OpAMD64VPSHRDWMasked256(v)
	case ssaop.OpAMD64VPSHUFB128:
		return rewriteValue_OpAMD64VPSHUFB128(v)
	case ssaop.OpAMD64VPSHUFB256:
		return rewriteValue_OpAMD64VPSHUFB256(v)
	case ssaop.OpAMD64VPSHUFBMasked128:
		return rewriteValue_OpAMD64VPSHUFBMasked128(v)
	case ssaop.OpAMD64VPSHUFBMasked256:
		return rewriteValue_OpAMD64VPSHUFBMasked256(v)
	case ssaop.OpAMD64VPSHUFD128:
		return rewriteValue_OpAMD64VPSHUFD128(v)
	case ssaop.OpAMD64VPSHUFD256:
		return rewriteValue_OpAMD64VPSHUFD256(v)
	case ssaop.OpAMD64VPSHUFD512:
		return rewriteValue_OpAMD64VPSHUFD512(v)
	case ssaop.OpAMD64VPSHUFDMasked128:
		return rewriteValue_OpAMD64VPSHUFDMasked128(v)
	case ssaop.OpAMD64VPSHUFDMasked256:
		return rewriteValue_OpAMD64VPSHUFDMasked256(v)
	case ssaop.OpAMD64VPSHUFDMasked512:
		return rewriteValue_OpAMD64VPSHUFDMasked512(v)
	case ssaop.OpAMD64VPSHUFHW128:
		return rewriteValue_OpAMD64VPSHUFHW128(v)
	case ssaop.OpAMD64VPSHUFHW256:
		return rewriteValue_OpAMD64VPSHUFHW256(v)
	case ssaop.OpAMD64VPSHUFHWMasked128:
		return rewriteValue_OpAMD64VPSHUFHWMasked128(v)
	case ssaop.OpAMD64VPSHUFHWMasked256:
		return rewriteValue_OpAMD64VPSHUFHWMasked256(v)
	case ssaop.OpAMD64VPSHUFLW128:
		return rewriteValue_OpAMD64VPSHUFLW128(v)
	case ssaop.OpAMD64VPSHUFLW256:
		return rewriteValue_OpAMD64VPSHUFLW256(v)
	case ssaop.OpAMD64VPSHUFLWMasked128:
		return rewriteValue_OpAMD64VPSHUFLWMasked128(v)
	case ssaop.OpAMD64VPSHUFLWMasked256:
		return rewriteValue_OpAMD64VPSHUFLWMasked256(v)
	case ssaop.OpAMD64VPSIGNB128:
		return rewriteValue_OpAMD64VPSIGNB128(v)
	case ssaop.OpAMD64VPSIGNB256:
		return rewriteValue_OpAMD64VPSIGNB256(v)
	case ssaop.OpAMD64VPSIGND128:
		return rewriteValue_OpAMD64VPSIGND128(v)
	case ssaop.OpAMD64VPSIGND256:
		return rewriteValue_OpAMD64VPSIGND256(v)
	case ssaop.OpAMD64VPSIGNW128:
		return rewriteValue_OpAMD64VPSIGNW128(v)
	case ssaop.OpAMD64VPSIGNW256:
		return rewriteValue_OpAMD64VPSIGNW256(v)
	case ssaop.OpAMD64VPSLLD128:
		return rewriteValue_OpAMD64VPSLLD128(v)
	case ssaop.OpAMD64VPSLLD128const:
		return rewriteValue_OpAMD64VPSLLD128const(v)
	case ssaop.OpAMD64VPSLLD256:
		return rewriteValue_OpAMD64VPSLLD256(v)
	case ssaop.OpAMD64VPSLLD256const:
		return rewriteValue_OpAMD64VPSLLD256const(v)
	case ssaop.OpAMD64VPSLLD512:
		return rewriteValue_OpAMD64VPSLLD512(v)
	case ssaop.OpAMD64VPSLLD512const:
		return rewriteValue_OpAMD64VPSLLD512const(v)
	case ssaop.OpAMD64VPSLLDMasked128:
		return rewriteValue_OpAMD64VPSLLDMasked128(v)
	case ssaop.OpAMD64VPSLLDMasked128const:
		return rewriteValue_OpAMD64VPSLLDMasked128const(v)
	case ssaop.OpAMD64VPSLLDMasked256:
		return rewriteValue_OpAMD64VPSLLDMasked256(v)
	case ssaop.OpAMD64VPSLLDMasked256const:
		return rewriteValue_OpAMD64VPSLLDMasked256const(v)
	case ssaop.OpAMD64VPSLLDMasked512:
		return rewriteValue_OpAMD64VPSLLDMasked512(v)
	case ssaop.OpAMD64VPSLLDMasked512const:
		return rewriteValue_OpAMD64VPSLLDMasked512const(v)
	case ssaop.OpAMD64VPSLLQ128:
		return rewriteValue_OpAMD64VPSLLQ128(v)
	case ssaop.OpAMD64VPSLLQ128const:
		return rewriteValue_OpAMD64VPSLLQ128const(v)
	case ssaop.OpAMD64VPSLLQ256:
		return rewriteValue_OpAMD64VPSLLQ256(v)
	case ssaop.OpAMD64VPSLLQ256const:
		return rewriteValue_OpAMD64VPSLLQ256const(v)
	case ssaop.OpAMD64VPSLLQ512:
		return rewriteValue_OpAMD64VPSLLQ512(v)
	case ssaop.OpAMD64VPSLLQ512const:
		return rewriteValue_OpAMD64VPSLLQ512const(v)
	case ssaop.OpAMD64VPSLLQMasked128:
		return rewriteValue_OpAMD64VPSLLQMasked128(v)
	case ssaop.OpAMD64VPSLLQMasked128const:
		return rewriteValue_OpAMD64VPSLLQMasked128const(v)
	case ssaop.OpAMD64VPSLLQMasked256:
		return rewriteValue_OpAMD64VPSLLQMasked256(v)
	case ssaop.OpAMD64VPSLLQMasked256const:
		return rewriteValue_OpAMD64VPSLLQMasked256const(v)
	case ssaop.OpAMD64VPSLLQMasked512:
		return rewriteValue_OpAMD64VPSLLQMasked512(v)
	case ssaop.OpAMD64VPSLLQMasked512const:
		return rewriteValue_OpAMD64VPSLLQMasked512const(v)
	case ssaop.OpAMD64VPSLLVD128:
		return rewriteValue_OpAMD64VPSLLVD128(v)
	case ssaop.OpAMD64VPSLLVD256:
		return rewriteValue_OpAMD64VPSLLVD256(v)
	case ssaop.OpAMD64VPSLLVD512:
		return rewriteValue_OpAMD64VPSLLVD512(v)
	case ssaop.OpAMD64VPSLLVDMasked128:
		return rewriteValue_OpAMD64VPSLLVDMasked128(v)
	case ssaop.OpAMD64VPSLLVDMasked256:
		return rewriteValue_OpAMD64VPSLLVDMasked256(v)
	case ssaop.OpAMD64VPSLLVDMasked512:
		return rewriteValue_OpAMD64VPSLLVDMasked512(v)
	case ssaop.OpAMD64VPSLLVQ128:
		return rewriteValue_OpAMD64VPSLLVQ128(v)
	case ssaop.OpAMD64VPSLLVQ256:
		return rewriteValue_OpAMD64VPSLLVQ256(v)
	case ssaop.OpAMD64VPSLLVQ512:
		return rewriteValue_OpAMD64VPSLLVQ512(v)
	case ssaop.OpAMD64VPSLLVQMasked128:
		return rewriteValue_OpAMD64VPSLLVQMasked128(v)
	case ssaop.OpAMD64VPSLLVQMasked256:
		return rewriteValue_OpAMD64VPSLLVQMasked256(v)
	case ssaop.OpAMD64VPSLLVQMasked512:
		return rewriteValue_OpAMD64VPSLLVQMasked512(v)
	case ssaop.OpAMD64VPSLLVW128:
		return rewriteValue_OpAMD64VPSLLVW128(v)
	case ssaop.OpAMD64VPSLLVW256:
		return rewriteValue_OpAMD64VPSLLVW256(v)
	case ssaop.OpAMD64VPSLLVWMasked128:
		return rewriteValue_OpAMD64VPSLLVWMasked128(v)
	case ssaop.OpAMD64VPSLLVWMasked256:
		return rewriteValue_OpAMD64VPSLLVWMasked256(v)
	case ssaop.OpAMD64VPSLLW128:
		return rewriteValue_OpAMD64VPSLLW128(v)
	case ssaop.OpAMD64VPSLLW128const:
		return rewriteValue_OpAMD64VPSLLW128const(v)
	case ssaop.OpAMD64VPSLLW256:
		return rewriteValue_OpAMD64VPSLLW256(v)
	case ssaop.OpAMD64VPSLLW256const:
		return rewriteValue_OpAMD64VPSLLW256const(v)
	case ssaop.OpAMD64VPSLLW512:
		return rewriteValue_OpAMD64VPSLLW512(v)
	case ssaop.OpAMD64VPSLLW512const:
		return rewriteValue_OpAMD64VPSLLW512const(v)
	case ssaop.OpAMD64VPSLLWMasked128:
		return rewriteValue_OpAMD64VPSLLWMasked128(v)
	case ssaop.OpAMD64VPSLLWMasked128const:
		return rewriteValue_OpAMD64VPSLLWMasked128const(v)
	case ssaop.OpAMD64VPSLLWMasked256:
		return rewriteValue_OpAMD64VPSLLWMasked256(v)
	case ssaop.OpAMD64VPSLLWMasked256const:
		return rewriteValue_OpAMD64VPSLLWMasked256const(v)
	case ssaop.OpAMD64VPSLLWMasked512:
		return rewriteValue_OpAMD64VPSLLWMasked512(v)
	case ssaop.OpAMD64VPSLLWMasked512const:
		return rewriteValue_OpAMD64VPSLLWMasked512const(v)
	case ssaop.OpAMD64VPSRAD128:
		return rewriteValue_OpAMD64VPSRAD128(v)
	case ssaop.OpAMD64VPSRAD128const:
		return rewriteValue_OpAMD64VPSRAD128const(v)
	case ssaop.OpAMD64VPSRAD256:
		return rewriteValue_OpAMD64VPSRAD256(v)
	case ssaop.OpAMD64VPSRAD256const:
		return rewriteValue_OpAMD64VPSRAD256const(v)
	case ssaop.OpAMD64VPSRAD512:
		return rewriteValue_OpAMD64VPSRAD512(v)
	case ssaop.OpAMD64VPSRAD512const:
		return rewriteValue_OpAMD64VPSRAD512const(v)
	case ssaop.OpAMD64VPSRADMasked128:
		return rewriteValue_OpAMD64VPSRADMasked128(v)
	case ssaop.OpAMD64VPSRADMasked128const:
		return rewriteValue_OpAMD64VPSRADMasked128const(v)
	case ssaop.OpAMD64VPSRADMasked256:
		return rewriteValue_OpAMD64VPSRADMasked256(v)
	case ssaop.OpAMD64VPSRADMasked256const:
		return rewriteValue_OpAMD64VPSRADMasked256const(v)
	case ssaop.OpAMD64VPSRADMasked512:
		return rewriteValue_OpAMD64VPSRADMasked512(v)
	case ssaop.OpAMD64VPSRADMasked512const:
		return rewriteValue_OpAMD64VPSRADMasked512const(v)
	case ssaop.OpAMD64VPSRAQ128:
		return rewriteValue_OpAMD64VPSRAQ128(v)
	case ssaop.OpAMD64VPSRAQ128const:
		return rewriteValue_OpAMD64VPSRAQ128const(v)
	case ssaop.OpAMD64VPSRAQ256:
		return rewriteValue_OpAMD64VPSRAQ256(v)
	case ssaop.OpAMD64VPSRAQ256const:
		return rewriteValue_OpAMD64VPSRAQ256const(v)
	case ssaop.OpAMD64VPSRAQ512:
		return rewriteValue_OpAMD64VPSRAQ512(v)
	case ssaop.OpAMD64VPSRAQ512const:
		return rewriteValue_OpAMD64VPSRAQ512const(v)
	case ssaop.OpAMD64VPSRAQMasked128:
		return rewriteValue_OpAMD64VPSRAQMasked128(v)
	case ssaop.OpAMD64VPSRAQMasked128const:
		return rewriteValue_OpAMD64VPSRAQMasked128const(v)
	case ssaop.OpAMD64VPSRAQMasked256:
		return rewriteValue_OpAMD64VPSRAQMasked256(v)
	case ssaop.OpAMD64VPSRAQMasked256const:
		return rewriteValue_OpAMD64VPSRAQMasked256const(v)
	case ssaop.OpAMD64VPSRAQMasked512:
		return rewriteValue_OpAMD64VPSRAQMasked512(v)
	case ssaop.OpAMD64VPSRAQMasked512const:
		return rewriteValue_OpAMD64VPSRAQMasked512const(v)
	case ssaop.OpAMD64VPSRAVD128:
		return rewriteValue_OpAMD64VPSRAVD128(v)
	case ssaop.OpAMD64VPSRAVD256:
		return rewriteValue_OpAMD64VPSRAVD256(v)
	case ssaop.OpAMD64VPSRAVD512:
		return rewriteValue_OpAMD64VPSRAVD512(v)
	case ssaop.OpAMD64VPSRAVDMasked128:
		return rewriteValue_OpAMD64VPSRAVDMasked128(v)
	case ssaop.OpAMD64VPSRAVDMasked256:
		return rewriteValue_OpAMD64VPSRAVDMasked256(v)
	case ssaop.OpAMD64VPSRAVDMasked512:
		return rewriteValue_OpAMD64VPSRAVDMasked512(v)
	case ssaop.OpAMD64VPSRAVQ128:
		return rewriteValue_OpAMD64VPSRAVQ128(v)
	case ssaop.OpAMD64VPSRAVQ256:
		return rewriteValue_OpAMD64VPSRAVQ256(v)
	case ssaop.OpAMD64VPSRAVQ512:
		return rewriteValue_OpAMD64VPSRAVQ512(v)
	case ssaop.OpAMD64VPSRAVQMasked128:
		return rewriteValue_OpAMD64VPSRAVQMasked128(v)
	case ssaop.OpAMD64VPSRAVQMasked256:
		return rewriteValue_OpAMD64VPSRAVQMasked256(v)
	case ssaop.OpAMD64VPSRAVQMasked512:
		return rewriteValue_OpAMD64VPSRAVQMasked512(v)
	case ssaop.OpAMD64VPSRAVW128:
		return rewriteValue_OpAMD64VPSRAVW128(v)
	case ssaop.OpAMD64VPSRAVW256:
		return rewriteValue_OpAMD64VPSRAVW256(v)
	case ssaop.OpAMD64VPSRAVWMasked128:
		return rewriteValue_OpAMD64VPSRAVWMasked128(v)
	case ssaop.OpAMD64VPSRAVWMasked256:
		return rewriteValue_OpAMD64VPSRAVWMasked256(v)
	case ssaop.OpAMD64VPSRAW128:
		return rewriteValue_OpAMD64VPSRAW128(v)
	case ssaop.OpAMD64VPSRAW128const:
		return rewriteValue_OpAMD64VPSRAW128const(v)
	case ssaop.OpAMD64VPSRAW256:
		return rewriteValue_OpAMD64VPSRAW256(v)
	case ssaop.OpAMD64VPSRAW256const:
		return rewriteValue_OpAMD64VPSRAW256const(v)
	case ssaop.OpAMD64VPSRAW512:
		return rewriteValue_OpAMD64VPSRAW512(v)
	case ssaop.OpAMD64VPSRAW512const:
		return rewriteValue_OpAMD64VPSRAW512const(v)
	case ssaop.OpAMD64VPSRAWMasked128:
		return rewriteValue_OpAMD64VPSRAWMasked128(v)
	case ssaop.OpAMD64VPSRAWMasked128const:
		return rewriteValue_OpAMD64VPSRAWMasked128const(v)
	case ssaop.OpAMD64VPSRAWMasked256:
		return rewriteValue_OpAMD64VPSRAWMasked256(v)
	case ssaop.OpAMD64VPSRAWMasked256const:
		return rewriteValue_OpAMD64VPSRAWMasked256const(v)
	case ssaop.OpAMD64VPSRAWMasked512:
		return rewriteValue_OpAMD64VPSRAWMasked512(v)
	case ssaop.OpAMD64VPSRAWMasked512const:
		return rewriteValue_OpAMD64VPSRAWMasked512const(v)
	case ssaop.OpAMD64VPSRLD128:
		return rewriteValue_OpAMD64VPSRLD128(v)
	case ssaop.OpAMD64VPSRLD128const:
		return rewriteValue_OpAMD64VPSRLD128const(v)
	case ssaop.OpAMD64VPSRLD256:
		return rewriteValue_OpAMD64VPSRLD256(v)
	case ssaop.OpAMD64VPSRLD256const:
		return rewriteValue_OpAMD64VPSRLD256const(v)
	case ssaop.OpAMD64VPSRLD512:
		return rewriteValue_OpAMD64VPSRLD512(v)
	case ssaop.OpAMD64VPSRLD512const:
		return rewriteValue_OpAMD64VPSRLD512const(v)
	case ssaop.OpAMD64VPSRLDMasked128:
		return rewriteValue_OpAMD64VPSRLDMasked128(v)
	case ssaop.OpAMD64VPSRLDMasked128const:
		return rewriteValue_OpAMD64VPSRLDMasked128const(v)
	case ssaop.OpAMD64VPSRLDMasked256:
		return rewriteValue_OpAMD64VPSRLDMasked256(v)
	case ssaop.OpAMD64VPSRLDMasked256const:
		return rewriteValue_OpAMD64VPSRLDMasked256const(v)
	case ssaop.OpAMD64VPSRLDMasked512:
		return rewriteValue_OpAMD64VPSRLDMasked512(v)
	case ssaop.OpAMD64VPSRLDMasked512const:
		return rewriteValue_OpAMD64VPSRLDMasked512const(v)
	case ssaop.OpAMD64VPSRLQ128:
		return rewriteValue_OpAMD64VPSRLQ128(v)
	case ssaop.OpAMD64VPSRLQ128const:
		return rewriteValue_OpAMD64VPSRLQ128const(v)
	case ssaop.OpAMD64VPSRLQ256:
		return rewriteValue_OpAMD64VPSRLQ256(v)
	case ssaop.OpAMD64VPSRLQ256const:
		return rewriteValue_OpAMD64VPSRLQ256const(v)
	case ssaop.OpAMD64VPSRLQ512:
		return rewriteValue_OpAMD64VPSRLQ512(v)
	case ssaop.OpAMD64VPSRLQ512const:
		return rewriteValue_OpAMD64VPSRLQ512const(v)
	case ssaop.OpAMD64VPSRLQMasked128:
		return rewriteValue_OpAMD64VPSRLQMasked128(v)
	case ssaop.OpAMD64VPSRLQMasked128const:
		return rewriteValue_OpAMD64VPSRLQMasked128const(v)
	case ssaop.OpAMD64VPSRLQMasked256:
		return rewriteValue_OpAMD64VPSRLQMasked256(v)
	case ssaop.OpAMD64VPSRLQMasked256const:
		return rewriteValue_OpAMD64VPSRLQMasked256const(v)
	case ssaop.OpAMD64VPSRLQMasked512:
		return rewriteValue_OpAMD64VPSRLQMasked512(v)
	case ssaop.OpAMD64VPSRLQMasked512const:
		return rewriteValue_OpAMD64VPSRLQMasked512const(v)
	case ssaop.OpAMD64VPSRLVD128:
		return rewriteValue_OpAMD64VPSRLVD128(v)
	case ssaop.OpAMD64VPSRLVD256:
		return rewriteValue_OpAMD64VPSRLVD256(v)
	case ssaop.OpAMD64VPSRLVD512:
		return rewriteValue_OpAMD64VPSRLVD512(v)
	case ssaop.OpAMD64VPSRLVDMasked128:
		return rewriteValue_OpAMD64VPSRLVDMasked128(v)
	case ssaop.OpAMD64VPSRLVDMasked256:
		return rewriteValue_OpAMD64VPSRLVDMasked256(v)
	case ssaop.OpAMD64VPSRLVDMasked512:
		return rewriteValue_OpAMD64VPSRLVDMasked512(v)
	case ssaop.OpAMD64VPSRLVQ128:
		return rewriteValue_OpAMD64VPSRLVQ128(v)
	case ssaop.OpAMD64VPSRLVQ256:
		return rewriteValue_OpAMD64VPSRLVQ256(v)
	case ssaop.OpAMD64VPSRLVQ512:
		return rewriteValue_OpAMD64VPSRLVQ512(v)
	case ssaop.OpAMD64VPSRLVQMasked128:
		return rewriteValue_OpAMD64VPSRLVQMasked128(v)
	case ssaop.OpAMD64VPSRLVQMasked256:
		return rewriteValue_OpAMD64VPSRLVQMasked256(v)
	case ssaop.OpAMD64VPSRLVQMasked512:
		return rewriteValue_OpAMD64VPSRLVQMasked512(v)
	case ssaop.OpAMD64VPSRLVW128:
		return rewriteValue_OpAMD64VPSRLVW128(v)
	case ssaop.OpAMD64VPSRLVW256:
		return rewriteValue_OpAMD64VPSRLVW256(v)
	case ssaop.OpAMD64VPSRLVWMasked128:
		return rewriteValue_OpAMD64VPSRLVWMasked128(v)
	case ssaop.OpAMD64VPSRLVWMasked256:
		return rewriteValue_OpAMD64VPSRLVWMasked256(v)
	case ssaop.OpAMD64VPSRLW128:
		return rewriteValue_OpAMD64VPSRLW128(v)
	case ssaop.OpAMD64VPSRLW128const:
		return rewriteValue_OpAMD64VPSRLW128const(v)
	case ssaop.OpAMD64VPSRLW256:
		return rewriteValue_OpAMD64VPSRLW256(v)
	case ssaop.OpAMD64VPSRLW256const:
		return rewriteValue_OpAMD64VPSRLW256const(v)
	case ssaop.OpAMD64VPSRLW512:
		return rewriteValue_OpAMD64VPSRLW512(v)
	case ssaop.OpAMD64VPSRLW512const:
		return rewriteValue_OpAMD64VPSRLW512const(v)
	case ssaop.OpAMD64VPSRLWMasked128:
		return rewriteValue_OpAMD64VPSRLWMasked128(v)
	case ssaop.OpAMD64VPSRLWMasked128const:
		return rewriteValue_OpAMD64VPSRLWMasked128const(v)
	case ssaop.OpAMD64VPSRLWMasked256:
		return rewriteValue_OpAMD64VPSRLWMasked256(v)
	case ssaop.OpAMD64VPSRLWMasked256const:
		return rewriteValue_OpAMD64VPSRLWMasked256const(v)
	case ssaop.OpAMD64VPSRLWMasked512:
		return rewriteValue_OpAMD64VPSRLWMasked512(v)
	case ssaop.OpAMD64VPSRLWMasked512const:
		return rewriteValue_OpAMD64VPSRLWMasked512const(v)
	case ssaop.OpAMD64VPSUBB128:
		return rewriteValue_OpAMD64VPSUBB128(v)
	case ssaop.OpAMD64VPSUBB256:
		return rewriteValue_OpAMD64VPSUBB256(v)
	case ssaop.OpAMD64VPSUBBMasked128:
		return rewriteValue_OpAMD64VPSUBBMasked128(v)
	case ssaop.OpAMD64VPSUBBMasked256:
		return rewriteValue_OpAMD64VPSUBBMasked256(v)
	case ssaop.OpAMD64VPSUBD128:
		return rewriteValue_OpAMD64VPSUBD128(v)
	case ssaop.OpAMD64VPSUBD256:
		return rewriteValue_OpAMD64VPSUBD256(v)
	case ssaop.OpAMD64VPSUBD512:
		return rewriteValue_OpAMD64VPSUBD512(v)
	case ssaop.OpAMD64VPSUBDMasked128:
		return rewriteValue_OpAMD64VPSUBDMasked128(v)
	case ssaop.OpAMD64VPSUBDMasked256:
		return rewriteValue_OpAMD64VPSUBDMasked256(v)
	case ssaop.OpAMD64VPSUBDMasked512:
		return rewriteValue_OpAMD64VPSUBDMasked512(v)
	case ssaop.OpAMD64VPSUBQ128:
		return rewriteValue_OpAMD64VPSUBQ128(v)
	case ssaop.OpAMD64VPSUBQ256:
		return rewriteValue_OpAMD64VPSUBQ256(v)
	case ssaop.OpAMD64VPSUBQ512:
		return rewriteValue_OpAMD64VPSUBQ512(v)
	case ssaop.OpAMD64VPSUBQMasked128:
		return rewriteValue_OpAMD64VPSUBQMasked128(v)
	case ssaop.OpAMD64VPSUBQMasked256:
		return rewriteValue_OpAMD64VPSUBQMasked256(v)
	case ssaop.OpAMD64VPSUBQMasked512:
		return rewriteValue_OpAMD64VPSUBQMasked512(v)
	case ssaop.OpAMD64VPSUBSB128:
		return rewriteValue_OpAMD64VPSUBSB128(v)
	case ssaop.OpAMD64VPSUBSB256:
		return rewriteValue_OpAMD64VPSUBSB256(v)
	case ssaop.OpAMD64VPSUBSBMasked128:
		return rewriteValue_OpAMD64VPSUBSBMasked128(v)
	case ssaop.OpAMD64VPSUBSBMasked256:
		return rewriteValue_OpAMD64VPSUBSBMasked256(v)
	case ssaop.OpAMD64VPSUBSW128:
		return rewriteValue_OpAMD64VPSUBSW128(v)
	case ssaop.OpAMD64VPSUBSW256:
		return rewriteValue_OpAMD64VPSUBSW256(v)
	case ssaop.OpAMD64VPSUBSWMasked128:
		return rewriteValue_OpAMD64VPSUBSWMasked128(v)
	case ssaop.OpAMD64VPSUBSWMasked256:
		return rewriteValue_OpAMD64VPSUBSWMasked256(v)
	case ssaop.OpAMD64VPSUBUSB128:
		return rewriteValue_OpAMD64VPSUBUSB128(v)
	case ssaop.OpAMD64VPSUBUSB256:
		return rewriteValue_OpAMD64VPSUBUSB256(v)
	case ssaop.OpAMD64VPSUBUSBMasked128:
		return rewriteValue_OpAMD64VPSUBUSBMasked128(v)
	case ssaop.OpAMD64VPSUBUSBMasked256:
		return rewriteValue_OpAMD64VPSUBUSBMasked256(v)
	case ssaop.OpAMD64VPSUBUSW128:
		return rewriteValue_OpAMD64VPSUBUSW128(v)
	case ssaop.OpAMD64VPSUBUSW256:
		return rewriteValue_OpAMD64VPSUBUSW256(v)
	case ssaop.OpAMD64VPSUBUSWMasked128:
		return rewriteValue_OpAMD64VPSUBUSWMasked128(v)
	case ssaop.OpAMD64VPSUBUSWMasked256:
		return rewriteValue_OpAMD64VPSUBUSWMasked256(v)
	case ssaop.OpAMD64VPSUBW128:
		return rewriteValue_OpAMD64VPSUBW128(v)
	case ssaop.OpAMD64VPSUBW256:
		return rewriteValue_OpAMD64VPSUBW256(v)
	case ssaop.OpAMD64VPSUBWMasked128:
		return rewriteValue_OpAMD64VPSUBWMasked128(v)
	case ssaop.OpAMD64VPSUBWMasked256:
		return rewriteValue_OpAMD64VPSUBWMasked256(v)
	case ssaop.OpAMD64VPTERNLOGD128:
		return rewriteValue_OpAMD64VPTERNLOGD128(v)
	case ssaop.OpAMD64VPTERNLOGD256:
		return rewriteValue_OpAMD64VPTERNLOGD256(v)
	case ssaop.OpAMD64VPTERNLOGD512:
		return rewriteValue_OpAMD64VPTERNLOGD512(v)
	case ssaop.OpAMD64VPTERNLOGQ128:
		return rewriteValue_OpAMD64VPTERNLOGQ128(v)
	case ssaop.OpAMD64VPTERNLOGQ256:
		return rewriteValue_OpAMD64VPTERNLOGQ256(v)
	case ssaop.OpAMD64VPTERNLOGQ512:
		return rewriteValue_OpAMD64VPTERNLOGQ512(v)
	case ssaop.OpAMD64VPUNPCKHDQ128:
		return rewriteValue_OpAMD64VPUNPCKHDQ128(v)
	case ssaop.OpAMD64VPUNPCKHDQ256:
		return rewriteValue_OpAMD64VPUNPCKHDQ256(v)
	case ssaop.OpAMD64VPUNPCKHDQ512:
		return rewriteValue_OpAMD64VPUNPCKHDQ512(v)
	case ssaop.OpAMD64VPUNPCKHQDQ128:
		return rewriteValue_OpAMD64VPUNPCKHQDQ128(v)
	case ssaop.OpAMD64VPUNPCKHQDQ256:
		return rewriteValue_OpAMD64VPUNPCKHQDQ256(v)
	case ssaop.OpAMD64VPUNPCKHQDQ512:
		return rewriteValue_OpAMD64VPUNPCKHQDQ512(v)
	case ssaop.OpAMD64VPUNPCKHWD128:
		return rewriteValue_OpAMD64VPUNPCKHWD128(v)
	case ssaop.OpAMD64VPUNPCKHWD256:
		return rewriteValue_OpAMD64VPUNPCKHWD256(v)
	case ssaop.OpAMD64VPUNPCKLDQ128:
		return rewriteValue_OpAMD64VPUNPCKLDQ128(v)
	case ssaop.OpAMD64VPUNPCKLDQ256:
		return rewriteValue_OpAMD64VPUNPCKLDQ256(v)
	case ssaop.OpAMD64VPUNPCKLDQ512:
		return rewriteValue_OpAMD64VPUNPCKLDQ512(v)
	case ssaop.OpAMD64VPUNPCKLQDQ128:
		return rewriteValue_OpAMD64VPUNPCKLQDQ128(v)
	case ssaop.OpAMD64VPUNPCKLQDQ256:
		return rewriteValue_OpAMD64VPUNPCKLQDQ256(v)
	case ssaop.OpAMD64VPUNPCKLQDQ512:
		return rewriteValue_OpAMD64VPUNPCKLQDQ512(v)
	case ssaop.OpAMD64VPUNPCKLWD128:
		return rewriteValue_OpAMD64VPUNPCKLWD128(v)
	case ssaop.OpAMD64VPUNPCKLWD256:
		return rewriteValue_OpAMD64VPUNPCKLWD256(v)
	case ssaop.OpAMD64VPXOR128:
		return rewriteValue_OpAMD64VPXOR128(v)
	case ssaop.OpAMD64VPXOR256:
		return rewriteValue_OpAMD64VPXOR256(v)
	case ssaop.OpAMD64VPXORD512:
		return rewriteValue_OpAMD64VPXORD512(v)
	case ssaop.OpAMD64VPXORDMasked128:
		return rewriteValue_OpAMD64VPXORDMasked128(v)
	case ssaop.OpAMD64VPXORDMasked256:
		return rewriteValue_OpAMD64VPXORDMasked256(v)
	case ssaop.OpAMD64VPXORDMasked512:
		return rewriteValue_OpAMD64VPXORDMasked512(v)
	case ssaop.OpAMD64VPXORQ512:
		return rewriteValue_OpAMD64VPXORQ512(v)
	case ssaop.OpAMD64VPXORQMasked128:
		return rewriteValue_OpAMD64VPXORQMasked128(v)
	case ssaop.OpAMD64VPXORQMasked256:
		return rewriteValue_OpAMD64VPXORQMasked256(v)
	case ssaop.OpAMD64VPXORQMasked512:
		return rewriteValue_OpAMD64VPXORQMasked512(v)
	case ssaop.OpAMD64VRCP14PD128:
		return rewriteValue_OpAMD64VRCP14PD128(v)
	case ssaop.OpAMD64VRCP14PD256:
		return rewriteValue_OpAMD64VRCP14PD256(v)
	case ssaop.OpAMD64VRCP14PD512:
		return rewriteValue_OpAMD64VRCP14PD512(v)
	case ssaop.OpAMD64VRCP14PDMasked128:
		return rewriteValue_OpAMD64VRCP14PDMasked128(v)
	case ssaop.OpAMD64VRCP14PDMasked256:
		return rewriteValue_OpAMD64VRCP14PDMasked256(v)
	case ssaop.OpAMD64VRCP14PDMasked512:
		return rewriteValue_OpAMD64VRCP14PDMasked512(v)
	case ssaop.OpAMD64VRCP14PS512:
		return rewriteValue_OpAMD64VRCP14PS512(v)
	case ssaop.OpAMD64VRCP14PSMasked128:
		return rewriteValue_OpAMD64VRCP14PSMasked128(v)
	case ssaop.OpAMD64VRCP14PSMasked256:
		return rewriteValue_OpAMD64VRCP14PSMasked256(v)
	case ssaop.OpAMD64VRCP14PSMasked512:
		return rewriteValue_OpAMD64VRCP14PSMasked512(v)
	case ssaop.OpAMD64VRCPPS128:
		return rewriteValue_OpAMD64VRCPPS128(v)
	case ssaop.OpAMD64VRCPPS256:
		return rewriteValue_OpAMD64VRCPPS256(v)
	case ssaop.OpAMD64VREDUCEPD128:
		return rewriteValue_OpAMD64VREDUCEPD128(v)
	case ssaop.OpAMD64VREDUCEPD256:
		return rewriteValue_OpAMD64VREDUCEPD256(v)
	case ssaop.OpAMD64VREDUCEPD512:
		return rewriteValue_OpAMD64VREDUCEPD512(v)
	case ssaop.OpAMD64VREDUCEPDMasked128:
		return rewriteValue_OpAMD64VREDUCEPDMasked128(v)
	case ssaop.OpAMD64VREDUCEPDMasked256:
		return rewriteValue_OpAMD64VREDUCEPDMasked256(v)
	case ssaop.OpAMD64VREDUCEPDMasked512:
		return rewriteValue_OpAMD64VREDUCEPDMasked512(v)
	case ssaop.OpAMD64VREDUCEPS128:
		return rewriteValue_OpAMD64VREDUCEPS128(v)
	case ssaop.OpAMD64VREDUCEPS256:
		return rewriteValue_OpAMD64VREDUCEPS256(v)
	case ssaop.OpAMD64VREDUCEPS512:
		return rewriteValue_OpAMD64VREDUCEPS512(v)
	case ssaop.OpAMD64VREDUCEPSMasked128:
		return rewriteValue_OpAMD64VREDUCEPSMasked128(v)
	case ssaop.OpAMD64VREDUCEPSMasked256:
		return rewriteValue_OpAMD64VREDUCEPSMasked256(v)
	case ssaop.OpAMD64VREDUCEPSMasked512:
		return rewriteValue_OpAMD64VREDUCEPSMasked512(v)
	case ssaop.OpAMD64VRNDSCALEPD128:
		return rewriteValue_OpAMD64VRNDSCALEPD128(v)
	case ssaop.OpAMD64VRNDSCALEPD256:
		return rewriteValue_OpAMD64VRNDSCALEPD256(v)
	case ssaop.OpAMD64VRNDSCALEPD512:
		return rewriteValue_OpAMD64VRNDSCALEPD512(v)
	case ssaop.OpAMD64VRNDSCALEPDMasked128:
		return rewriteValue_OpAMD64VRNDSCALEPDMasked128(v)
	case ssaop.OpAMD64VRNDSCALEPDMasked256:
		return rewriteValue_OpAMD64VRNDSCALEPDMasked256(v)
	case ssaop.OpAMD64VRNDSCALEPDMasked512:
		return rewriteValue_OpAMD64VRNDSCALEPDMasked512(v)
	case ssaop.OpAMD64VRNDSCALEPS128:
		return rewriteValue_OpAMD64VRNDSCALEPS128(v)
	case ssaop.OpAMD64VRNDSCALEPS256:
		return rewriteValue_OpAMD64VRNDSCALEPS256(v)
	case ssaop.OpAMD64VRNDSCALEPS512:
		return rewriteValue_OpAMD64VRNDSCALEPS512(v)
	case ssaop.OpAMD64VRNDSCALEPSMasked128:
		return rewriteValue_OpAMD64VRNDSCALEPSMasked128(v)
	case ssaop.OpAMD64VRNDSCALEPSMasked256:
		return rewriteValue_OpAMD64VRNDSCALEPSMasked256(v)
	case ssaop.OpAMD64VRNDSCALEPSMasked512:
		return rewriteValue_OpAMD64VRNDSCALEPSMasked512(v)
	case ssaop.OpAMD64VROUNDPD128:
		return rewriteValue_OpAMD64VROUNDPD128(v)
	case ssaop.OpAMD64VROUNDPD256:
		return rewriteValue_OpAMD64VROUNDPD256(v)
	case ssaop.OpAMD64VROUNDPS128:
		return rewriteValue_OpAMD64VROUNDPS128(v)
	case ssaop.OpAMD64VROUNDPS256:
		return rewriteValue_OpAMD64VROUNDPS256(v)
	case ssaop.OpAMD64VRSQRT14PD128:
		return rewriteValue_OpAMD64VRSQRT14PD128(v)
	case ssaop.OpAMD64VRSQRT14PD256:
		return rewriteValue_OpAMD64VRSQRT14PD256(v)
	case ssaop.OpAMD64VRSQRT14PD512:
		return rewriteValue_OpAMD64VRSQRT14PD512(v)
	case ssaop.OpAMD64VRSQRT14PDMasked128:
		return rewriteValue_OpAMD64VRSQRT14PDMasked128(v)
	case ssaop.OpAMD64VRSQRT14PDMasked256:
		return rewriteValue_OpAMD64VRSQRT14PDMasked256(v)
	case ssaop.OpAMD64VRSQRT14PDMasked512:
		return rewriteValue_OpAMD64VRSQRT14PDMasked512(v)
	case ssaop.OpAMD64VRSQRT14PS512:
		return rewriteValue_OpAMD64VRSQRT14PS512(v)
	case ssaop.OpAMD64VRSQRT14PSMasked128:
		return rewriteValue_OpAMD64VRSQRT14PSMasked128(v)
	case ssaop.OpAMD64VRSQRT14PSMasked256:
		return rewriteValue_OpAMD64VRSQRT14PSMasked256(v)
	case ssaop.OpAMD64VRSQRT14PSMasked512:
		return rewriteValue_OpAMD64VRSQRT14PSMasked512(v)
	case ssaop.OpAMD64VRSQRTPS128:
		return rewriteValue_OpAMD64VRSQRTPS128(v)
	case ssaop.OpAMD64VRSQRTPS256:
		return rewriteValue_OpAMD64VRSQRTPS256(v)
	case ssaop.OpAMD64VSCALEFPD128:
		return rewriteValue_OpAMD64VSCALEFPD128(v)
	case ssaop.OpAMD64VSCALEFPD256:
		return rewriteValue_OpAMD64VSCALEFPD256(v)
	case ssaop.OpAMD64VSCALEFPD512:
		return rewriteValue_OpAMD64VSCALEFPD512(v)
	case ssaop.OpAMD64VSCALEFPDMasked128:
		return rewriteValue_OpAMD64VSCALEFPDMasked128(v)
	case ssaop.OpAMD64VSCALEFPDMasked256:
		return rewriteValue_OpAMD64VSCALEFPDMasked256(v)
	case ssaop.OpAMD64VSCALEFPDMasked512:
		return rewriteValue_OpAMD64VSCALEFPDMasked512(v)
	case ssaop.OpAMD64VSCALEFPS128:
		return rewriteValue_OpAMD64VSCALEFPS128(v)
	case ssaop.OpAMD64VSCALEFPS256:
		return rewriteValue_OpAMD64VSCALEFPS256(v)
	case ssaop.OpAMD64VSCALEFPS512:
		return rewriteValue_OpAMD64VSCALEFPS512(v)
	case ssaop.OpAMD64VSCALEFPSMasked128:
		return rewriteValue_OpAMD64VSCALEFPSMasked128(v)
	case ssaop.OpAMD64VSCALEFPSMasked256:
		return rewriteValue_OpAMD64VSCALEFPSMasked256(v)
	case ssaop.OpAMD64VSCALEFPSMasked512:
		return rewriteValue_OpAMD64VSCALEFPSMasked512(v)
	case ssaop.OpAMD64VSHUFPD128:
		return rewriteValue_OpAMD64VSHUFPD128(v)
	case ssaop.OpAMD64VSHUFPD256:
		return rewriteValue_OpAMD64VSHUFPD256(v)
	case ssaop.OpAMD64VSHUFPD512:
		return rewriteValue_OpAMD64VSHUFPD512(v)
	case ssaop.OpAMD64VSHUFPS128:
		return rewriteValue_OpAMD64VSHUFPS128(v)
	case ssaop.OpAMD64VSHUFPS256:
		return rewriteValue_OpAMD64VSHUFPS256(v)
	case ssaop.OpAMD64VSHUFPS512:
		return rewriteValue_OpAMD64VSHUFPS512(v)
	case ssaop.OpAMD64VSQRTPD128:
		return rewriteValue_OpAMD64VSQRTPD128(v)
	case ssaop.OpAMD64VSQRTPD256:
		return rewriteValue_OpAMD64VSQRTPD256(v)
	case ssaop.OpAMD64VSQRTPD512:
		return rewriteValue_OpAMD64VSQRTPD512(v)
	case ssaop.OpAMD64VSQRTPDMasked128:
		return rewriteValue_OpAMD64VSQRTPDMasked128(v)
	case ssaop.OpAMD64VSQRTPDMasked256:
		return rewriteValue_OpAMD64VSQRTPDMasked256(v)
	case ssaop.OpAMD64VSQRTPDMasked512:
		return rewriteValue_OpAMD64VSQRTPDMasked512(v)
	case ssaop.OpAMD64VSQRTPS128:
		return rewriteValue_OpAMD64VSQRTPS128(v)
	case ssaop.OpAMD64VSQRTPS256:
		return rewriteValue_OpAMD64VSQRTPS256(v)
	case ssaop.OpAMD64VSQRTPS512:
		return rewriteValue_OpAMD64VSQRTPS512(v)
	case ssaop.OpAMD64VSQRTPSMasked128:
		return rewriteValue_OpAMD64VSQRTPSMasked128(v)
	case ssaop.OpAMD64VSQRTPSMasked256:
		return rewriteValue_OpAMD64VSQRTPSMasked256(v)
	case ssaop.OpAMD64VSQRTPSMasked512:
		return rewriteValue_OpAMD64VSQRTPSMasked512(v)
	case ssaop.OpAMD64VSUBPD128:
		return rewriteValue_OpAMD64VSUBPD128(v)
	case ssaop.OpAMD64VSUBPD256:
		return rewriteValue_OpAMD64VSUBPD256(v)
	case ssaop.OpAMD64VSUBPD512:
		return rewriteValue_OpAMD64VSUBPD512(v)
	case ssaop.OpAMD64VSUBPDMasked128:
		return rewriteValue_OpAMD64VSUBPDMasked128(v)
	case ssaop.OpAMD64VSUBPDMasked256:
		return rewriteValue_OpAMD64VSUBPDMasked256(v)
	case ssaop.OpAMD64VSUBPDMasked512:
		return rewriteValue_OpAMD64VSUBPDMasked512(v)
	case ssaop.OpAMD64VSUBPS128:
		return rewriteValue_OpAMD64VSUBPS128(v)
	case ssaop.OpAMD64VSUBPS256:
		return rewriteValue_OpAMD64VSUBPS256(v)
	case ssaop.OpAMD64VSUBPS512:
		return rewriteValue_OpAMD64VSUBPS512(v)
	case ssaop.OpAMD64VSUBPSMasked128:
		return rewriteValue_OpAMD64VSUBPSMasked128(v)
	case ssaop.OpAMD64VSUBPSMasked256:
		return rewriteValue_OpAMD64VSUBPSMasked256(v)
	case ssaop.OpAMD64VSUBPSMasked512:
		return rewriteValue_OpAMD64VSUBPSMasked512(v)
	case ssaop.OpAMD64XADDLlock:
		return rewriteValue_OpAMD64XADDLlock(v)
	case ssaop.OpAMD64XADDQlock:
		return rewriteValue_OpAMD64XADDQlock(v)
	case ssaop.OpAMD64XCHGL:
		return rewriteValue_OpAMD64XCHGL(v)
	case ssaop.OpAMD64XCHGQ:
		return rewriteValue_OpAMD64XCHGQ(v)
	case ssaop.OpAMD64XORBconstmodify:
		return rewriteValue_OpAMD64XORBconstmodify(v)
	case ssaop.OpAMD64XORL:
		return rewriteValue_OpAMD64XORL(v)
	case ssaop.OpAMD64XORLconst:
		return rewriteValue_OpAMD64XORLconst(v)
	case ssaop.OpAMD64XORLconstmodify:
		return rewriteValue_OpAMD64XORLconstmodify(v)
	case ssaop.OpAMD64XORLload:
		return rewriteValue_OpAMD64XORLload(v)
	case ssaop.OpAMD64XORLmodify:
		return rewriteValue_OpAMD64XORLmodify(v)
	case ssaop.OpAMD64XORQ:
		return rewriteValue_OpAMD64XORQ(v)
	case ssaop.OpAMD64XORQconst:
		return rewriteValue_OpAMD64XORQconst(v)
	case ssaop.OpAMD64XORQconstmodify:
		return rewriteValue_OpAMD64XORQconstmodify(v)
	case ssaop.OpAMD64XORQload:
		return rewriteValue_OpAMD64XORQload(v)
	case ssaop.OpAMD64XORQmodify:
		return rewriteValue_OpAMD64XORQmodify(v)
	case ssaop.OpAMD64XORWconstmodify:
		return rewriteValue_OpAMD64XORWconstmodify(v)
	case ssaop.OpAbsInt16x16:
		v.Op = ssaop.OpAMD64VPABSW256
		return true
	case ssaop.OpAbsInt16x32:
		v.Op = ssaop.OpAMD64VPABSW512
		return true
	case ssaop.OpAbsInt16x8:
		v.Op = ssaop.OpAMD64VPABSW128
		return true
	case ssaop.OpAbsInt32x16:
		v.Op = ssaop.OpAMD64VPABSD512
		return true
	case ssaop.OpAbsInt32x4:
		v.Op = ssaop.OpAMD64VPABSD128
		return true
	case ssaop.OpAbsInt32x8:
		v.Op = ssaop.OpAMD64VPABSD256
		return true
	case ssaop.OpAbsInt64x2:
		v.Op = ssaop.OpAMD64VPABSQ128
		return true
	case ssaop.OpAbsInt64x4:
		v.Op = ssaop.OpAMD64VPABSQ256
		return true
	case ssaop.OpAbsInt64x8:
		v.Op = ssaop.OpAMD64VPABSQ512
		return true
	case ssaop.OpAbsInt8x16:
		v.Op = ssaop.OpAMD64VPABSB128
		return true
	case ssaop.OpAbsInt8x32:
		v.Op = ssaop.OpAMD64VPABSB256
		return true
	case ssaop.OpAbsInt8x64:
		v.Op = ssaop.OpAMD64VPABSB512
		return true
	case ssaop.OpAdd16:
		v.Op = ssaop.OpAMD64ADDL
		return true
	case ssaop.OpAdd32:
		v.Op = ssaop.OpAMD64ADDL
		return true
	case ssaop.OpAdd32F:
		v.Op = ssaop.OpAMD64ADDSS
		return true
	case ssaop.OpAdd64:
		v.Op = ssaop.OpAMD64ADDQ
		return true
	case ssaop.OpAdd64F:
		v.Op = ssaop.OpAMD64ADDSD
		return true
	case ssaop.OpAdd8:
		v.Op = ssaop.OpAMD64ADDL
		return true
	case ssaop.OpAddFloat32x16:
		v.Op = ssaop.OpAMD64VADDPS512
		return true
	case ssaop.OpAddFloat32x4:
		v.Op = ssaop.OpAMD64VADDPS128
		return true
	case ssaop.OpAddFloat32x8:
		v.Op = ssaop.OpAMD64VADDPS256
		return true
	case ssaop.OpAddFloat64x2:
		v.Op = ssaop.OpAMD64VADDPD128
		return true
	case ssaop.OpAddFloat64x4:
		v.Op = ssaop.OpAMD64VADDPD256
		return true
	case ssaop.OpAddFloat64x8:
		v.Op = ssaop.OpAMD64VADDPD512
		return true
	case ssaop.OpAddInt16x16:
		v.Op = ssaop.OpAMD64VPADDW256
		return true
	case ssaop.OpAddInt16x32:
		v.Op = ssaop.OpAMD64VPADDW512
		return true
	case ssaop.OpAddInt16x8:
		v.Op = ssaop.OpAMD64VPADDW128
		return true
	case ssaop.OpAddInt32x16:
		v.Op = ssaop.OpAMD64VPADDD512
		return true
	case ssaop.OpAddInt32x4:
		v.Op = ssaop.OpAMD64VPADDD128
		return true
	case ssaop.OpAddInt32x8:
		v.Op = ssaop.OpAMD64VPADDD256
		return true
	case ssaop.OpAddInt64x2:
		v.Op = ssaop.OpAMD64VPADDQ128
		return true
	case ssaop.OpAddInt64x4:
		v.Op = ssaop.OpAMD64VPADDQ256
		return true
	case ssaop.OpAddInt64x8:
		v.Op = ssaop.OpAMD64VPADDQ512
		return true
	case ssaop.OpAddInt8x16:
		v.Op = ssaop.OpAMD64VPADDB128
		return true
	case ssaop.OpAddInt8x32:
		v.Op = ssaop.OpAMD64VPADDB256
		return true
	case ssaop.OpAddInt8x64:
		v.Op = ssaop.OpAMD64VPADDB512
		return true
	case ssaop.OpAddOddSubEvenFloat32x4:
		v.Op = ssaop.OpAMD64VADDSUBPS128
		return true
	case ssaop.OpAddOddSubEvenFloat32x8:
		v.Op = ssaop.OpAMD64VADDSUBPS256
		return true
	case ssaop.OpAddOddSubEvenFloat64x2:
		v.Op = ssaop.OpAMD64VADDSUBPD128
		return true
	case ssaop.OpAddOddSubEvenFloat64x4:
		v.Op = ssaop.OpAMD64VADDSUBPD256
		return true
	case ssaop.OpAddPtr:
		v.Op = ssaop.OpAMD64ADDQ
		return true
	case ssaop.OpAddSaturatedInt16x16:
		v.Op = ssaop.OpAMD64VPADDSW256
		return true
	case ssaop.OpAddSaturatedInt16x32:
		v.Op = ssaop.OpAMD64VPADDSW512
		return true
	case ssaop.OpAddSaturatedInt16x8:
		v.Op = ssaop.OpAMD64VPADDSW128
		return true
	case ssaop.OpAddSaturatedInt8x16:
		v.Op = ssaop.OpAMD64VPADDSB128
		return true
	case ssaop.OpAddSaturatedInt8x32:
		v.Op = ssaop.OpAMD64VPADDSB256
		return true
	case ssaop.OpAddSaturatedInt8x64:
		v.Op = ssaop.OpAMD64VPADDSB512
		return true
	case ssaop.OpAddSaturatedUint16x16:
		v.Op = ssaop.OpAMD64VPADDUSW256
		return true
	case ssaop.OpAddSaturatedUint16x32:
		v.Op = ssaop.OpAMD64VPADDUSW512
		return true
	case ssaop.OpAddSaturatedUint16x8:
		v.Op = ssaop.OpAMD64VPADDUSW128
		return true
	case ssaop.OpAddSaturatedUint8x16:
		v.Op = ssaop.OpAMD64VPADDUSB128
		return true
	case ssaop.OpAddSaturatedUint8x32:
		v.Op = ssaop.OpAMD64VPADDUSB256
		return true
	case ssaop.OpAddSaturatedUint8x64:
		v.Op = ssaop.OpAMD64VPADDUSB512
		return true
	case ssaop.OpAddUint16x16:
		v.Op = ssaop.OpAMD64VPADDW256
		return true
	case ssaop.OpAddUint16x32:
		v.Op = ssaop.OpAMD64VPADDW512
		return true
	case ssaop.OpAddUint16x8:
		v.Op = ssaop.OpAMD64VPADDW128
		return true
	case ssaop.OpAddUint32x16:
		v.Op = ssaop.OpAMD64VPADDD512
		return true
	case ssaop.OpAddUint32x4:
		v.Op = ssaop.OpAMD64VPADDD128
		return true
	case ssaop.OpAddUint32x8:
		v.Op = ssaop.OpAMD64VPADDD256
		return true
	case ssaop.OpAddUint64x2:
		v.Op = ssaop.OpAMD64VPADDQ128
		return true
	case ssaop.OpAddUint64x4:
		v.Op = ssaop.OpAMD64VPADDQ256
		return true
	case ssaop.OpAddUint64x8:
		v.Op = ssaop.OpAMD64VPADDQ512
		return true
	case ssaop.OpAddUint8x16:
		v.Op = ssaop.OpAMD64VPADDB128
		return true
	case ssaop.OpAddUint8x32:
		v.Op = ssaop.OpAMD64VPADDB256
		return true
	case ssaop.OpAddUint8x64:
		v.Op = ssaop.OpAMD64VPADDB512
		return true
	case ssaop.OpAddr:
		return rewriteValue_OpAddr(v)
	case ssaop.OpAnd16:
		v.Op = ssaop.OpAMD64ANDL
		return true
	case ssaop.OpAnd32:
		v.Op = ssaop.OpAMD64ANDL
		return true
	case ssaop.OpAnd64:
		v.Op = ssaop.OpAMD64ANDQ
		return true
	case ssaop.OpAnd8:
		v.Op = ssaop.OpAMD64ANDL
		return true
	case ssaop.OpAndB:
		v.Op = ssaop.OpAMD64ANDL
		return true
	case ssaop.OpAndInt16x16:
		v.Op = ssaop.OpAMD64VPAND256
		return true
	case ssaop.OpAndInt16x32:
		v.Op = ssaop.OpAMD64VPANDD512
		return true
	case ssaop.OpAndInt16x8:
		v.Op = ssaop.OpAMD64VPAND128
		return true
	case ssaop.OpAndInt32x16:
		v.Op = ssaop.OpAMD64VPANDD512
		return true
	case ssaop.OpAndInt32x4:
		v.Op = ssaop.OpAMD64VPAND128
		return true
	case ssaop.OpAndInt32x8:
		v.Op = ssaop.OpAMD64VPAND256
		return true
	case ssaop.OpAndInt64x2:
		v.Op = ssaop.OpAMD64VPAND128
		return true
	case ssaop.OpAndInt64x4:
		v.Op = ssaop.OpAMD64VPAND256
		return true
	case ssaop.OpAndInt64x8:
		v.Op = ssaop.OpAMD64VPANDQ512
		return true
	case ssaop.OpAndInt8x16:
		v.Op = ssaop.OpAMD64VPAND128
		return true
	case ssaop.OpAndInt8x32:
		v.Op = ssaop.OpAMD64VPAND256
		return true
	case ssaop.OpAndInt8x64:
		v.Op = ssaop.OpAMD64VPANDD512
		return true
	case ssaop.OpAndNotInt16x16:
		v.Op = ssaop.OpAMD64VPANDN256
		return true
	case ssaop.OpAndNotInt16x32:
		v.Op = ssaop.OpAMD64VPANDND512
		return true
	case ssaop.OpAndNotInt16x8:
		v.Op = ssaop.OpAMD64VPANDN128
		return true
	case ssaop.OpAndNotInt32x16:
		v.Op = ssaop.OpAMD64VPANDND512
		return true
	case ssaop.OpAndNotInt32x4:
		v.Op = ssaop.OpAMD64VPANDN128
		return true
	case ssaop.OpAndNotInt32x8:
		v.Op = ssaop.OpAMD64VPANDN256
		return true
	case ssaop.OpAndNotInt64x2:
		v.Op = ssaop.OpAMD64VPANDN128
		return true
	case ssaop.OpAndNotInt64x4:
		v.Op = ssaop.OpAMD64VPANDN256
		return true
	case ssaop.OpAndNotInt64x8:
		v.Op = ssaop.OpAMD64VPANDNQ512
		return true
	case ssaop.OpAndNotInt8x16:
		v.Op = ssaop.OpAMD64VPANDN128
		return true
	case ssaop.OpAndNotInt8x32:
		v.Op = ssaop.OpAMD64VPANDN256
		return true
	case ssaop.OpAndNotInt8x64:
		v.Op = ssaop.OpAMD64VPANDND512
		return true
	case ssaop.OpAndNotUint16x16:
		v.Op = ssaop.OpAMD64VPANDN256
		return true
	case ssaop.OpAndNotUint16x32:
		v.Op = ssaop.OpAMD64VPANDND512
		return true
	case ssaop.OpAndNotUint16x8:
		v.Op = ssaop.OpAMD64VPANDN128
		return true
	case ssaop.OpAndNotUint32x16:
		v.Op = ssaop.OpAMD64VPANDND512
		return true
	case ssaop.OpAndNotUint32x4:
		v.Op = ssaop.OpAMD64VPANDN128
		return true
	case ssaop.OpAndNotUint32x8:
		v.Op = ssaop.OpAMD64VPANDN256
		return true
	case ssaop.OpAndNotUint64x2:
		v.Op = ssaop.OpAMD64VPANDN128
		return true
	case ssaop.OpAndNotUint64x4:
		v.Op = ssaop.OpAMD64VPANDN256
		return true
	case ssaop.OpAndNotUint64x8:
		v.Op = ssaop.OpAMD64VPANDNQ512
		return true
	case ssaop.OpAndNotUint8x16:
		v.Op = ssaop.OpAMD64VPANDN128
		return true
	case ssaop.OpAndNotUint8x32:
		v.Op = ssaop.OpAMD64VPANDN256
		return true
	case ssaop.OpAndNotUint8x64:
		v.Op = ssaop.OpAMD64VPANDND512
		return true
	case ssaop.OpAndUint16x16:
		v.Op = ssaop.OpAMD64VPAND256
		return true
	case ssaop.OpAndUint16x32:
		v.Op = ssaop.OpAMD64VPANDD512
		return true
	case ssaop.OpAndUint16x8:
		v.Op = ssaop.OpAMD64VPAND128
		return true
	case ssaop.OpAndUint32x16:
		v.Op = ssaop.OpAMD64VPANDD512
		return true
	case ssaop.OpAndUint32x4:
		v.Op = ssaop.OpAMD64VPAND128
		return true
	case ssaop.OpAndUint32x8:
		v.Op = ssaop.OpAMD64VPAND256
		return true
	case ssaop.OpAndUint64x2:
		v.Op = ssaop.OpAMD64VPAND128
		return true
	case ssaop.OpAndUint64x4:
		v.Op = ssaop.OpAMD64VPAND256
		return true
	case ssaop.OpAndUint64x8:
		v.Op = ssaop.OpAMD64VPANDQ512
		return true
	case ssaop.OpAndUint8x16:
		v.Op = ssaop.OpAMD64VPAND128
		return true
	case ssaop.OpAndUint8x32:
		v.Op = ssaop.OpAMD64VPAND256
		return true
	case ssaop.OpAndUint8x64:
		v.Op = ssaop.OpAMD64VPANDD512
		return true
	case ssaop.OpAtomicAdd32:
		return rewriteValue_OpAtomicAdd32(v)
	case ssaop.OpAtomicAdd64:
		return rewriteValue_OpAtomicAdd64(v)
	case ssaop.OpAtomicAnd32:
		return rewriteValue_OpAtomicAnd32(v)
	case ssaop.OpAtomicAnd32value:
		return rewriteValue_OpAtomicAnd32value(v)
	case ssaop.OpAtomicAnd64value:
		return rewriteValue_OpAtomicAnd64value(v)
	case ssaop.OpAtomicAnd8:
		return rewriteValue_OpAtomicAnd8(v)
	case ssaop.OpAtomicCompareAndSwap32:
		return rewriteValue_OpAtomicCompareAndSwap32(v)
	case ssaop.OpAtomicCompareAndSwap64:
		return rewriteValue_OpAtomicCompareAndSwap64(v)
	case ssaop.OpAtomicExchange32:
		return rewriteValue_OpAtomicExchange32(v)
	case ssaop.OpAtomicExchange64:
		return rewriteValue_OpAtomicExchange64(v)
	case ssaop.OpAtomicExchange8:
		return rewriteValue_OpAtomicExchange8(v)
	case ssaop.OpAtomicLoad32:
		return rewriteValue_OpAtomicLoad32(v)
	case ssaop.OpAtomicLoad64:
		return rewriteValue_OpAtomicLoad64(v)
	case ssaop.OpAtomicLoad8:
		return rewriteValue_OpAtomicLoad8(v)
	case ssaop.OpAtomicLoadPtr:
		return rewriteValue_OpAtomicLoadPtr(v)
	case ssaop.OpAtomicOr32:
		return rewriteValue_OpAtomicOr32(v)
	case ssaop.OpAtomicOr32value:
		return rewriteValue_OpAtomicOr32value(v)
	case ssaop.OpAtomicOr64value:
		return rewriteValue_OpAtomicOr64value(v)
	case ssaop.OpAtomicOr8:
		return rewriteValue_OpAtomicOr8(v)
	case ssaop.OpAtomicStore32:
		return rewriteValue_OpAtomicStore32(v)
	case ssaop.OpAtomicStore64:
		return rewriteValue_OpAtomicStore64(v)
	case ssaop.OpAtomicStore8:
		return rewriteValue_OpAtomicStore8(v)
	case ssaop.OpAtomicStorePtrNoWB:
		return rewriteValue_OpAtomicStorePtrNoWB(v)
	case ssaop.OpAverageUint16x16:
		v.Op = ssaop.OpAMD64VPAVGW256
		return true
	case ssaop.OpAverageUint16x32:
		v.Op = ssaop.OpAMD64VPAVGW512
		return true
	case ssaop.OpAverageUint16x8:
		v.Op = ssaop.OpAMD64VPAVGW128
		return true
	case ssaop.OpAverageUint8x16:
		v.Op = ssaop.OpAMD64VPAVGB128
		return true
	case ssaop.OpAverageUint8x32:
		v.Op = ssaop.OpAMD64VPAVGB256
		return true
	case ssaop.OpAverageUint8x64:
		v.Op = ssaop.OpAMD64VPAVGB512
		return true
	case ssaop.OpAvg64u:
		v.Op = ssaop.OpAMD64AVGQU
		return true
	case ssaop.OpBitLen16:
		return rewriteValue_OpBitLen16(v)
	case ssaop.OpBitLen32:
		return rewriteValue_OpBitLen32(v)
	case ssaop.OpBitLen64:
		return rewriteValue_OpBitLen64(v)
	case ssaop.OpBitLen8:
		return rewriteValue_OpBitLen8(v)
	case ssaop.OpBswap16:
		return rewriteValue_OpBswap16(v)
	case ssaop.OpBswap32:
		v.Op = ssaop.OpAMD64BSWAPL
		return true
	case ssaop.OpBswap64:
		v.Op = ssaop.OpAMD64BSWAPQ
		return true
	case ssaop.OpCeil:
		return rewriteValue_OpCeil(v)
	case ssaop.OpCeilFloat32x4:
		return rewriteValue_OpCeilFloat32x4(v)
	case ssaop.OpCeilFloat32x8:
		return rewriteValue_OpCeilFloat32x8(v)
	case ssaop.OpCeilFloat64x2:
		return rewriteValue_OpCeilFloat64x2(v)
	case ssaop.OpCeilFloat64x4:
		return rewriteValue_OpCeilFloat64x4(v)
	case ssaop.OpCeilScaledFloat32x16:
		return rewriteValue_OpCeilScaledFloat32x16(v)
	case ssaop.OpCeilScaledFloat32x4:
		return rewriteValue_OpCeilScaledFloat32x4(v)
	case ssaop.OpCeilScaledFloat32x8:
		return rewriteValue_OpCeilScaledFloat32x8(v)
	case ssaop.OpCeilScaledFloat64x2:
		return rewriteValue_OpCeilScaledFloat64x2(v)
	case ssaop.OpCeilScaledFloat64x4:
		return rewriteValue_OpCeilScaledFloat64x4(v)
	case ssaop.OpCeilScaledFloat64x8:
		return rewriteValue_OpCeilScaledFloat64x8(v)
	case ssaop.OpCeilScaledResidueFloat32x16:
		return rewriteValue_OpCeilScaledResidueFloat32x16(v)
	case ssaop.OpCeilScaledResidueFloat32x4:
		return rewriteValue_OpCeilScaledResidueFloat32x4(v)
	case ssaop.OpCeilScaledResidueFloat32x8:
		return rewriteValue_OpCeilScaledResidueFloat32x8(v)
	case ssaop.OpCeilScaledResidueFloat64x2:
		return rewriteValue_OpCeilScaledResidueFloat64x2(v)
	case ssaop.OpCeilScaledResidueFloat64x4:
		return rewriteValue_OpCeilScaledResidueFloat64x4(v)
	case ssaop.OpCeilScaledResidueFloat64x8:
		return rewriteValue_OpCeilScaledResidueFloat64x8(v)
	case ssaop.OpClosureCall:
		v.Op = ssaop.OpAMD64CALLclosure
		return true
	case ssaop.OpCom16:
		v.Op = ssaop.OpAMD64NOTL
		return true
	case ssaop.OpCom32:
		v.Op = ssaop.OpAMD64NOTL
		return true
	case ssaop.OpCom64:
		v.Op = ssaop.OpAMD64NOTQ
		return true
	case ssaop.OpCom8:
		v.Op = ssaop.OpAMD64NOTL
		return true
	case ssaop.OpCompressFloat32x16:
		return rewriteValue_OpCompressFloat32x16(v)
	case ssaop.OpCompressFloat32x4:
		return rewriteValue_OpCompressFloat32x4(v)
	case ssaop.OpCompressFloat32x8:
		return rewriteValue_OpCompressFloat32x8(v)
	case ssaop.OpCompressFloat64x2:
		return rewriteValue_OpCompressFloat64x2(v)
	case ssaop.OpCompressFloat64x4:
		return rewriteValue_OpCompressFloat64x4(v)
	case ssaop.OpCompressFloat64x8:
		return rewriteValue_OpCompressFloat64x8(v)
	case ssaop.OpCompressInt16x16:
		return rewriteValue_OpCompressInt16x16(v)
	case ssaop.OpCompressInt16x32:
		return rewriteValue_OpCompressInt16x32(v)
	case ssaop.OpCompressInt16x8:
		return rewriteValue_OpCompressInt16x8(v)
	case ssaop.OpCompressInt32x16:
		return rewriteValue_OpCompressInt32x16(v)
	case ssaop.OpCompressInt32x4:
		return rewriteValue_OpCompressInt32x4(v)
	case ssaop.OpCompressInt32x8:
		return rewriteValue_OpCompressInt32x8(v)
	case ssaop.OpCompressInt64x2:
		return rewriteValue_OpCompressInt64x2(v)
	case ssaop.OpCompressInt64x4:
		return rewriteValue_OpCompressInt64x4(v)
	case ssaop.OpCompressInt64x8:
		return rewriteValue_OpCompressInt64x8(v)
	case ssaop.OpCompressInt8x16:
		return rewriteValue_OpCompressInt8x16(v)
	case ssaop.OpCompressInt8x32:
		return rewriteValue_OpCompressInt8x32(v)
	case ssaop.OpCompressInt8x64:
		return rewriteValue_OpCompressInt8x64(v)
	case ssaop.OpCompressUint16x16:
		return rewriteValue_OpCompressUint16x16(v)
	case ssaop.OpCompressUint16x32:
		return rewriteValue_OpCompressUint16x32(v)
	case ssaop.OpCompressUint16x8:
		return rewriteValue_OpCompressUint16x8(v)
	case ssaop.OpCompressUint32x16:
		return rewriteValue_OpCompressUint32x16(v)
	case ssaop.OpCompressUint32x4:
		return rewriteValue_OpCompressUint32x4(v)
	case ssaop.OpCompressUint32x8:
		return rewriteValue_OpCompressUint32x8(v)
	case ssaop.OpCompressUint64x2:
		return rewriteValue_OpCompressUint64x2(v)
	case ssaop.OpCompressUint64x4:
		return rewriteValue_OpCompressUint64x4(v)
	case ssaop.OpCompressUint64x8:
		return rewriteValue_OpCompressUint64x8(v)
	case ssaop.OpCompressUint8x16:
		return rewriteValue_OpCompressUint8x16(v)
	case ssaop.OpCompressUint8x32:
		return rewriteValue_OpCompressUint8x32(v)
	case ssaop.OpCompressUint8x64:
		return rewriteValue_OpCompressUint8x64(v)
	case ssaop.OpConcatAddPairsFloat32x4:
		v.Op = ssaop.OpAMD64VHADDPS128
		return true
	case ssaop.OpConcatAddPairsFloat64x2:
		v.Op = ssaop.OpAMD64VHADDPD128
		return true
	case ssaop.OpConcatAddPairsGroupedFloat32x8:
		v.Op = ssaop.OpAMD64VHADDPS256
		return true
	case ssaop.OpConcatAddPairsGroupedFloat64x4:
		v.Op = ssaop.OpAMD64VHADDPD256
		return true
	case ssaop.OpConcatAddPairsGroupedInt16x16:
		v.Op = ssaop.OpAMD64VPHADDW256
		return true
	case ssaop.OpConcatAddPairsGroupedInt32x8:
		v.Op = ssaop.OpAMD64VPHADDD256
		return true
	case ssaop.OpConcatAddPairsGroupedUint16x16:
		v.Op = ssaop.OpAMD64VPHADDW256
		return true
	case ssaop.OpConcatAddPairsGroupedUint32x8:
		v.Op = ssaop.OpAMD64VPHADDD256
		return true
	case ssaop.OpConcatAddPairsInt16x8:
		v.Op = ssaop.OpAMD64VPHADDW128
		return true
	case ssaop.OpConcatAddPairsInt32x4:
		v.Op = ssaop.OpAMD64VPHADDD128
		return true
	case ssaop.OpConcatAddPairsSaturatedGroupedInt16x16:
		v.Op = ssaop.OpAMD64VPHADDSW256
		return true
	case ssaop.OpConcatAddPairsSaturatedInt16x8:
		v.Op = ssaop.OpAMD64VPHADDSW128
		return true
	case ssaop.OpConcatAddPairsUint16x8:
		v.Op = ssaop.OpAMD64VPHADDW128
		return true
	case ssaop.OpConcatAddPairsUint32x4:
		v.Op = ssaop.OpAMD64VPHADDD128
		return true
	case ssaop.OpConcatPermute128ScalarsFloat32x8:
		v.Op = ssaop.OpAMD64VPERM2F128256
		return true
	case ssaop.OpConcatPermute128ScalarsFloat64x4:
		v.Op = ssaop.OpAMD64VPERM2F128256
		return true
	case ssaop.OpConcatPermute128ScalarsInt16x16:
		v.Op = ssaop.OpAMD64VPERM2I128256
		return true
	case ssaop.OpConcatPermute128ScalarsInt32x8:
		v.Op = ssaop.OpAMD64VPERM2I128256
		return true
	case ssaop.OpConcatPermute128ScalarsInt64x4:
		v.Op = ssaop.OpAMD64VPERM2I128256
		return true
	case ssaop.OpConcatPermute128ScalarsInt8x32:
		v.Op = ssaop.OpAMD64VPERM2I128256
		return true
	case ssaop.OpConcatPermute128ScalarsUint16x16:
		v.Op = ssaop.OpAMD64VPERM2I128256
		return true
	case ssaop.OpConcatPermute128ScalarsUint32x8:
		v.Op = ssaop.OpAMD64VPERM2I128256
		return true
	case ssaop.OpConcatPermute128ScalarsUint64x4:
		v.Op = ssaop.OpAMD64VPERM2I128256
		return true
	case ssaop.OpConcatPermute128ScalarsUint8x32:
		v.Op = ssaop.OpAMD64VPERM2I128256
		return true
	case ssaop.OpConcatPermuteFloat32x16:
		v.Op = ssaop.OpAMD64VPERMI2PS512
		return true
	case ssaop.OpConcatPermuteFloat32x4:
		v.Op = ssaop.OpAMD64VPERMI2PS128
		return true
	case ssaop.OpConcatPermuteFloat32x8:
		v.Op = ssaop.OpAMD64VPERMI2PS256
		return true
	case ssaop.OpConcatPermuteFloat64x2:
		v.Op = ssaop.OpAMD64VPERMI2PD128
		return true
	case ssaop.OpConcatPermuteFloat64x4:
		v.Op = ssaop.OpAMD64VPERMI2PD256
		return true
	case ssaop.OpConcatPermuteFloat64x8:
		v.Op = ssaop.OpAMD64VPERMI2PD512
		return true
	case ssaop.OpConcatPermuteInt16x16:
		v.Op = ssaop.OpAMD64VPERMI2W256
		return true
	case ssaop.OpConcatPermuteInt16x32:
		v.Op = ssaop.OpAMD64VPERMI2W512
		return true
	case ssaop.OpConcatPermuteInt16x8:
		v.Op = ssaop.OpAMD64VPERMI2W128
		return true
	case ssaop.OpConcatPermuteInt32x16:
		v.Op = ssaop.OpAMD64VPERMI2D512
		return true
	case ssaop.OpConcatPermuteInt32x4:
		v.Op = ssaop.OpAMD64VPERMI2D128
		return true
	case ssaop.OpConcatPermuteInt32x8:
		v.Op = ssaop.OpAMD64VPERMI2D256
		return true
	case ssaop.OpConcatPermuteInt64x2:
		v.Op = ssaop.OpAMD64VPERMI2Q128
		return true
	case ssaop.OpConcatPermuteInt64x4:
		v.Op = ssaop.OpAMD64VPERMI2Q256
		return true
	case ssaop.OpConcatPermuteInt64x8:
		v.Op = ssaop.OpAMD64VPERMI2Q512
		return true
	case ssaop.OpConcatPermuteInt8x16:
		v.Op = ssaop.OpAMD64VPERMI2B128
		return true
	case ssaop.OpConcatPermuteInt8x32:
		v.Op = ssaop.OpAMD64VPERMI2B256
		return true
	case ssaop.OpConcatPermuteInt8x64:
		v.Op = ssaop.OpAMD64VPERMI2B512
		return true
	case ssaop.OpConcatPermuteUint16x16:
		v.Op = ssaop.OpAMD64VPERMI2W256
		return true
	case ssaop.OpConcatPermuteUint16x32:
		v.Op = ssaop.OpAMD64VPERMI2W512
		return true
	case ssaop.OpConcatPermuteUint16x8:
		v.Op = ssaop.OpAMD64VPERMI2W128
		return true
	case ssaop.OpConcatPermuteUint32x16:
		v.Op = ssaop.OpAMD64VPERMI2D512
		return true
	case ssaop.OpConcatPermuteUint32x4:
		v.Op = ssaop.OpAMD64VPERMI2D128
		return true
	case ssaop.OpConcatPermuteUint32x8:
		v.Op = ssaop.OpAMD64VPERMI2D256
		return true
	case ssaop.OpConcatPermuteUint64x2:
		v.Op = ssaop.OpAMD64VPERMI2Q128
		return true
	case ssaop.OpConcatPermuteUint64x4:
		v.Op = ssaop.OpAMD64VPERMI2Q256
		return true
	case ssaop.OpConcatPermuteUint64x8:
		v.Op = ssaop.OpAMD64VPERMI2Q512
		return true
	case ssaop.OpConcatPermuteUint8x16:
		v.Op = ssaop.OpAMD64VPERMI2B128
		return true
	case ssaop.OpConcatPermuteUint8x32:
		v.Op = ssaop.OpAMD64VPERMI2B256
		return true
	case ssaop.OpConcatPermuteUint8x64:
		v.Op = ssaop.OpAMD64VPERMI2B512
		return true
	case ssaop.OpConcatShiftBytesRightGroupedUint8x32:
		v.Op = ssaop.OpAMD64VPALIGNR256
		return true
	case ssaop.OpConcatShiftBytesRightGroupedUint8x64:
		v.Op = ssaop.OpAMD64VPALIGNR512
		return true
	case ssaop.OpConcatShiftBytesRightUint8x16:
		v.Op = ssaop.OpAMD64VPALIGNR128
		return true
	case ssaop.OpConcatSubPairsFloat32x4:
		v.Op = ssaop.OpAMD64VHSUBPS128
		return true
	case ssaop.OpConcatSubPairsFloat64x2:
		v.Op = ssaop.OpAMD64VHSUBPD128
		return true
	case ssaop.OpConcatSubPairsGroupedFloat32x8:
		v.Op = ssaop.OpAMD64VHSUBPS256
		return true
	case ssaop.OpConcatSubPairsGroupedFloat64x4:
		v.Op = ssaop.OpAMD64VHSUBPD256
		return true
	case ssaop.OpConcatSubPairsGroupedInt16x16:
		v.Op = ssaop.OpAMD64VPHSUBW256
		return true
	case ssaop.OpConcatSubPairsGroupedInt32x8:
		v.Op = ssaop.OpAMD64VPHSUBD256
		return true
	case ssaop.OpConcatSubPairsGroupedUint16x16:
		v.Op = ssaop.OpAMD64VPHSUBW256
		return true
	case ssaop.OpConcatSubPairsGroupedUint32x8:
		v.Op = ssaop.OpAMD64VPHSUBD256
		return true
	case ssaop.OpConcatSubPairsInt16x8:
		v.Op = ssaop.OpAMD64VPHSUBW128
		return true
	case ssaop.OpConcatSubPairsInt32x4:
		v.Op = ssaop.OpAMD64VPHSUBD128
		return true
	case ssaop.OpConcatSubPairsSaturatedGroupedInt16x16:
		v.Op = ssaop.OpAMD64VPHSUBSW256
		return true
	case ssaop.OpConcatSubPairsSaturatedInt16x8:
		v.Op = ssaop.OpAMD64VPHSUBSW128
		return true
	case ssaop.OpConcatSubPairsUint16x8:
		v.Op = ssaop.OpAMD64VPHSUBW128
		return true
	case ssaop.OpConcatSubPairsUint32x4:
		v.Op = ssaop.OpAMD64VPHSUBD128
		return true
	case ssaop.OpCondSelect:
		return rewriteValue_OpCondSelect(v)
	case ssaop.OpConst16:
		return rewriteValue_OpConst16(v)
	case ssaop.OpConst32:
		v.Op = ssaop.OpAMD64MOVLconst
		return true
	case ssaop.OpConst32F:
		v.Op = ssaop.OpAMD64MOVSSconst
		return true
	case ssaop.OpConst64:
		v.Op = ssaop.OpAMD64MOVQconst
		return true
	case ssaop.OpConst64F:
		v.Op = ssaop.OpAMD64MOVSDconst
		return true
	case ssaop.OpConst8:
		return rewriteValue_OpConst8(v)
	case ssaop.OpConstBool:
		return rewriteValue_OpConstBool(v)
	case ssaop.OpConstNil:
		return rewriteValue_OpConstNil(v)
	case ssaop.OpConvertToFloat32Float64x2:
		v.Op = ssaop.OpAMD64VCVTPD2PSX128
		return true
	case ssaop.OpConvertToFloat32Float64x4:
		v.Op = ssaop.OpAMD64VCVTPD2PSY128
		return true
	case ssaop.OpConvertToFloat32Float64x8:
		v.Op = ssaop.OpAMD64VCVTPD2PS256
		return true
	case ssaop.OpConvertToFloat32Int32x16:
		v.Op = ssaop.OpAMD64VCVTDQ2PS512
		return true
	case ssaop.OpConvertToFloat32Int32x4:
		v.Op = ssaop.OpAMD64VCVTDQ2PS128
		return true
	case ssaop.OpConvertToFloat32Int32x8:
		v.Op = ssaop.OpAMD64VCVTDQ2PS256
		return true
	case ssaop.OpConvertToFloat32Int64x2:
		v.Op = ssaop.OpAMD64VCVTQQ2PSX128
		return true
	case ssaop.OpConvertToFloat32Int64x4:
		v.Op = ssaop.OpAMD64VCVTQQ2PSY128
		return true
	case ssaop.OpConvertToFloat32Int64x8:
		v.Op = ssaop.OpAMD64VCVTQQ2PS256
		return true
	case ssaop.OpConvertToFloat32Uint32x16:
		v.Op = ssaop.OpAMD64VCVTUDQ2PS512
		return true
	case ssaop.OpConvertToFloat32Uint32x4:
		v.Op = ssaop.OpAMD64VCVTUDQ2PS128
		return true
	case ssaop.OpConvertToFloat32Uint32x8:
		v.Op = ssaop.OpAMD64VCVTUDQ2PS256
		return true
	case ssaop.OpConvertToFloat32Uint64x2:
		v.Op = ssaop.OpAMD64VCVTUQQ2PSX128
		return true
	case ssaop.OpConvertToFloat32Uint64x4:
		v.Op = ssaop.OpAMD64VCVTUQQ2PSY128
		return true
	case ssaop.OpConvertToFloat32Uint64x8:
		v.Op = ssaop.OpAMD64VCVTUQQ2PS256
		return true
	case ssaop.OpConvertToFloat64Float32x4:
		v.Op = ssaop.OpAMD64VCVTPS2PD256
		return true
	case ssaop.OpConvertToFloat64Float32x8:
		v.Op = ssaop.OpAMD64VCVTPS2PD512
		return true
	case ssaop.OpConvertToFloat64Int32x4:
		v.Op = ssaop.OpAMD64VCVTDQ2PD256
		return true
	case ssaop.OpConvertToFloat64Int32x8:
		v.Op = ssaop.OpAMD64VCVTDQ2PD512
		return true
	case ssaop.OpConvertToFloat64Int64x2:
		v.Op = ssaop.OpAMD64VCVTQQ2PD128
		return true
	case ssaop.OpConvertToFloat64Int64x4:
		v.Op = ssaop.OpAMD64VCVTQQ2PD256
		return true
	case ssaop.OpConvertToFloat64Int64x8:
		v.Op = ssaop.OpAMD64VCVTQQ2PD512
		return true
	case ssaop.OpConvertToFloat64Uint32x4:
		v.Op = ssaop.OpAMD64VCVTUDQ2PD256
		return true
	case ssaop.OpConvertToFloat64Uint32x8:
		v.Op = ssaop.OpAMD64VCVTUDQ2PD512
		return true
	case ssaop.OpConvertToFloat64Uint64x2:
		v.Op = ssaop.OpAMD64VCVTUQQ2PD128
		return true
	case ssaop.OpConvertToFloat64Uint64x4:
		v.Op = ssaop.OpAMD64VCVTUQQ2PD256
		return true
	case ssaop.OpConvertToFloat64Uint64x8:
		v.Op = ssaop.OpAMD64VCVTUQQ2PD512
		return true
	case ssaop.OpConvertToInt32Float32x16:
		v.Op = ssaop.OpAMD64VCVTTPS2DQ512
		return true
	case ssaop.OpConvertToInt32Float32x4:
		v.Op = ssaop.OpAMD64VCVTTPS2DQ128
		return true
	case ssaop.OpConvertToInt32Float32x8:
		v.Op = ssaop.OpAMD64VCVTTPS2DQ256
		return true
	case ssaop.OpConvertToInt32Float64x2:
		v.Op = ssaop.OpAMD64VCVTTPD2DQX128
		return true
	case ssaop.OpConvertToInt32Float64x4:
		v.Op = ssaop.OpAMD64VCVTTPD2DQY128
		return true
	case ssaop.OpConvertToInt32Float64x8:
		v.Op = ssaop.OpAMD64VCVTTPD2DQ256
		return true
	case ssaop.OpConvertToInt64Float32x4:
		v.Op = ssaop.OpAMD64VCVTTPS2QQ256
		return true
	case ssaop.OpConvertToInt64Float32x8:
		v.Op = ssaop.OpAMD64VCVTTPS2QQ512
		return true
	case ssaop.OpConvertToInt64Float64x2:
		v.Op = ssaop.OpAMD64VCVTTPD2QQ128
		return true
	case ssaop.OpConvertToInt64Float64x4:
		v.Op = ssaop.OpAMD64VCVTTPD2QQ256
		return true
	case ssaop.OpConvertToInt64Float64x8:
		v.Op = ssaop.OpAMD64VCVTTPD2QQ512
		return true
	case ssaop.OpConvertToUint32Float32x16:
		v.Op = ssaop.OpAMD64VCVTTPS2UDQ512
		return true
	case ssaop.OpConvertToUint32Float32x4:
		v.Op = ssaop.OpAMD64VCVTTPS2UDQ128
		return true
	case ssaop.OpConvertToUint32Float32x8:
		v.Op = ssaop.OpAMD64VCVTTPS2UDQ256
		return true
	case ssaop.OpConvertToUint32Float64x2:
		v.Op = ssaop.OpAMD64VCVTTPD2UDQX128
		return true
	case ssaop.OpConvertToUint32Float64x4:
		v.Op = ssaop.OpAMD64VCVTTPD2UDQY128
		return true
	case ssaop.OpConvertToUint32Float64x8:
		v.Op = ssaop.OpAMD64VCVTTPD2UDQ256
		return true
	case ssaop.OpConvertToUint64Float32x4:
		v.Op = ssaop.OpAMD64VCVTTPS2UQQ256
		return true
	case ssaop.OpConvertToUint64Float32x8:
		v.Op = ssaop.OpAMD64VCVTTPS2UQQ512
		return true
	case ssaop.OpConvertToUint64Float64x2:
		v.Op = ssaop.OpAMD64VCVTTPD2UQQ128
		return true
	case ssaop.OpConvertToUint64Float64x4:
		v.Op = ssaop.OpAMD64VCVTTPD2UQQ256
		return true
	case ssaop.OpConvertToUint64Float64x8:
		v.Op = ssaop.OpAMD64VCVTTPD2UQQ512
		return true
	case ssaop.OpCtz16:
		return rewriteValue_OpCtz16(v)
	case ssaop.OpCtz16NonZero:
		return rewriteValue_OpCtz16NonZero(v)
	case ssaop.OpCtz32:
		return rewriteValue_OpCtz32(v)
	case ssaop.OpCtz32NonZero:
		return rewriteValue_OpCtz32NonZero(v)
	case ssaop.OpCtz64:
		return rewriteValue_OpCtz64(v)
	case ssaop.OpCtz64NonZero:
		return rewriteValue_OpCtz64NonZero(v)
	case ssaop.OpCtz8:
		return rewriteValue_OpCtz8(v)
	case ssaop.OpCtz8NonZero:
		return rewriteValue_OpCtz8NonZero(v)
	case ssaop.OpCvt16toMask16x16:
		return rewriteValue_OpCvt16toMask16x16(v)
	case ssaop.OpCvt16toMask32x16:
		return rewriteValue_OpCvt16toMask32x16(v)
	case ssaop.OpCvt16toMask8x16:
		return rewriteValue_OpCvt16toMask8x16(v)
	case ssaop.OpCvt32Fto32:
		return rewriteValue_OpCvt32Fto32(v)
	case ssaop.OpCvt32Fto64:
		return rewriteValue_OpCvt32Fto64(v)
	case ssaop.OpCvt32Fto64F:
		v.Op = ssaop.OpAMD64CVTSS2SD
		return true
	case ssaop.OpCvt32to32F:
		v.Op = ssaop.OpAMD64CVTSL2SS
		return true
	case ssaop.OpCvt32to64F:
		v.Op = ssaop.OpAMD64CVTSL2SD
		return true
	case ssaop.OpCvt32toMask16x32:
		return rewriteValue_OpCvt32toMask16x32(v)
	case ssaop.OpCvt32toMask8x32:
		return rewriteValue_OpCvt32toMask8x32(v)
	case ssaop.OpCvt64Fto32:
		return rewriteValue_OpCvt64Fto32(v)
	case ssaop.OpCvt64Fto32F:
		v.Op = ssaop.OpAMD64CVTSD2SS
		return true
	case ssaop.OpCvt64Fto64:
		return rewriteValue_OpCvt64Fto64(v)
	case ssaop.OpCvt64to32F:
		v.Op = ssaop.OpAMD64CVTSQ2SS
		return true
	case ssaop.OpCvt64to64F:
		v.Op = ssaop.OpAMD64CVTSQ2SD
		return true
	case ssaop.OpCvt64toMask8x64:
		return rewriteValue_OpCvt64toMask8x64(v)
	case ssaop.OpCvt8toMask16x8:
		return rewriteValue_OpCvt8toMask16x8(v)
	case ssaop.OpCvt8toMask32x4:
		return rewriteValue_OpCvt8toMask32x4(v)
	case ssaop.OpCvt8toMask32x8:
		return rewriteValue_OpCvt8toMask32x8(v)
	case ssaop.OpCvt8toMask64x2:
		return rewriteValue_OpCvt8toMask64x2(v)
	case ssaop.OpCvt8toMask64x4:
		return rewriteValue_OpCvt8toMask64x4(v)
	case ssaop.OpCvt8toMask64x8:
		return rewriteValue_OpCvt8toMask64x8(v)
	case ssaop.OpCvtBoolToUint8:
		v.Op = ssaop.OpCopy
		return true
	case ssaop.OpCvtMask16x16to16:
		return rewriteValue_OpCvtMask16x16to16(v)
	case ssaop.OpCvtMask16x32to32:
		return rewriteValue_OpCvtMask16x32to32(v)
	case ssaop.OpCvtMask16x8to8:
		return rewriteValue_OpCvtMask16x8to8(v)
	case ssaop.OpCvtMask32x16to16:
		return rewriteValue_OpCvtMask32x16to16(v)
	case ssaop.OpCvtMask32x4to8:
		v.Op = ssaop.OpAMD64VMOVMSKPS128
		return true
	case ssaop.OpCvtMask32x8to8:
		v.Op = ssaop.OpAMD64VMOVMSKPS256
		return true
	case ssaop.OpCvtMask64x2to8:
		v.Op = ssaop.OpAMD64VMOVMSKPD128
		return true
	case ssaop.OpCvtMask64x4to8:
		v.Op = ssaop.OpAMD64VMOVMSKPD256
		return true
	case ssaop.OpCvtMask64x8to8:
		return rewriteValue_OpCvtMask64x8to8(v)
	case ssaop.OpCvtMask8x16to16:
		v.Op = ssaop.OpAMD64VPMOVMSKB128
		return true
	case ssaop.OpCvtMask8x32to32:
		v.Op = ssaop.OpAMD64VPMOVMSKB256
		return true
	case ssaop.OpCvtMask8x64to64:
		return rewriteValue_OpCvtMask8x64to64(v)
	case ssaop.OpDiv128u:
		v.Op = ssaop.OpAMD64DIVQU2
		return true
	case ssaop.OpDiv16:
		return rewriteValue_OpDiv16(v)
	case ssaop.OpDiv16u:
		return rewriteValue_OpDiv16u(v)
	case ssaop.OpDiv32:
		return rewriteValue_OpDiv32(v)
	case ssaop.OpDiv32F:
		v.Op = ssaop.OpAMD64DIVSS
		return true
	case ssaop.OpDiv32u:
		return rewriteValue_OpDiv32u(v)
	case ssaop.OpDiv64:
		return rewriteValue_OpDiv64(v)
	case ssaop.OpDiv64F:
		v.Op = ssaop.OpAMD64DIVSD
		return true
	case ssaop.OpDiv64u:
		return rewriteValue_OpDiv64u(v)
	case ssaop.OpDiv8:
		return rewriteValue_OpDiv8(v)
	case ssaop.OpDiv8u:
		return rewriteValue_OpDiv8u(v)
	case ssaop.OpDivFloat32x16:
		v.Op = ssaop.OpAMD64VDIVPS512
		return true
	case ssaop.OpDivFloat32x4:
		v.Op = ssaop.OpAMD64VDIVPS128
		return true
	case ssaop.OpDivFloat32x8:
		v.Op = ssaop.OpAMD64VDIVPS256
		return true
	case ssaop.OpDivFloat64x2:
		v.Op = ssaop.OpAMD64VDIVPD128
		return true
	case ssaop.OpDivFloat64x4:
		v.Op = ssaop.OpAMD64VDIVPD256
		return true
	case ssaop.OpDivFloat64x8:
		v.Op = ssaop.OpAMD64VDIVPD512
		return true
	case ssaop.OpDotProductPairsInt16x16:
		v.Op = ssaop.OpAMD64VPMADDWD256
		return true
	case ssaop.OpDotProductPairsInt16x32:
		v.Op = ssaop.OpAMD64VPMADDWD512
		return true
	case ssaop.OpDotProductPairsInt16x8:
		v.Op = ssaop.OpAMD64VPMADDWD128
		return true
	case ssaop.OpDotProductPairsSaturatedUint8x16:
		v.Op = ssaop.OpAMD64VPMADDUBSW128
		return true
	case ssaop.OpDotProductPairsSaturatedUint8x32:
		v.Op = ssaop.OpAMD64VPMADDUBSW256
		return true
	case ssaop.OpDotProductPairsSaturatedUint8x64:
		v.Op = ssaop.OpAMD64VPMADDUBSW512
		return true
	case ssaop.OpEq16:
		return rewriteValue_OpEq16(v)
	case ssaop.OpEq32:
		return rewriteValue_OpEq32(v)
	case ssaop.OpEq32F:
		return rewriteValue_OpEq32F(v)
	case ssaop.OpEq64:
		return rewriteValue_OpEq64(v)
	case ssaop.OpEq64F:
		return rewriteValue_OpEq64F(v)
	case ssaop.OpEq8:
		return rewriteValue_OpEq8(v)
	case ssaop.OpEqB:
		return rewriteValue_OpEqB(v)
	case ssaop.OpEqPtr:
		return rewriteValue_OpEqPtr(v)
	case ssaop.OpEqualFloat32x16:
		return rewriteValue_OpEqualFloat32x16(v)
	case ssaop.OpEqualFloat32x4:
		return rewriteValue_OpEqualFloat32x4(v)
	case ssaop.OpEqualFloat32x8:
		return rewriteValue_OpEqualFloat32x8(v)
	case ssaop.OpEqualFloat64x2:
		return rewriteValue_OpEqualFloat64x2(v)
	case ssaop.OpEqualFloat64x4:
		return rewriteValue_OpEqualFloat64x4(v)
	case ssaop.OpEqualFloat64x8:
		return rewriteValue_OpEqualFloat64x8(v)
	case ssaop.OpEqualInt16x16:
		v.Op = ssaop.OpAMD64VPCMPEQW256
		return true
	case ssaop.OpEqualInt16x32:
		return rewriteValue_OpEqualInt16x32(v)
	case ssaop.OpEqualInt16x8:
		v.Op = ssaop.OpAMD64VPCMPEQW128
		return true
	case ssaop.OpEqualInt32x16:
		return rewriteValue_OpEqualInt32x16(v)
	case ssaop.OpEqualInt32x4:
		v.Op = ssaop.OpAMD64VPCMPEQD128
		return true
	case ssaop.OpEqualInt32x8:
		v.Op = ssaop.OpAMD64VPCMPEQD256
		return true
	case ssaop.OpEqualInt64x2:
		v.Op = ssaop.OpAMD64VPCMPEQQ128
		return true
	case ssaop.OpEqualInt64x4:
		v.Op = ssaop.OpAMD64VPCMPEQQ256
		return true
	case ssaop.OpEqualInt64x8:
		return rewriteValue_OpEqualInt64x8(v)
	case ssaop.OpEqualInt8x16:
		v.Op = ssaop.OpAMD64VPCMPEQB128
		return true
	case ssaop.OpEqualInt8x32:
		v.Op = ssaop.OpAMD64VPCMPEQB256
		return true
	case ssaop.OpEqualInt8x64:
		return rewriteValue_OpEqualInt8x64(v)
	case ssaop.OpEqualUint16x16:
		v.Op = ssaop.OpAMD64VPCMPEQW256
		return true
	case ssaop.OpEqualUint16x32:
		return rewriteValue_OpEqualUint16x32(v)
	case ssaop.OpEqualUint16x8:
		v.Op = ssaop.OpAMD64VPCMPEQW128
		return true
	case ssaop.OpEqualUint32x16:
		return rewriteValue_OpEqualUint32x16(v)
	case ssaop.OpEqualUint32x4:
		v.Op = ssaop.OpAMD64VPCMPEQD128
		return true
	case ssaop.OpEqualUint32x8:
		v.Op = ssaop.OpAMD64VPCMPEQD256
		return true
	case ssaop.OpEqualUint64x2:
		v.Op = ssaop.OpAMD64VPCMPEQQ128
		return true
	case ssaop.OpEqualUint64x4:
		v.Op = ssaop.OpAMD64VPCMPEQQ256
		return true
	case ssaop.OpEqualUint64x8:
		return rewriteValue_OpEqualUint64x8(v)
	case ssaop.OpEqualUint8x16:
		v.Op = ssaop.OpAMD64VPCMPEQB128
		return true
	case ssaop.OpEqualUint8x32:
		v.Op = ssaop.OpAMD64VPCMPEQB256
		return true
	case ssaop.OpEqualUint8x64:
		return rewriteValue_OpEqualUint8x64(v)
	case ssaop.OpExpandFloat32x16:
		return rewriteValue_OpExpandFloat32x16(v)
	case ssaop.OpExpandFloat32x4:
		return rewriteValue_OpExpandFloat32x4(v)
	case ssaop.OpExpandFloat32x8:
		return rewriteValue_OpExpandFloat32x8(v)
	case ssaop.OpExpandFloat64x2:
		return rewriteValue_OpExpandFloat64x2(v)
	case ssaop.OpExpandFloat64x4:
		return rewriteValue_OpExpandFloat64x4(v)
	case ssaop.OpExpandFloat64x8:
		return rewriteValue_OpExpandFloat64x8(v)
	case ssaop.OpExpandInt16x16:
		return rewriteValue_OpExpandInt16x16(v)
	case ssaop.OpExpandInt16x32:
		return rewriteValue_OpExpandInt16x32(v)
	case ssaop.OpExpandInt16x8:
		return rewriteValue_OpExpandInt16x8(v)
	case ssaop.OpExpandInt32x16:
		return rewriteValue_OpExpandInt32x16(v)
	case ssaop.OpExpandInt32x4:
		return rewriteValue_OpExpandInt32x4(v)
	case ssaop.OpExpandInt32x8:
		return rewriteValue_OpExpandInt32x8(v)
	case ssaop.OpExpandInt64x2:
		return rewriteValue_OpExpandInt64x2(v)
	case ssaop.OpExpandInt64x4:
		return rewriteValue_OpExpandInt64x4(v)
	case ssaop.OpExpandInt64x8:
		return rewriteValue_OpExpandInt64x8(v)
	case ssaop.OpExpandInt8x16:
		return rewriteValue_OpExpandInt8x16(v)
	case ssaop.OpExpandInt8x32:
		return rewriteValue_OpExpandInt8x32(v)
	case ssaop.OpExpandInt8x64:
		return rewriteValue_OpExpandInt8x64(v)
	case ssaop.OpExpandUint16x16:
		return rewriteValue_OpExpandUint16x16(v)
	case ssaop.OpExpandUint16x32:
		return rewriteValue_OpExpandUint16x32(v)
	case ssaop.OpExpandUint16x8:
		return rewriteValue_OpExpandUint16x8(v)
	case ssaop.OpExpandUint32x16:
		return rewriteValue_OpExpandUint32x16(v)
	case ssaop.OpExpandUint32x4:
		return rewriteValue_OpExpandUint32x4(v)
	case ssaop.OpExpandUint32x8:
		return rewriteValue_OpExpandUint32x8(v)
	case ssaop.OpExpandUint64x2:
		return rewriteValue_OpExpandUint64x2(v)
	case ssaop.OpExpandUint64x4:
		return rewriteValue_OpExpandUint64x4(v)
	case ssaop.OpExpandUint64x8:
		return rewriteValue_OpExpandUint64x8(v)
	case ssaop.OpExpandUint8x16:
		return rewriteValue_OpExpandUint8x16(v)
	case ssaop.OpExpandUint8x32:
		return rewriteValue_OpExpandUint8x32(v)
	case ssaop.OpExpandUint8x64:
		return rewriteValue_OpExpandUint8x64(v)
	case ssaop.OpExtendLo2ToInt64Int16x8:
		v.Op = ssaop.OpAMD64VPMOVSXWQ128
		return true
	case ssaop.OpExtendLo2ToInt64Int32x4:
		v.Op = ssaop.OpAMD64VPMOVSXDQ128
		return true
	case ssaop.OpExtendLo2ToInt64Int8x16:
		v.Op = ssaop.OpAMD64VPMOVSXBQ128
		return true
	case ssaop.OpExtendLo2ToUint64Uint16x8:
		v.Op = ssaop.OpAMD64VPMOVZXWQ128
		return true
	case ssaop.OpExtendLo2ToUint64Uint32x4:
		v.Op = ssaop.OpAMD64VPMOVZXDQ128
		return true
	case ssaop.OpExtendLo2ToUint64Uint8x16:
		v.Op = ssaop.OpAMD64VPMOVZXBQ128
		return true
	case ssaop.OpExtendLo4ToInt32Int16x8:
		v.Op = ssaop.OpAMD64VPMOVSXWD128
		return true
	case ssaop.OpExtendLo4ToInt32Int8x16:
		v.Op = ssaop.OpAMD64VPMOVSXBD128
		return true
	case ssaop.OpExtendLo4ToInt64Int16x8:
		v.Op = ssaop.OpAMD64VPMOVSXWQ256
		return true
	case ssaop.OpExtendLo4ToInt64Int8x16:
		v.Op = ssaop.OpAMD64VPMOVSXBQ256
		return true
	case ssaop.OpExtendLo4ToUint32Uint16x8:
		v.Op = ssaop.OpAMD64VPMOVZXWD128
		return true
	case ssaop.OpExtendLo4ToUint32Uint8x16:
		v.Op = ssaop.OpAMD64VPMOVZXBD128
		return true
	case ssaop.OpExtendLo4ToUint64Uint16x8:
		v.Op = ssaop.OpAMD64VPMOVZXWQ256
		return true
	case ssaop.OpExtendLo4ToUint64Uint8x16:
		v.Op = ssaop.OpAMD64VPMOVZXBQ256
		return true
	case ssaop.OpExtendLo8ToInt16Int8x16:
		v.Op = ssaop.OpAMD64VPMOVSXBW128
		return true
	case ssaop.OpExtendLo8ToInt32Int8x16:
		v.Op = ssaop.OpAMD64VPMOVSXBD256
		return true
	case ssaop.OpExtendLo8ToInt64Int8x16:
		v.Op = ssaop.OpAMD64VPMOVSXBQ512
		return true
	case ssaop.OpExtendLo8ToUint16Uint8x16:
		v.Op = ssaop.OpAMD64VPMOVZXBW128
		return true
	case ssaop.OpExtendLo8ToUint32Uint8x16:
		v.Op = ssaop.OpAMD64VPMOVZXBD256
		return true
	case ssaop.OpExtendLo8ToUint64Uint8x16:
		v.Op = ssaop.OpAMD64VPMOVZXBQ512
		return true
	case ssaop.OpExtendToInt16Int8x16:
		v.Op = ssaop.OpAMD64VPMOVSXBW256
		return true
	case ssaop.OpExtendToInt16Int8x32:
		v.Op = ssaop.OpAMD64VPMOVSXBW512
		return true
	case ssaop.OpExtendToInt32Int16x16:
		v.Op = ssaop.OpAMD64VPMOVSXWD512
		return true
	case ssaop.OpExtendToInt32Int16x8:
		v.Op = ssaop.OpAMD64VPMOVSXWD256
		return true
	case ssaop.OpExtendToInt32Int8x16:
		v.Op = ssaop.OpAMD64VPMOVSXBD512
		return true
	case ssaop.OpExtendToInt64Int16x8:
		v.Op = ssaop.OpAMD64VPMOVSXWQ512
		return true
	case ssaop.OpExtendToInt64Int32x4:
		v.Op = ssaop.OpAMD64VPMOVSXDQ256
		return true
	case ssaop.OpExtendToInt64Int32x8:
		v.Op = ssaop.OpAMD64VPMOVSXDQ512
		return true
	case ssaop.OpExtendToUint16Uint8x16:
		v.Op = ssaop.OpAMD64VPMOVZXBW256
		return true
	case ssaop.OpExtendToUint16Uint8x32:
		v.Op = ssaop.OpAMD64VPMOVZXBW512
		return true
	case ssaop.OpExtendToUint32Uint16x16:
		v.Op = ssaop.OpAMD64VPMOVZXWD512
		return true
	case ssaop.OpExtendToUint32Uint16x8:
		v.Op = ssaop.OpAMD64VPMOVZXWD256
		return true
	case ssaop.OpExtendToUint32Uint8x16:
		v.Op = ssaop.OpAMD64VPMOVZXBD512
		return true
	case ssaop.OpExtendToUint64Uint16x8:
		v.Op = ssaop.OpAMD64VPMOVZXWQ512
		return true
	case ssaop.OpExtendToUint64Uint32x4:
		v.Op = ssaop.OpAMD64VPMOVZXDQ256
		return true
	case ssaop.OpExtendToUint64Uint32x8:
		v.Op = ssaop.OpAMD64VPMOVZXDQ512
		return true
	case ssaop.OpFMA:
		return rewriteValue_OpFMA(v)
	case ssaop.OpFloor:
		return rewriteValue_OpFloor(v)
	case ssaop.OpFloorFloat32x4:
		return rewriteValue_OpFloorFloat32x4(v)
	case ssaop.OpFloorFloat32x8:
		return rewriteValue_OpFloorFloat32x8(v)
	case ssaop.OpFloorFloat64x2:
		return rewriteValue_OpFloorFloat64x2(v)
	case ssaop.OpFloorFloat64x4:
		return rewriteValue_OpFloorFloat64x4(v)
	case ssaop.OpFloorScaledFloat32x16:
		return rewriteValue_OpFloorScaledFloat32x16(v)
	case ssaop.OpFloorScaledFloat32x4:
		return rewriteValue_OpFloorScaledFloat32x4(v)
	case ssaop.OpFloorScaledFloat32x8:
		return rewriteValue_OpFloorScaledFloat32x8(v)
	case ssaop.OpFloorScaledFloat64x2:
		return rewriteValue_OpFloorScaledFloat64x2(v)
	case ssaop.OpFloorScaledFloat64x4:
		return rewriteValue_OpFloorScaledFloat64x4(v)
	case ssaop.OpFloorScaledFloat64x8:
		return rewriteValue_OpFloorScaledFloat64x8(v)
	case ssaop.OpFloorScaledResidueFloat32x16:
		return rewriteValue_OpFloorScaledResidueFloat32x16(v)
	case ssaop.OpFloorScaledResidueFloat32x4:
		return rewriteValue_OpFloorScaledResidueFloat32x4(v)
	case ssaop.OpFloorScaledResidueFloat32x8:
		return rewriteValue_OpFloorScaledResidueFloat32x8(v)
	case ssaop.OpFloorScaledResidueFloat64x2:
		return rewriteValue_OpFloorScaledResidueFloat64x2(v)
	case ssaop.OpFloorScaledResidueFloat64x4:
		return rewriteValue_OpFloorScaledResidueFloat64x4(v)
	case ssaop.OpFloorScaledResidueFloat64x8:
		return rewriteValue_OpFloorScaledResidueFloat64x8(v)
	case ssaop.OpGaloisFieldAffineTransformInverseUint8x16:
		v.Op = ssaop.OpAMD64VGF2P8AFFINEINVQB128
		return true
	case ssaop.OpGaloisFieldAffineTransformInverseUint8x32:
		v.Op = ssaop.OpAMD64VGF2P8AFFINEINVQB256
		return true
	case ssaop.OpGaloisFieldAffineTransformInverseUint8x64:
		v.Op = ssaop.OpAMD64VGF2P8AFFINEINVQB512
		return true
	case ssaop.OpGaloisFieldAffineTransformUint8x16:
		v.Op = ssaop.OpAMD64VGF2P8AFFINEQB128
		return true
	case ssaop.OpGaloisFieldAffineTransformUint8x32:
		v.Op = ssaop.OpAMD64VGF2P8AFFINEQB256
		return true
	case ssaop.OpGaloisFieldAffineTransformUint8x64:
		v.Op = ssaop.OpAMD64VGF2P8AFFINEQB512
		return true
	case ssaop.OpGaloisFieldMulUint8x16:
		v.Op = ssaop.OpAMD64VGF2P8MULB128
		return true
	case ssaop.OpGaloisFieldMulUint8x32:
		v.Op = ssaop.OpAMD64VGF2P8MULB256
		return true
	case ssaop.OpGaloisFieldMulUint8x64:
		v.Op = ssaop.OpAMD64VGF2P8MULB512
		return true
	case ssaop.OpGetCallerPC:
		v.Op = ssaop.OpAMD64LoweredGetCallerPC
		return true
	case ssaop.OpGetCallerSP:
		v.Op = ssaop.OpAMD64LoweredGetCallerSP
		return true
	case ssaop.OpGetClosurePtr:
		v.Op = ssaop.OpAMD64LoweredGetClosurePtr
		return true
	case ssaop.OpGetElemFloat32x4:
		v.Op = ssaop.OpAMD64VPEXTRD128
		return true
	case ssaop.OpGetElemFloat64x2:
		v.Op = ssaop.OpAMD64VPEXTRQ128
		return true
	case ssaop.OpGetElemInt16x8:
		v.Op = ssaop.OpAMD64VPEXTRW128
		return true
	case ssaop.OpGetElemInt32x4:
		v.Op = ssaop.OpAMD64VPEXTRD128
		return true
	case ssaop.OpGetElemInt64x2:
		v.Op = ssaop.OpAMD64VPEXTRQ128
		return true
	case ssaop.OpGetElemInt8x16:
		v.Op = ssaop.OpAMD64VPEXTRB128
		return true
	case ssaop.OpGetElemUint16x8:
		v.Op = ssaop.OpAMD64VPEXTRW128
		return true
	case ssaop.OpGetElemUint32x4:
		v.Op = ssaop.OpAMD64VPEXTRD128
		return true
	case ssaop.OpGetElemUint64x2:
		v.Op = ssaop.OpAMD64VPEXTRQ128
		return true
	case ssaop.OpGetElemUint8x16:
		v.Op = ssaop.OpAMD64VPEXTRB128
		return true
	case ssaop.OpGetG:
		return rewriteValue_OpGetG(v)
	case ssaop.OpGetHiFloat32x16:
		return rewriteValue_OpGetHiFloat32x16(v)
	case ssaop.OpGetHiFloat32x8:
		return rewriteValue_OpGetHiFloat32x8(v)
	case ssaop.OpGetHiFloat64x4:
		return rewriteValue_OpGetHiFloat64x4(v)
	case ssaop.OpGetHiFloat64x8:
		return rewriteValue_OpGetHiFloat64x8(v)
	case ssaop.OpGetHiInt16x16:
		return rewriteValue_OpGetHiInt16x16(v)
	case ssaop.OpGetHiInt16x32:
		return rewriteValue_OpGetHiInt16x32(v)
	case ssaop.OpGetHiInt32x16:
		return rewriteValue_OpGetHiInt32x16(v)
	case ssaop.OpGetHiInt32x8:
		return rewriteValue_OpGetHiInt32x8(v)
	case ssaop.OpGetHiInt64x4:
		return rewriteValue_OpGetHiInt64x4(v)
	case ssaop.OpGetHiInt64x8:
		return rewriteValue_OpGetHiInt64x8(v)
	case ssaop.OpGetHiInt8x32:
		return rewriteValue_OpGetHiInt8x32(v)
	case ssaop.OpGetHiInt8x64:
		return rewriteValue_OpGetHiInt8x64(v)
	case ssaop.OpGetHiUint16x16:
		return rewriteValue_OpGetHiUint16x16(v)
	case ssaop.OpGetHiUint16x32:
		return rewriteValue_OpGetHiUint16x32(v)
	case ssaop.OpGetHiUint32x16:
		return rewriteValue_OpGetHiUint32x16(v)
	case ssaop.OpGetHiUint32x8:
		return rewriteValue_OpGetHiUint32x8(v)
	case ssaop.OpGetHiUint64x4:
		return rewriteValue_OpGetHiUint64x4(v)
	case ssaop.OpGetHiUint64x8:
		return rewriteValue_OpGetHiUint64x8(v)
	case ssaop.OpGetHiUint8x32:
		return rewriteValue_OpGetHiUint8x32(v)
	case ssaop.OpGetHiUint8x64:
		return rewriteValue_OpGetHiUint8x64(v)
	case ssaop.OpGetLoFloat32x16:
		return rewriteValue_OpGetLoFloat32x16(v)
	case ssaop.OpGetLoFloat32x8:
		return rewriteValue_OpGetLoFloat32x8(v)
	case ssaop.OpGetLoFloat64x4:
		return rewriteValue_OpGetLoFloat64x4(v)
	case ssaop.OpGetLoFloat64x8:
		return rewriteValue_OpGetLoFloat64x8(v)
	case ssaop.OpGetLoInt16x16:
		return rewriteValue_OpGetLoInt16x16(v)
	case ssaop.OpGetLoInt16x32:
		return rewriteValue_OpGetLoInt16x32(v)
	case ssaop.OpGetLoInt32x16:
		return rewriteValue_OpGetLoInt32x16(v)
	case ssaop.OpGetLoInt32x8:
		return rewriteValue_OpGetLoInt32x8(v)
	case ssaop.OpGetLoInt64x4:
		return rewriteValue_OpGetLoInt64x4(v)
	case ssaop.OpGetLoInt64x8:
		return rewriteValue_OpGetLoInt64x8(v)
	case ssaop.OpGetLoInt8x32:
		return rewriteValue_OpGetLoInt8x32(v)
	case ssaop.OpGetLoInt8x64:
		return rewriteValue_OpGetLoInt8x64(v)
	case ssaop.OpGetLoUint16x16:
		return rewriteValue_OpGetLoUint16x16(v)
	case ssaop.OpGetLoUint16x32:
		return rewriteValue_OpGetLoUint16x32(v)
	case ssaop.OpGetLoUint32x16:
		return rewriteValue_OpGetLoUint32x16(v)
	case ssaop.OpGetLoUint32x8:
		return rewriteValue_OpGetLoUint32x8(v)
	case ssaop.OpGetLoUint64x4:
		return rewriteValue_OpGetLoUint64x4(v)
	case ssaop.OpGetLoUint64x8:
		return rewriteValue_OpGetLoUint64x8(v)
	case ssaop.OpGetLoUint8x32:
		return rewriteValue_OpGetLoUint8x32(v)
	case ssaop.OpGetLoUint8x64:
		return rewriteValue_OpGetLoUint8x64(v)
	case ssaop.OpGreaterEqualFloat32x16:
		return rewriteValue_OpGreaterEqualFloat32x16(v)
	case ssaop.OpGreaterEqualFloat32x4:
		return rewriteValue_OpGreaterEqualFloat32x4(v)
	case ssaop.OpGreaterEqualFloat32x8:
		return rewriteValue_OpGreaterEqualFloat32x8(v)
	case ssaop.OpGreaterEqualFloat64x2:
		return rewriteValue_OpGreaterEqualFloat64x2(v)
	case ssaop.OpGreaterEqualFloat64x4:
		return rewriteValue_OpGreaterEqualFloat64x4(v)
	case ssaop.OpGreaterEqualFloat64x8:
		return rewriteValue_OpGreaterEqualFloat64x8(v)
	case ssaop.OpGreaterEqualInt16x32:
		return rewriteValue_OpGreaterEqualInt16x32(v)
	case ssaop.OpGreaterEqualInt32x16:
		return rewriteValue_OpGreaterEqualInt32x16(v)
	case ssaop.OpGreaterEqualInt64x8:
		return rewriteValue_OpGreaterEqualInt64x8(v)
	case ssaop.OpGreaterEqualInt8x64:
		return rewriteValue_OpGreaterEqualInt8x64(v)
	case ssaop.OpGreaterEqualUint16x32:
		return rewriteValue_OpGreaterEqualUint16x32(v)
	case ssaop.OpGreaterEqualUint32x16:
		return rewriteValue_OpGreaterEqualUint32x16(v)
	case ssaop.OpGreaterEqualUint64x8:
		return rewriteValue_OpGreaterEqualUint64x8(v)
	case ssaop.OpGreaterEqualUint8x64:
		return rewriteValue_OpGreaterEqualUint8x64(v)
	case ssaop.OpGreaterFloat32x16:
		return rewriteValue_OpGreaterFloat32x16(v)
	case ssaop.OpGreaterFloat32x4:
		return rewriteValue_OpGreaterFloat32x4(v)
	case ssaop.OpGreaterFloat32x8:
		return rewriteValue_OpGreaterFloat32x8(v)
	case ssaop.OpGreaterFloat64x2:
		return rewriteValue_OpGreaterFloat64x2(v)
	case ssaop.OpGreaterFloat64x4:
		return rewriteValue_OpGreaterFloat64x4(v)
	case ssaop.OpGreaterFloat64x8:
		return rewriteValue_OpGreaterFloat64x8(v)
	case ssaop.OpGreaterInt16x16:
		v.Op = ssaop.OpAMD64VPCMPGTW256
		return true
	case ssaop.OpGreaterInt16x32:
		return rewriteValue_OpGreaterInt16x32(v)
	case ssaop.OpGreaterInt16x8:
		v.Op = ssaop.OpAMD64VPCMPGTW128
		return true
	case ssaop.OpGreaterInt32x16:
		return rewriteValue_OpGreaterInt32x16(v)
	case ssaop.OpGreaterInt32x4:
		v.Op = ssaop.OpAMD64VPCMPGTD128
		return true
	case ssaop.OpGreaterInt32x8:
		v.Op = ssaop.OpAMD64VPCMPGTD256
		return true
	case ssaop.OpGreaterInt64x2:
		v.Op = ssaop.OpAMD64VPCMPGTQ128
		return true
	case ssaop.OpGreaterInt64x4:
		v.Op = ssaop.OpAMD64VPCMPGTQ256
		return true
	case ssaop.OpGreaterInt64x8:
		return rewriteValue_OpGreaterInt64x8(v)
	case ssaop.OpGreaterInt8x16:
		v.Op = ssaop.OpAMD64VPCMPGTB128
		return true
	case ssaop.OpGreaterInt8x32:
		v.Op = ssaop.OpAMD64VPCMPGTB256
		return true
	case ssaop.OpGreaterInt8x64:
		return rewriteValue_OpGreaterInt8x64(v)
	case ssaop.OpGreaterUint16x32:
		return rewriteValue_OpGreaterUint16x32(v)
	case ssaop.OpGreaterUint32x16:
		return rewriteValue_OpGreaterUint32x16(v)
	case ssaop.OpGreaterUint64x8:
		return rewriteValue_OpGreaterUint64x8(v)
	case ssaop.OpGreaterUint8x64:
		return rewriteValue_OpGreaterUint8x64(v)
	case ssaop.OpHasCPUFeature:
		return rewriteValue_OpHasCPUFeature(v)
	case ssaop.OpHmul32:
		v.Op = ssaop.OpAMD64HMULL
		return true
	case ssaop.OpHmul32u:
		v.Op = ssaop.OpAMD64HMULLU
		return true
	case ssaop.OpHmul64:
		v.Op = ssaop.OpAMD64HMULQ
		return true
	case ssaop.OpHmul64u:
		v.Op = ssaop.OpAMD64HMULQU
		return true
	case ssaop.OpInterCall:
		v.Op = ssaop.OpAMD64CALLinter
		return true
	case ssaop.OpInterleaveHiGroupedInt16x16:
		v.Op = ssaop.OpAMD64VPUNPCKHWD256
		return true
	case ssaop.OpInterleaveHiGroupedInt16x32:
		v.Op = ssaop.OpAMD64VPUNPCKHWD512
		return true
	case ssaop.OpInterleaveHiGroupedInt32x16:
		v.Op = ssaop.OpAMD64VPUNPCKHDQ512
		return true
	case ssaop.OpInterleaveHiGroupedInt32x8:
		v.Op = ssaop.OpAMD64VPUNPCKHDQ256
		return true
	case ssaop.OpInterleaveHiGroupedInt64x4:
		v.Op = ssaop.OpAMD64VPUNPCKHQDQ256
		return true
	case ssaop.OpInterleaveHiGroupedInt64x8:
		v.Op = ssaop.OpAMD64VPUNPCKHQDQ512
		return true
	case ssaop.OpInterleaveHiGroupedUint16x16:
		v.Op = ssaop.OpAMD64VPUNPCKHWD256
		return true
	case ssaop.OpInterleaveHiGroupedUint16x32:
		v.Op = ssaop.OpAMD64VPUNPCKHWD512
		return true
	case ssaop.OpInterleaveHiGroupedUint32x16:
		v.Op = ssaop.OpAMD64VPUNPCKHDQ512
		return true
	case ssaop.OpInterleaveHiGroupedUint32x8:
		v.Op = ssaop.OpAMD64VPUNPCKHDQ256
		return true
	case ssaop.OpInterleaveHiGroupedUint64x4:
		v.Op = ssaop.OpAMD64VPUNPCKHQDQ256
		return true
	case ssaop.OpInterleaveHiGroupedUint64x8:
		v.Op = ssaop.OpAMD64VPUNPCKHQDQ512
		return true
	case ssaop.OpInterleaveHiInt16x8:
		v.Op = ssaop.OpAMD64VPUNPCKHWD128
		return true
	case ssaop.OpInterleaveHiInt32x4:
		v.Op = ssaop.OpAMD64VPUNPCKHDQ128
		return true
	case ssaop.OpInterleaveHiInt64x2:
		v.Op = ssaop.OpAMD64VPUNPCKHQDQ128
		return true
	case ssaop.OpInterleaveHiUint16x8:
		v.Op = ssaop.OpAMD64VPUNPCKHWD128
		return true
	case ssaop.OpInterleaveHiUint32x4:
		v.Op = ssaop.OpAMD64VPUNPCKHDQ128
		return true
	case ssaop.OpInterleaveHiUint64x2:
		v.Op = ssaop.OpAMD64VPUNPCKHQDQ128
		return true
	case ssaop.OpInterleaveLoGroupedInt16x16:
		v.Op = ssaop.OpAMD64VPUNPCKLWD256
		return true
	case ssaop.OpInterleaveLoGroupedInt16x32:
		v.Op = ssaop.OpAMD64VPUNPCKLWD512
		return true
	case ssaop.OpInterleaveLoGroupedInt32x16:
		v.Op = ssaop.OpAMD64VPUNPCKLDQ512
		return true
	case ssaop.OpInterleaveLoGroupedInt32x8:
		v.Op = ssaop.OpAMD64VPUNPCKLDQ256
		return true
	case ssaop.OpInterleaveLoGroupedInt64x4:
		v.Op = ssaop.OpAMD64VPUNPCKLQDQ256
		return true
	case ssaop.OpInterleaveLoGroupedInt64x8:
		v.Op = ssaop.OpAMD64VPUNPCKLQDQ512
		return true
	case ssaop.OpInterleaveLoGroupedUint16x16:
		v.Op = ssaop.OpAMD64VPUNPCKLWD256
		return true
	case ssaop.OpInterleaveLoGroupedUint16x32:
		v.Op = ssaop.OpAMD64VPUNPCKLWD512
		return true
	case ssaop.OpInterleaveLoGroupedUint32x16:
		v.Op = ssaop.OpAMD64VPUNPCKLDQ512
		return true
	case ssaop.OpInterleaveLoGroupedUint32x8:
		v.Op = ssaop.OpAMD64VPUNPCKLDQ256
		return true
	case ssaop.OpInterleaveLoGroupedUint64x4:
		v.Op = ssaop.OpAMD64VPUNPCKLQDQ256
		return true
	case ssaop.OpInterleaveLoGroupedUint64x8:
		v.Op = ssaop.OpAMD64VPUNPCKLQDQ512
		return true
	case ssaop.OpInterleaveLoInt16x8:
		v.Op = ssaop.OpAMD64VPUNPCKLWD128
		return true
	case ssaop.OpInterleaveLoInt32x4:
		v.Op = ssaop.OpAMD64VPUNPCKLDQ128
		return true
	case ssaop.OpInterleaveLoInt64x2:
		v.Op = ssaop.OpAMD64VPUNPCKLQDQ128
		return true
	case ssaop.OpInterleaveLoUint16x8:
		v.Op = ssaop.OpAMD64VPUNPCKLWD128
		return true
	case ssaop.OpInterleaveLoUint32x4:
		v.Op = ssaop.OpAMD64VPUNPCKLDQ128
		return true
	case ssaop.OpInterleaveLoUint64x2:
		v.Op = ssaop.OpAMD64VPUNPCKLQDQ128
		return true
	case ssaop.OpIsInBounds:
		return rewriteValue_OpIsInBounds(v)
	case ssaop.OpIsNaNFloat32x16:
		return rewriteValue_OpIsNaNFloat32x16(v)
	case ssaop.OpIsNaNFloat32x4:
		return rewriteValue_OpIsNaNFloat32x4(v)
	case ssaop.OpIsNaNFloat32x8:
		return rewriteValue_OpIsNaNFloat32x8(v)
	case ssaop.OpIsNaNFloat64x2:
		return rewriteValue_OpIsNaNFloat64x2(v)
	case ssaop.OpIsNaNFloat64x4:
		return rewriteValue_OpIsNaNFloat64x4(v)
	case ssaop.OpIsNaNFloat64x8:
		return rewriteValue_OpIsNaNFloat64x8(v)
	case ssaop.OpIsNonNil:
		return rewriteValue_OpIsNonNil(v)
	case ssaop.OpIsSliceInBounds:
		return rewriteValue_OpIsSliceInBounds(v)
	case ssaop.OpIsZeroVec:
		return rewriteValue_OpIsZeroVec(v)
	case ssaop.OpLeadingZerosInt32x16:
		v.Op = ssaop.OpAMD64VPLZCNTD512
		return true
	case ssaop.OpLeadingZerosInt32x4:
		v.Op = ssaop.OpAMD64VPLZCNTD128
		return true
	case ssaop.OpLeadingZerosInt32x8:
		v.Op = ssaop.OpAMD64VPLZCNTD256
		return true
	case ssaop.OpLeadingZerosInt64x2:
		v.Op = ssaop.OpAMD64VPLZCNTQ128
		return true
	case ssaop.OpLeadingZerosInt64x4:
		v.Op = ssaop.OpAMD64VPLZCNTQ256
		return true
	case ssaop.OpLeadingZerosInt64x8:
		v.Op = ssaop.OpAMD64VPLZCNTQ512
		return true
	case ssaop.OpLeadingZerosUint32x16:
		v.Op = ssaop.OpAMD64VPLZCNTD512
		return true
	case ssaop.OpLeadingZerosUint32x4:
		v.Op = ssaop.OpAMD64VPLZCNTD128
		return true
	case ssaop.OpLeadingZerosUint32x8:
		v.Op = ssaop.OpAMD64VPLZCNTD256
		return true
	case ssaop.OpLeadingZerosUint64x2:
		v.Op = ssaop.OpAMD64VPLZCNTQ128
		return true
	case ssaop.OpLeadingZerosUint64x4:
		v.Op = ssaop.OpAMD64VPLZCNTQ256
		return true
	case ssaop.OpLeadingZerosUint64x8:
		v.Op = ssaop.OpAMD64VPLZCNTQ512
		return true
	case ssaop.OpLeq16:
		return rewriteValue_OpLeq16(v)
	case ssaop.OpLeq16U:
		return rewriteValue_OpLeq16U(v)
	case ssaop.OpLeq32:
		return rewriteValue_OpLeq32(v)
	case ssaop.OpLeq32F:
		return rewriteValue_OpLeq32F(v)
	case ssaop.OpLeq32U:
		return rewriteValue_OpLeq32U(v)
	case ssaop.OpLeq64:
		return rewriteValue_OpLeq64(v)
	case ssaop.OpLeq64F:
		return rewriteValue_OpLeq64F(v)
	case ssaop.OpLeq64U:
		return rewriteValue_OpLeq64U(v)
	case ssaop.OpLeq8:
		return rewriteValue_OpLeq8(v)
	case ssaop.OpLeq8U:
		return rewriteValue_OpLeq8U(v)
	case ssaop.OpLess16:
		return rewriteValue_OpLess16(v)
	case ssaop.OpLess16U:
		return rewriteValue_OpLess16U(v)
	case ssaop.OpLess32:
		return rewriteValue_OpLess32(v)
	case ssaop.OpLess32F:
		return rewriteValue_OpLess32F(v)
	case ssaop.OpLess32U:
		return rewriteValue_OpLess32U(v)
	case ssaop.OpLess64:
		return rewriteValue_OpLess64(v)
	case ssaop.OpLess64F:
		return rewriteValue_OpLess64F(v)
	case ssaop.OpLess64U:
		return rewriteValue_OpLess64U(v)
	case ssaop.OpLess8:
		return rewriteValue_OpLess8(v)
	case ssaop.OpLess8U:
		return rewriteValue_OpLess8U(v)
	case ssaop.OpLessEqualFloat32x16:
		return rewriteValue_OpLessEqualFloat32x16(v)
	case ssaop.OpLessEqualFloat32x4:
		return rewriteValue_OpLessEqualFloat32x4(v)
	case ssaop.OpLessEqualFloat32x8:
		return rewriteValue_OpLessEqualFloat32x8(v)
	case ssaop.OpLessEqualFloat64x2:
		return rewriteValue_OpLessEqualFloat64x2(v)
	case ssaop.OpLessEqualFloat64x4:
		return rewriteValue_OpLessEqualFloat64x4(v)
	case ssaop.OpLessEqualFloat64x8:
		return rewriteValue_OpLessEqualFloat64x8(v)
	case ssaop.OpLessEqualInt16x32:
		return rewriteValue_OpLessEqualInt16x32(v)
	case ssaop.OpLessEqualInt32x16:
		return rewriteValue_OpLessEqualInt32x16(v)
	case ssaop.OpLessEqualInt64x8:
		return rewriteValue_OpLessEqualInt64x8(v)
	case ssaop.OpLessEqualInt8x64:
		return rewriteValue_OpLessEqualInt8x64(v)
	case ssaop.OpLessEqualUint16x32:
		return rewriteValue_OpLessEqualUint16x32(v)
	case ssaop.OpLessEqualUint32x16:
		return rewriteValue_OpLessEqualUint32x16(v)
	case ssaop.OpLessEqualUint64x8:
		return rewriteValue_OpLessEqualUint64x8(v)
	case ssaop.OpLessEqualUint8x64:
		return rewriteValue_OpLessEqualUint8x64(v)
	case ssaop.OpLessFloat32x16:
		return rewriteValue_OpLessFloat32x16(v)
	case ssaop.OpLessFloat32x4:
		return rewriteValue_OpLessFloat32x4(v)
	case ssaop.OpLessFloat32x8:
		return rewriteValue_OpLessFloat32x8(v)
	case ssaop.OpLessFloat64x2:
		return rewriteValue_OpLessFloat64x2(v)
	case ssaop.OpLessFloat64x4:
		return rewriteValue_OpLessFloat64x4(v)
	case ssaop.OpLessFloat64x8:
		return rewriteValue_OpLessFloat64x8(v)
	case ssaop.OpLessInt16x32:
		return rewriteValue_OpLessInt16x32(v)
	case ssaop.OpLessInt32x16:
		return rewriteValue_OpLessInt32x16(v)
	case ssaop.OpLessInt64x8:
		return rewriteValue_OpLessInt64x8(v)
	case ssaop.OpLessInt8x64:
		return rewriteValue_OpLessInt8x64(v)
	case ssaop.OpLessUint16x32:
		return rewriteValue_OpLessUint16x32(v)
	case ssaop.OpLessUint32x16:
		return rewriteValue_OpLessUint32x16(v)
	case ssaop.OpLessUint64x8:
		return rewriteValue_OpLessUint64x8(v)
	case ssaop.OpLessUint8x64:
		return rewriteValue_OpLessUint8x64(v)
	case ssaop.OpLoad:
		return rewriteValue_OpLoad(v)
	case ssaop.OpLoadMasked16:
		return rewriteValue_OpLoadMasked16(v)
	case ssaop.OpLoadMasked32:
		return rewriteValue_OpLoadMasked32(v)
	case ssaop.OpLoadMasked64:
		return rewriteValue_OpLoadMasked64(v)
	case ssaop.OpLoadMasked8:
		return rewriteValue_OpLoadMasked8(v)
	case ssaop.OpLocalAddr:
		return rewriteValue_OpLocalAddr(v)
	case ssaop.OpLsh16x16:
		return rewriteValue_OpLsh16x16(v)
	case ssaop.OpLsh16x32:
		return rewriteValue_OpLsh16x32(v)
	case ssaop.OpLsh16x64:
		return rewriteValue_OpLsh16x64(v)
	case ssaop.OpLsh16x8:
		return rewriteValue_OpLsh16x8(v)
	case ssaop.OpLsh32x16:
		return rewriteValue_OpLsh32x16(v)
	case ssaop.OpLsh32x32:
		return rewriteValue_OpLsh32x32(v)
	case ssaop.OpLsh32x64:
		return rewriteValue_OpLsh32x64(v)
	case ssaop.OpLsh32x8:
		return rewriteValue_OpLsh32x8(v)
	case ssaop.OpLsh64x16:
		return rewriteValue_OpLsh64x16(v)
	case ssaop.OpLsh64x32:
		return rewriteValue_OpLsh64x32(v)
	case ssaop.OpLsh64x64:
		return rewriteValue_OpLsh64x64(v)
	case ssaop.OpLsh64x8:
		return rewriteValue_OpLsh64x8(v)
	case ssaop.OpLsh8x16:
		return rewriteValue_OpLsh8x16(v)
	case ssaop.OpLsh8x32:
		return rewriteValue_OpLsh8x32(v)
	case ssaop.OpLsh8x64:
		return rewriteValue_OpLsh8x64(v)
	case ssaop.OpLsh8x8:
		return rewriteValue_OpLsh8x8(v)
	case ssaop.OpMax32F:
		return rewriteValue_OpMax32F(v)
	case ssaop.OpMax32FSel:
		v.Op = ssaop.OpAMD64MAXSS
		return true
	case ssaop.OpMax64F:
		return rewriteValue_OpMax64F(v)
	case ssaop.OpMax64FSel:
		v.Op = ssaop.OpAMD64MAXSD
		return true
	case ssaop.OpMaxFloat32x16:
		v.Op = ssaop.OpAMD64VMAXPS512
		return true
	case ssaop.OpMaxFloat32x4:
		v.Op = ssaop.OpAMD64VMAXPS128
		return true
	case ssaop.OpMaxFloat32x8:
		v.Op = ssaop.OpAMD64VMAXPS256
		return true
	case ssaop.OpMaxFloat64x2:
		v.Op = ssaop.OpAMD64VMAXPD128
		return true
	case ssaop.OpMaxFloat64x4:
		v.Op = ssaop.OpAMD64VMAXPD256
		return true
	case ssaop.OpMaxFloat64x8:
		v.Op = ssaop.OpAMD64VMAXPD512
		return true
	case ssaop.OpMaxInt16x16:
		v.Op = ssaop.OpAMD64VPMAXSW256
		return true
	case ssaop.OpMaxInt16x32:
		v.Op = ssaop.OpAMD64VPMAXSW512
		return true
	case ssaop.OpMaxInt16x8:
		v.Op = ssaop.OpAMD64VPMAXSW128
		return true
	case ssaop.OpMaxInt32x16:
		v.Op = ssaop.OpAMD64VPMAXSD512
		return true
	case ssaop.OpMaxInt32x4:
		v.Op = ssaop.OpAMD64VPMAXSD128
		return true
	case ssaop.OpMaxInt32x8:
		v.Op = ssaop.OpAMD64VPMAXSD256
		return true
	case ssaop.OpMaxInt64x2:
		v.Op = ssaop.OpAMD64VPMAXSQ128
		return true
	case ssaop.OpMaxInt64x4:
		v.Op = ssaop.OpAMD64VPMAXSQ256
		return true
	case ssaop.OpMaxInt64x8:
		v.Op = ssaop.OpAMD64VPMAXSQ512
		return true
	case ssaop.OpMaxInt8x16:
		v.Op = ssaop.OpAMD64VPMAXSB128
		return true
	case ssaop.OpMaxInt8x32:
		v.Op = ssaop.OpAMD64VPMAXSB256
		return true
	case ssaop.OpMaxInt8x64:
		v.Op = ssaop.OpAMD64VPMAXSB512
		return true
	case ssaop.OpMaxUint16x16:
		v.Op = ssaop.OpAMD64VPMAXUW256
		return true
	case ssaop.OpMaxUint16x32:
		v.Op = ssaop.OpAMD64VPMAXUW512
		return true
	case ssaop.OpMaxUint16x8:
		v.Op = ssaop.OpAMD64VPMAXUW128
		return true
	case ssaop.OpMaxUint32x16:
		v.Op = ssaop.OpAMD64VPMAXUD512
		return true
	case ssaop.OpMaxUint32x4:
		v.Op = ssaop.OpAMD64VPMAXUD128
		return true
	case ssaop.OpMaxUint32x8:
		v.Op = ssaop.OpAMD64VPMAXUD256
		return true
	case ssaop.OpMaxUint64x2:
		v.Op = ssaop.OpAMD64VPMAXUQ128
		return true
	case ssaop.OpMaxUint64x4:
		v.Op = ssaop.OpAMD64VPMAXUQ256
		return true
	case ssaop.OpMaxUint64x8:
		v.Op = ssaop.OpAMD64VPMAXUQ512
		return true
	case ssaop.OpMaxUint8x16:
		v.Op = ssaop.OpAMD64VPMAXUB128
		return true
	case ssaop.OpMaxUint8x32:
		v.Op = ssaop.OpAMD64VPMAXUB256
		return true
	case ssaop.OpMaxUint8x64:
		v.Op = ssaop.OpAMD64VPMAXUB512
		return true
	case ssaop.OpMin32F:
		return rewriteValue_OpMin32F(v)
	case ssaop.OpMin32FSel:
		v.Op = ssaop.OpAMD64MINSS
		return true
	case ssaop.OpMin64F:
		return rewriteValue_OpMin64F(v)
	case ssaop.OpMin64FSel:
		v.Op = ssaop.OpAMD64MINSD
		return true
	case ssaop.OpMinFloat32x16:
		v.Op = ssaop.OpAMD64VMINPS512
		return true
	case ssaop.OpMinFloat32x4:
		v.Op = ssaop.OpAMD64VMINPS128
		return true
	case ssaop.OpMinFloat32x8:
		v.Op = ssaop.OpAMD64VMINPS256
		return true
	case ssaop.OpMinFloat64x2:
		v.Op = ssaop.OpAMD64VMINPD128
		return true
	case ssaop.OpMinFloat64x4:
		v.Op = ssaop.OpAMD64VMINPD256
		return true
	case ssaop.OpMinFloat64x8:
		v.Op = ssaop.OpAMD64VMINPD512
		return true
	case ssaop.OpMinInt16x16:
		v.Op = ssaop.OpAMD64VPMINSW256
		return true
	case ssaop.OpMinInt16x32:
		v.Op = ssaop.OpAMD64VPMINSW512
		return true
	case ssaop.OpMinInt16x8:
		v.Op = ssaop.OpAMD64VPMINSW128
		return true
	case ssaop.OpMinInt32x16:
		v.Op = ssaop.OpAMD64VPMINSD512
		return true
	case ssaop.OpMinInt32x4:
		v.Op = ssaop.OpAMD64VPMINSD128
		return true
	case ssaop.OpMinInt32x8:
		v.Op = ssaop.OpAMD64VPMINSD256
		return true
	case ssaop.OpMinInt64x2:
		v.Op = ssaop.OpAMD64VPMINSQ128
		return true
	case ssaop.OpMinInt64x4:
		v.Op = ssaop.OpAMD64VPMINSQ256
		return true
	case ssaop.OpMinInt64x8:
		v.Op = ssaop.OpAMD64VPMINSQ512
		return true
	case ssaop.OpMinInt8x16:
		v.Op = ssaop.OpAMD64VPMINSB128
		return true
	case ssaop.OpMinInt8x32:
		v.Op = ssaop.OpAMD64VPMINSB256
		return true
	case ssaop.OpMinInt8x64:
		v.Op = ssaop.OpAMD64VPMINSB512
		return true
	case ssaop.OpMinUint16x16:
		v.Op = ssaop.OpAMD64VPMINUW256
		return true
	case ssaop.OpMinUint16x32:
		v.Op = ssaop.OpAMD64VPMINUW512
		return true
	case ssaop.OpMinUint16x8:
		v.Op = ssaop.OpAMD64VPMINUW128
		return true
	case ssaop.OpMinUint32x16:
		v.Op = ssaop.OpAMD64VPMINUD512
		return true
	case ssaop.OpMinUint32x4:
		v.Op = ssaop.OpAMD64VPMINUD128
		return true
	case ssaop.OpMinUint32x8:
		v.Op = ssaop.OpAMD64VPMINUD256
		return true
	case ssaop.OpMinUint64x2:
		v.Op = ssaop.OpAMD64VPMINUQ128
		return true
	case ssaop.OpMinUint64x4:
		v.Op = ssaop.OpAMD64VPMINUQ256
		return true
	case ssaop.OpMinUint64x8:
		v.Op = ssaop.OpAMD64VPMINUQ512
		return true
	case ssaop.OpMinUint8x16:
		v.Op = ssaop.OpAMD64VPMINUB128
		return true
	case ssaop.OpMinUint8x32:
		v.Op = ssaop.OpAMD64VPMINUB256
		return true
	case ssaop.OpMinUint8x64:
		v.Op = ssaop.OpAMD64VPMINUB512
		return true
	case ssaop.OpMod16:
		return rewriteValue_OpMod16(v)
	case ssaop.OpMod16u:
		return rewriteValue_OpMod16u(v)
	case ssaop.OpMod32:
		return rewriteValue_OpMod32(v)
	case ssaop.OpMod32u:
		return rewriteValue_OpMod32u(v)
	case ssaop.OpMod64:
		return rewriteValue_OpMod64(v)
	case ssaop.OpMod64u:
		return rewriteValue_OpMod64u(v)
	case ssaop.OpMod8:
		return rewriteValue_OpMod8(v)
	case ssaop.OpMod8u:
		return rewriteValue_OpMod8u(v)
	case ssaop.OpMove:
		return rewriteValue_OpMove(v)
	case ssaop.OpMul16:
		v.Op = ssaop.OpAMD64MULL
		return true
	case ssaop.OpMul32:
		v.Op = ssaop.OpAMD64MULL
		return true
	case ssaop.OpMul32F:
		v.Op = ssaop.OpAMD64MULSS
		return true
	case ssaop.OpMul64:
		v.Op = ssaop.OpAMD64MULQ
		return true
	case ssaop.OpMul64F:
		v.Op = ssaop.OpAMD64MULSD
		return true
	case ssaop.OpMul64uhilo:
		return rewriteValue_OpMul64uhilo(v)
	case ssaop.OpMul8:
		v.Op = ssaop.OpAMD64MULL
		return true
	case ssaop.OpMulAddEvenSubOddFloat32x16:
		v.Op = ssaop.OpAMD64VFMADDSUB213PS512
		return true
	case ssaop.OpMulAddEvenSubOddFloat32x4:
		v.Op = ssaop.OpAMD64VFMADDSUB213PS128
		return true
	case ssaop.OpMulAddEvenSubOddFloat32x8:
		v.Op = ssaop.OpAMD64VFMADDSUB213PS256
		return true
	case ssaop.OpMulAddEvenSubOddFloat64x2:
		v.Op = ssaop.OpAMD64VFMADDSUB213PD128
		return true
	case ssaop.OpMulAddEvenSubOddFloat64x4:
		v.Op = ssaop.OpAMD64VFMADDSUB213PD256
		return true
	case ssaop.OpMulAddEvenSubOddFloat64x8:
		v.Op = ssaop.OpAMD64VFMADDSUB213PD512
		return true
	case ssaop.OpMulAddFloat32x16:
		v.Op = ssaop.OpAMD64VFMADD213PS512
		return true
	case ssaop.OpMulAddFloat32x4:
		v.Op = ssaop.OpAMD64VFMADD213PS128
		return true
	case ssaop.OpMulAddFloat32x8:
		v.Op = ssaop.OpAMD64VFMADD213PS256
		return true
	case ssaop.OpMulAddFloat64x2:
		v.Op = ssaop.OpAMD64VFMADD213PD128
		return true
	case ssaop.OpMulAddFloat64x4:
		v.Op = ssaop.OpAMD64VFMADD213PD256
		return true
	case ssaop.OpMulAddFloat64x8:
		v.Op = ssaop.OpAMD64VFMADD213PD512
		return true
	case ssaop.OpMulAddOddSubEvenFloat32x16:
		v.Op = ssaop.OpAMD64VFMSUBADD213PS512
		return true
	case ssaop.OpMulAddOddSubEvenFloat32x4:
		v.Op = ssaop.OpAMD64VFMSUBADD213PS128
		return true
	case ssaop.OpMulAddOddSubEvenFloat32x8:
		v.Op = ssaop.OpAMD64VFMSUBADD213PS256
		return true
	case ssaop.OpMulAddOddSubEvenFloat64x2:
		v.Op = ssaop.OpAMD64VFMSUBADD213PD128
		return true
	case ssaop.OpMulAddOddSubEvenFloat64x4:
		v.Op = ssaop.OpAMD64VFMSUBADD213PD256
		return true
	case ssaop.OpMulAddOddSubEvenFloat64x8:
		v.Op = ssaop.OpAMD64VFMSUBADD213PD512
		return true
	case ssaop.OpMulFloat32x16:
		v.Op = ssaop.OpAMD64VMULPS512
		return true
	case ssaop.OpMulFloat32x4:
		v.Op = ssaop.OpAMD64VMULPS128
		return true
	case ssaop.OpMulFloat32x8:
		v.Op = ssaop.OpAMD64VMULPS256
		return true
	case ssaop.OpMulFloat64x2:
		v.Op = ssaop.OpAMD64VMULPD128
		return true
	case ssaop.OpMulFloat64x4:
		v.Op = ssaop.OpAMD64VMULPD256
		return true
	case ssaop.OpMulFloat64x8:
		v.Op = ssaop.OpAMD64VMULPD512
		return true
	case ssaop.OpMulHighInt16x16:
		v.Op = ssaop.OpAMD64VPMULHW256
		return true
	case ssaop.OpMulHighInt16x32:
		v.Op = ssaop.OpAMD64VPMULHW512
		return true
	case ssaop.OpMulHighInt16x8:
		v.Op = ssaop.OpAMD64VPMULHW128
		return true
	case ssaop.OpMulHighUint16x16:
		v.Op = ssaop.OpAMD64VPMULHUW256
		return true
	case ssaop.OpMulHighUint16x32:
		v.Op = ssaop.OpAMD64VPMULHUW512
		return true
	case ssaop.OpMulHighUint16x8:
		v.Op = ssaop.OpAMD64VPMULHUW128
		return true
	case ssaop.OpMulInt16x16:
		v.Op = ssaop.OpAMD64VPMULLW256
		return true
	case ssaop.OpMulInt16x32:
		v.Op = ssaop.OpAMD64VPMULLW512
		return true
	case ssaop.OpMulInt16x8:
		v.Op = ssaop.OpAMD64VPMULLW128
		return true
	case ssaop.OpMulInt32x16:
		v.Op = ssaop.OpAMD64VPMULLD512
		return true
	case ssaop.OpMulInt32x4:
		v.Op = ssaop.OpAMD64VPMULLD128
		return true
	case ssaop.OpMulInt32x8:
		v.Op = ssaop.OpAMD64VPMULLD256
		return true
	case ssaop.OpMulInt64x2:
		v.Op = ssaop.OpAMD64VPMULLQ128
		return true
	case ssaop.OpMulInt64x4:
		v.Op = ssaop.OpAMD64VPMULLQ256
		return true
	case ssaop.OpMulInt64x8:
		v.Op = ssaop.OpAMD64VPMULLQ512
		return true
	case ssaop.OpMulSignInt16x16:
		v.Op = ssaop.OpAMD64VPSIGNW256
		return true
	case ssaop.OpMulSignInt16x8:
		v.Op = ssaop.OpAMD64VPSIGNW128
		return true
	case ssaop.OpMulSignInt32x4:
		v.Op = ssaop.OpAMD64VPSIGND128
		return true
	case ssaop.OpMulSignInt32x8:
		v.Op = ssaop.OpAMD64VPSIGND256
		return true
	case ssaop.OpMulSignInt8x16:
		v.Op = ssaop.OpAMD64VPSIGNB128
		return true
	case ssaop.OpMulSignInt8x32:
		v.Op = ssaop.OpAMD64VPSIGNB256
		return true
	case ssaop.OpMulUint16x16:
		v.Op = ssaop.OpAMD64VPMULLW256
		return true
	case ssaop.OpMulUint16x32:
		v.Op = ssaop.OpAMD64VPMULLW512
		return true
	case ssaop.OpMulUint16x8:
		v.Op = ssaop.OpAMD64VPMULLW128
		return true
	case ssaop.OpMulUint32x16:
		v.Op = ssaop.OpAMD64VPMULLD512
		return true
	case ssaop.OpMulUint32x4:
		v.Op = ssaop.OpAMD64VPMULLD128
		return true
	case ssaop.OpMulUint32x8:
		v.Op = ssaop.OpAMD64VPMULLD256
		return true
	case ssaop.OpMulUint64x2:
		v.Op = ssaop.OpAMD64VPMULLQ128
		return true
	case ssaop.OpMulUint64x4:
		v.Op = ssaop.OpAMD64VPMULLQ256
		return true
	case ssaop.OpMulUint64x8:
		v.Op = ssaop.OpAMD64VPMULLQ512
		return true
	case ssaop.OpMulWidenEvenInt32x4:
		v.Op = ssaop.OpAMD64VPMULDQ128
		return true
	case ssaop.OpMulWidenEvenInt32x8:
		v.Op = ssaop.OpAMD64VPMULDQ256
		return true
	case ssaop.OpMulWidenEvenUint32x4:
		v.Op = ssaop.OpAMD64VPMULUDQ128
		return true
	case ssaop.OpMulWidenEvenUint32x8:
		v.Op = ssaop.OpAMD64VPMULUDQ256
		return true
	case ssaop.OpNeg16:
		v.Op = ssaop.OpAMD64NEGL
		return true
	case ssaop.OpNeg32:
		v.Op = ssaop.OpAMD64NEGL
		return true
	case ssaop.OpNeg32F:
		return rewriteValue_OpNeg32F(v)
	case ssaop.OpNeg64:
		v.Op = ssaop.OpAMD64NEGQ
		return true
	case ssaop.OpNeg64F:
		return rewriteValue_OpNeg64F(v)
	case ssaop.OpNeg8:
		v.Op = ssaop.OpAMD64NEGL
		return true
	case ssaop.OpNeq16:
		return rewriteValue_OpNeq16(v)
	case ssaop.OpNeq32:
		return rewriteValue_OpNeq32(v)
	case ssaop.OpNeq32F:
		return rewriteValue_OpNeq32F(v)
	case ssaop.OpNeq64:
		return rewriteValue_OpNeq64(v)
	case ssaop.OpNeq64F:
		return rewriteValue_OpNeq64F(v)
	case ssaop.OpNeq8:
		return rewriteValue_OpNeq8(v)
	case ssaop.OpNeqB:
		return rewriteValue_OpNeqB(v)
	case ssaop.OpNeqPtr:
		return rewriteValue_OpNeqPtr(v)
	case ssaop.OpNilCheck:
		v.Op = ssaop.OpAMD64LoweredNilCheck
		return true
	case ssaop.OpNot:
		return rewriteValue_OpNot(v)
	case ssaop.OpNotEqualFloat32x16:
		return rewriteValue_OpNotEqualFloat32x16(v)
	case ssaop.OpNotEqualFloat32x4:
		return rewriteValue_OpNotEqualFloat32x4(v)
	case ssaop.OpNotEqualFloat32x8:
		return rewriteValue_OpNotEqualFloat32x8(v)
	case ssaop.OpNotEqualFloat64x2:
		return rewriteValue_OpNotEqualFloat64x2(v)
	case ssaop.OpNotEqualFloat64x4:
		return rewriteValue_OpNotEqualFloat64x4(v)
	case ssaop.OpNotEqualFloat64x8:
		return rewriteValue_OpNotEqualFloat64x8(v)
	case ssaop.OpNotEqualInt16x32:
		return rewriteValue_OpNotEqualInt16x32(v)
	case ssaop.OpNotEqualInt32x16:
		return rewriteValue_OpNotEqualInt32x16(v)
	case ssaop.OpNotEqualInt64x8:
		return rewriteValue_OpNotEqualInt64x8(v)
	case ssaop.OpNotEqualInt8x64:
		return rewriteValue_OpNotEqualInt8x64(v)
	case ssaop.OpNotEqualUint16x32:
		return rewriteValue_OpNotEqualUint16x32(v)
	case ssaop.OpNotEqualUint32x16:
		return rewriteValue_OpNotEqualUint32x16(v)
	case ssaop.OpNotEqualUint64x8:
		return rewriteValue_OpNotEqualUint64x8(v)
	case ssaop.OpNotEqualUint8x64:
		return rewriteValue_OpNotEqualUint8x64(v)
	case ssaop.OpOffPtr:
		return rewriteValue_OpOffPtr(v)
	case ssaop.OpOnesCountInt16x16:
		v.Op = ssaop.OpAMD64VPOPCNTW256
		return true
	case ssaop.OpOnesCountInt16x32:
		v.Op = ssaop.OpAMD64VPOPCNTW512
		return true
	case ssaop.OpOnesCountInt16x8:
		v.Op = ssaop.OpAMD64VPOPCNTW128
		return true
	case ssaop.OpOnesCountInt32x16:
		v.Op = ssaop.OpAMD64VPOPCNTD512
		return true
	case ssaop.OpOnesCountInt32x4:
		v.Op = ssaop.OpAMD64VPOPCNTD128
		return true
	case ssaop.OpOnesCountInt32x8:
		v.Op = ssaop.OpAMD64VPOPCNTD256
		return true
	case ssaop.OpOnesCountInt64x2:
		v.Op = ssaop.OpAMD64VPOPCNTQ128
		return true
	case ssaop.OpOnesCountInt64x4:
		v.Op = ssaop.OpAMD64VPOPCNTQ256
		return true
	case ssaop.OpOnesCountInt64x8:
		v.Op = ssaop.OpAMD64VPOPCNTQ512
		return true
	case ssaop.OpOnesCountInt8x16:
		v.Op = ssaop.OpAMD64VPOPCNTB128
		return true
	case ssaop.OpOnesCountInt8x32:
		v.Op = ssaop.OpAMD64VPOPCNTB256
		return true
	case ssaop.OpOnesCountInt8x64:
		v.Op = ssaop.OpAMD64VPOPCNTB512
		return true
	case ssaop.OpOnesCountUint16x16:
		v.Op = ssaop.OpAMD64VPOPCNTW256
		return true
	case ssaop.OpOnesCountUint16x32:
		v.Op = ssaop.OpAMD64VPOPCNTW512
		return true
	case ssaop.OpOnesCountUint16x8:
		v.Op = ssaop.OpAMD64VPOPCNTW128
		return true
	case ssaop.OpOnesCountUint32x16:
		v.Op = ssaop.OpAMD64VPOPCNTD512
		return true
	case ssaop.OpOnesCountUint32x4:
		v.Op = ssaop.OpAMD64VPOPCNTD128
		return true
	case ssaop.OpOnesCountUint32x8:
		v.Op = ssaop.OpAMD64VPOPCNTD256
		return true
	case ssaop.OpOnesCountUint64x2:
		v.Op = ssaop.OpAMD64VPOPCNTQ128
		return true
	case ssaop.OpOnesCountUint64x4:
		v.Op = ssaop.OpAMD64VPOPCNTQ256
		return true
	case ssaop.OpOnesCountUint64x8:
		v.Op = ssaop.OpAMD64VPOPCNTQ512
		return true
	case ssaop.OpOnesCountUint8x16:
		v.Op = ssaop.OpAMD64VPOPCNTB128
		return true
	case ssaop.OpOnesCountUint8x32:
		v.Op = ssaop.OpAMD64VPOPCNTB256
		return true
	case ssaop.OpOnesCountUint8x64:
		v.Op = ssaop.OpAMD64VPOPCNTB512
		return true
	case ssaop.OpOr16:
		v.Op = ssaop.OpAMD64ORL
		return true
	case ssaop.OpOr32:
		v.Op = ssaop.OpAMD64ORL
		return true
	case ssaop.OpOr64:
		v.Op = ssaop.OpAMD64ORQ
		return true
	case ssaop.OpOr8:
		v.Op = ssaop.OpAMD64ORL
		return true
	case ssaop.OpOrB:
		v.Op = ssaop.OpAMD64ORL
		return true
	case ssaop.OpOrInt16x16:
		v.Op = ssaop.OpAMD64VPOR256
		return true
	case ssaop.OpOrInt16x32:
		v.Op = ssaop.OpAMD64VPORD512
		return true
	case ssaop.OpOrInt16x8:
		v.Op = ssaop.OpAMD64VPOR128
		return true
	case ssaop.OpOrInt32x16:
		v.Op = ssaop.OpAMD64VPORD512
		return true
	case ssaop.OpOrInt32x4:
		v.Op = ssaop.OpAMD64VPOR128
		return true
	case ssaop.OpOrInt32x8:
		v.Op = ssaop.OpAMD64VPOR256
		return true
	case ssaop.OpOrInt64x2:
		v.Op = ssaop.OpAMD64VPOR128
		return true
	case ssaop.OpOrInt64x4:
		v.Op = ssaop.OpAMD64VPOR256
		return true
	case ssaop.OpOrInt64x8:
		v.Op = ssaop.OpAMD64VPORQ512
		return true
	case ssaop.OpOrInt8x16:
		v.Op = ssaop.OpAMD64VPOR128
		return true
	case ssaop.OpOrInt8x32:
		v.Op = ssaop.OpAMD64VPOR256
		return true
	case ssaop.OpOrInt8x64:
		v.Op = ssaop.OpAMD64VPORD512
		return true
	case ssaop.OpOrUint16x16:
		v.Op = ssaop.OpAMD64VPOR256
		return true
	case ssaop.OpOrUint16x32:
		v.Op = ssaop.OpAMD64VPORD512
		return true
	case ssaop.OpOrUint16x8:
		v.Op = ssaop.OpAMD64VPOR128
		return true
	case ssaop.OpOrUint32x16:
		v.Op = ssaop.OpAMD64VPORD512
		return true
	case ssaop.OpOrUint32x4:
		v.Op = ssaop.OpAMD64VPOR128
		return true
	case ssaop.OpOrUint32x8:
		v.Op = ssaop.OpAMD64VPOR256
		return true
	case ssaop.OpOrUint64x2:
		v.Op = ssaop.OpAMD64VPOR128
		return true
	case ssaop.OpOrUint64x4:
		v.Op = ssaop.OpAMD64VPOR256
		return true
	case ssaop.OpOrUint64x8:
		v.Op = ssaop.OpAMD64VPORQ512
		return true
	case ssaop.OpOrUint8x16:
		v.Op = ssaop.OpAMD64VPOR128
		return true
	case ssaop.OpOrUint8x32:
		v.Op = ssaop.OpAMD64VPOR256
		return true
	case ssaop.OpOrUint8x64:
		v.Op = ssaop.OpAMD64VPORD512
		return true
	case ssaop.OpPanicBounds:
		v.Op = ssaop.OpAMD64LoweredPanicBoundsRR
		return true
	case ssaop.OpPermuteFloat32x16:
		v.Op = ssaop.OpAMD64VPERMPS512
		return true
	case ssaop.OpPermuteFloat32x8:
		v.Op = ssaop.OpAMD64VPERMPS256
		return true
	case ssaop.OpPermuteFloat64x4:
		v.Op = ssaop.OpAMD64VPERMPD256
		return true
	case ssaop.OpPermuteFloat64x8:
		v.Op = ssaop.OpAMD64VPERMPD512
		return true
	case ssaop.OpPermuteInt16x16:
		v.Op = ssaop.OpAMD64VPERMW256
		return true
	case ssaop.OpPermuteInt16x32:
		v.Op = ssaop.OpAMD64VPERMW512
		return true
	case ssaop.OpPermuteInt16x8:
		v.Op = ssaop.OpAMD64VPERMW128
		return true
	case ssaop.OpPermuteInt32x16:
		v.Op = ssaop.OpAMD64VPERMD512
		return true
	case ssaop.OpPermuteInt32x8:
		v.Op = ssaop.OpAMD64VPERMD256
		return true
	case ssaop.OpPermuteInt64x4:
		v.Op = ssaop.OpAMD64VPERMQ256
		return true
	case ssaop.OpPermuteInt64x8:
		v.Op = ssaop.OpAMD64VPERMQ512
		return true
	case ssaop.OpPermuteInt8x16:
		v.Op = ssaop.OpAMD64VPERMB128
		return true
	case ssaop.OpPermuteInt8x32:
		v.Op = ssaop.OpAMD64VPERMB256
		return true
	case ssaop.OpPermuteInt8x64:
		v.Op = ssaop.OpAMD64VPERMB512
		return true
	case ssaop.OpPermuteOrZeroGroupedInt8x32:
		v.Op = ssaop.OpAMD64VPSHUFB256
		return true
	case ssaop.OpPermuteOrZeroGroupedInt8x64:
		v.Op = ssaop.OpAMD64VPSHUFB512
		return true
	case ssaop.OpPermuteOrZeroGroupedUint8x32:
		v.Op = ssaop.OpAMD64VPSHUFB256
		return true
	case ssaop.OpPermuteOrZeroGroupedUint8x64:
		v.Op = ssaop.OpAMD64VPSHUFB512
		return true
	case ssaop.OpPermuteOrZeroInt8x16:
		v.Op = ssaop.OpAMD64VPSHUFB128
		return true
	case ssaop.OpPermuteOrZeroUint8x16:
		v.Op = ssaop.OpAMD64VPSHUFB128
		return true
	case ssaop.OpPermuteUint16x16:
		v.Op = ssaop.OpAMD64VPERMW256
		return true
	case ssaop.OpPermuteUint16x32:
		v.Op = ssaop.OpAMD64VPERMW512
		return true
	case ssaop.OpPermuteUint16x8:
		v.Op = ssaop.OpAMD64VPERMW128
		return true
	case ssaop.OpPermuteUint32x16:
		v.Op = ssaop.OpAMD64VPERMD512
		return true
	case ssaop.OpPermuteUint32x8:
		v.Op = ssaop.OpAMD64VPERMD256
		return true
	case ssaop.OpPermuteUint64x4:
		v.Op = ssaop.OpAMD64VPERMQ256
		return true
	case ssaop.OpPermuteUint64x8:
		v.Op = ssaop.OpAMD64VPERMQ512
		return true
	case ssaop.OpPermuteUint8x16:
		v.Op = ssaop.OpAMD64VPERMB128
		return true
	case ssaop.OpPermuteUint8x32:
		v.Op = ssaop.OpAMD64VPERMB256
		return true
	case ssaop.OpPermuteUint8x64:
		v.Op = ssaop.OpAMD64VPERMB512
		return true
	case ssaop.OpPopCount16:
		return rewriteValue_OpPopCount16(v)
	case ssaop.OpPopCount32:
		v.Op = ssaop.OpAMD64POPCNTL
		return true
	case ssaop.OpPopCount64:
		v.Op = ssaop.OpAMD64POPCNTQ
		return true
	case ssaop.OpPopCount8:
		return rewriteValue_OpPopCount8(v)
	case ssaop.OpPrefetchCache:
		v.Op = ssaop.OpAMD64PrefetchT0
		return true
	case ssaop.OpPrefetchCacheStreamed:
		v.Op = ssaop.OpAMD64PrefetchNTA
		return true
	case ssaop.OpReciprocalFloat32x16:
		v.Op = ssaop.OpAMD64VRCP14PS512
		return true
	case ssaop.OpReciprocalFloat32x4:
		v.Op = ssaop.OpAMD64VRCPPS128
		return true
	case ssaop.OpReciprocalFloat32x8:
		v.Op = ssaop.OpAMD64VRCPPS256
		return true
	case ssaop.OpReciprocalFloat64x2:
		v.Op = ssaop.OpAMD64VRCP14PD128
		return true
	case ssaop.OpReciprocalFloat64x4:
		v.Op = ssaop.OpAMD64VRCP14PD256
		return true
	case ssaop.OpReciprocalFloat64x8:
		v.Op = ssaop.OpAMD64VRCP14PD512
		return true
	case ssaop.OpReciprocalSqrtFloat32x16:
		v.Op = ssaop.OpAMD64VRSQRT14PS512
		return true
	case ssaop.OpReciprocalSqrtFloat32x4:
		v.Op = ssaop.OpAMD64VRSQRTPS128
		return true
	case ssaop.OpReciprocalSqrtFloat32x8:
		v.Op = ssaop.OpAMD64VRSQRTPS256
		return true
	case ssaop.OpReciprocalSqrtFloat64x2:
		v.Op = ssaop.OpAMD64VRSQRT14PD128
		return true
	case ssaop.OpReciprocalSqrtFloat64x4:
		v.Op = ssaop.OpAMD64VRSQRT14PD256
		return true
	case ssaop.OpReciprocalSqrtFloat64x8:
		v.Op = ssaop.OpAMD64VRSQRT14PD512
		return true
	case ssaop.OpRotateLeft16:
		v.Op = ssaop.OpAMD64ROLW
		return true
	case ssaop.OpRotateLeft32:
		v.Op = ssaop.OpAMD64ROLL
		return true
	case ssaop.OpRotateLeft64:
		v.Op = ssaop.OpAMD64ROLQ
		return true
	case ssaop.OpRotateLeft8:
		v.Op = ssaop.OpAMD64ROLB
		return true
	case ssaop.OpRotateLeftInt32x16:
		v.Op = ssaop.OpAMD64VPROLVD512
		return true
	case ssaop.OpRotateLeftInt32x4:
		v.Op = ssaop.OpAMD64VPROLVD128
		return true
	case ssaop.OpRotateLeftInt32x8:
		v.Op = ssaop.OpAMD64VPROLVD256
		return true
	case ssaop.OpRotateLeftInt64x2:
		v.Op = ssaop.OpAMD64VPROLVQ128
		return true
	case ssaop.OpRotateLeftInt64x4:
		v.Op = ssaop.OpAMD64VPROLVQ256
		return true
	case ssaop.OpRotateLeftInt64x8:
		v.Op = ssaop.OpAMD64VPROLVQ512
		return true
	case ssaop.OpRotateLeftUint32x16:
		v.Op = ssaop.OpAMD64VPROLVD512
		return true
	case ssaop.OpRotateLeftUint32x4:
		v.Op = ssaop.OpAMD64VPROLVD128
		return true
	case ssaop.OpRotateLeftUint32x8:
		v.Op = ssaop.OpAMD64VPROLVD256
		return true
	case ssaop.OpRotateLeftUint64x2:
		v.Op = ssaop.OpAMD64VPROLVQ128
		return true
	case ssaop.OpRotateLeftUint64x4:
		v.Op = ssaop.OpAMD64VPROLVQ256
		return true
	case ssaop.OpRotateLeftUint64x8:
		v.Op = ssaop.OpAMD64VPROLVQ512
		return true
	case ssaop.OpRotateRightInt32x16:
		v.Op = ssaop.OpAMD64VPRORVD512
		return true
	case ssaop.OpRotateRightInt32x4:
		v.Op = ssaop.OpAMD64VPRORVD128
		return true
	case ssaop.OpRotateRightInt32x8:
		v.Op = ssaop.OpAMD64VPRORVD256
		return true
	case ssaop.OpRotateRightInt64x2:
		v.Op = ssaop.OpAMD64VPRORVQ128
		return true
	case ssaop.OpRotateRightInt64x4:
		v.Op = ssaop.OpAMD64VPRORVQ256
		return true
	case ssaop.OpRotateRightInt64x8:
		v.Op = ssaop.OpAMD64VPRORVQ512
		return true
	case ssaop.OpRotateRightUint32x16:
		v.Op = ssaop.OpAMD64VPRORVD512
		return true
	case ssaop.OpRotateRightUint32x4:
		v.Op = ssaop.OpAMD64VPRORVD128
		return true
	case ssaop.OpRotateRightUint32x8:
		v.Op = ssaop.OpAMD64VPRORVD256
		return true
	case ssaop.OpRotateRightUint64x2:
		v.Op = ssaop.OpAMD64VPRORVQ128
		return true
	case ssaop.OpRotateRightUint64x4:
		v.Op = ssaop.OpAMD64VPRORVQ256
		return true
	case ssaop.OpRotateRightUint64x8:
		v.Op = ssaop.OpAMD64VPRORVQ512
		return true
	case ssaop.OpRound32F:
		v.Op = ssaop.OpAMD64LoweredRound32F
		return true
	case ssaop.OpRound64F:
		v.Op = ssaop.OpAMD64LoweredRound64F
		return true
	case ssaop.OpRoundFloat32x4:
		return rewriteValue_OpRoundFloat32x4(v)
	case ssaop.OpRoundFloat32x8:
		return rewriteValue_OpRoundFloat32x8(v)
	case ssaop.OpRoundFloat64x2:
		return rewriteValue_OpRoundFloat64x2(v)
	case ssaop.OpRoundFloat64x4:
		return rewriteValue_OpRoundFloat64x4(v)
	case ssaop.OpRoundScaledFloat32x16:
		return rewriteValue_OpRoundScaledFloat32x16(v)
	case ssaop.OpRoundScaledFloat32x4:
		return rewriteValue_OpRoundScaledFloat32x4(v)
	case ssaop.OpRoundScaledFloat32x8:
		return rewriteValue_OpRoundScaledFloat32x8(v)
	case ssaop.OpRoundScaledFloat64x2:
		return rewriteValue_OpRoundScaledFloat64x2(v)
	case ssaop.OpRoundScaledFloat64x4:
		return rewriteValue_OpRoundScaledFloat64x4(v)
	case ssaop.OpRoundScaledFloat64x8:
		return rewriteValue_OpRoundScaledFloat64x8(v)
	case ssaop.OpRoundScaledResidueFloat32x16:
		return rewriteValue_OpRoundScaledResidueFloat32x16(v)
	case ssaop.OpRoundScaledResidueFloat32x4:
		return rewriteValue_OpRoundScaledResidueFloat32x4(v)
	case ssaop.OpRoundScaledResidueFloat32x8:
		return rewriteValue_OpRoundScaledResidueFloat32x8(v)
	case ssaop.OpRoundScaledResidueFloat64x2:
		return rewriteValue_OpRoundScaledResidueFloat64x2(v)
	case ssaop.OpRoundScaledResidueFloat64x4:
		return rewriteValue_OpRoundScaledResidueFloat64x4(v)
	case ssaop.OpRoundScaledResidueFloat64x8:
		return rewriteValue_OpRoundScaledResidueFloat64x8(v)
	case ssaop.OpRoundToEven:
		return rewriteValue_OpRoundToEven(v)
	case ssaop.OpRsh16Ux16:
		return rewriteValue_OpRsh16Ux16(v)
	case ssaop.OpRsh16Ux32:
		return rewriteValue_OpRsh16Ux32(v)
	case ssaop.OpRsh16Ux64:
		return rewriteValue_OpRsh16Ux64(v)
	case ssaop.OpRsh16Ux8:
		return rewriteValue_OpRsh16Ux8(v)
	case ssaop.OpRsh16x16:
		return rewriteValue_OpRsh16x16(v)
	case ssaop.OpRsh16x32:
		return rewriteValue_OpRsh16x32(v)
	case ssaop.OpRsh16x64:
		return rewriteValue_OpRsh16x64(v)
	case ssaop.OpRsh16x8:
		return rewriteValue_OpRsh16x8(v)
	case ssaop.OpRsh32Ux16:
		return rewriteValue_OpRsh32Ux16(v)
	case ssaop.OpRsh32Ux32:
		return rewriteValue_OpRsh32Ux32(v)
	case ssaop.OpRsh32Ux64:
		return rewriteValue_OpRsh32Ux64(v)
	case ssaop.OpRsh32Ux8:
		return rewriteValue_OpRsh32Ux8(v)
	case ssaop.OpRsh32x16:
		return rewriteValue_OpRsh32x16(v)
	case ssaop.OpRsh32x32:
		return rewriteValue_OpRsh32x32(v)
	case ssaop.OpRsh32x64:
		return rewriteValue_OpRsh32x64(v)
	case ssaop.OpRsh32x8:
		return rewriteValue_OpRsh32x8(v)
	case ssaop.OpRsh64Ux16:
		return rewriteValue_OpRsh64Ux16(v)
	case ssaop.OpRsh64Ux32:
		return rewriteValue_OpRsh64Ux32(v)
	case ssaop.OpRsh64Ux64:
		return rewriteValue_OpRsh64Ux64(v)
	case ssaop.OpRsh64Ux8:
		return rewriteValue_OpRsh64Ux8(v)
	case ssaop.OpRsh64x16:
		return rewriteValue_OpRsh64x16(v)
	case ssaop.OpRsh64x32:
		return rewriteValue_OpRsh64x32(v)
	case ssaop.OpRsh64x64:
		return rewriteValue_OpRsh64x64(v)
	case ssaop.OpRsh64x8:
		return rewriteValue_OpRsh64x8(v)
	case ssaop.OpRsh8Ux16:
		return rewriteValue_OpRsh8Ux16(v)
	case ssaop.OpRsh8Ux32:
		return rewriteValue_OpRsh8Ux32(v)
	case ssaop.OpRsh8Ux64:
		return rewriteValue_OpRsh8Ux64(v)
	case ssaop.OpRsh8Ux8:
		return rewriteValue_OpRsh8Ux8(v)
	case ssaop.OpRsh8x16:
		return rewriteValue_OpRsh8x16(v)
	case ssaop.OpRsh8x32:
		return rewriteValue_OpRsh8x32(v)
	case ssaop.OpRsh8x64:
		return rewriteValue_OpRsh8x64(v)
	case ssaop.OpRsh8x8:
		return rewriteValue_OpRsh8x8(v)
	case ssaop.OpSHA1FourRoundsUint32x4:
		v.Op = ssaop.OpAMD64SHA1RNDS4128
		return true
	case ssaop.OpSHA1Message1Uint32x4:
		v.Op = ssaop.OpAMD64SHA1MSG1128
		return true
	case ssaop.OpSHA1Message2Uint32x4:
		v.Op = ssaop.OpAMD64SHA1MSG2128
		return true
	case ssaop.OpSHA1NextEUint32x4:
		v.Op = ssaop.OpAMD64SHA1NEXTE128
		return true
	case ssaop.OpSHA256Message1Uint32x4:
		v.Op = ssaop.OpAMD64SHA256MSG1128
		return true
	case ssaop.OpSHA256Message2Uint32x4:
		v.Op = ssaop.OpAMD64SHA256MSG2128
		return true
	case ssaop.OpSHA256TwoRoundsUint32x4:
		v.Op = ssaop.OpAMD64SHA256RNDS2128
		return true
	case ssaop.OpSaturateToInt16ConcatGroupedInt32x16:
		v.Op = ssaop.OpAMD64VPACKSSDW512
		return true
	case ssaop.OpSaturateToInt16ConcatGroupedInt32x8:
		v.Op = ssaop.OpAMD64VPACKSSDW256
		return true
	case ssaop.OpSaturateToInt16ConcatInt32x4:
		v.Op = ssaop.OpAMD64VPACKSSDW128
		return true
	case ssaop.OpSaturateToInt16Int32x16:
		v.Op = ssaop.OpAMD64VPMOVSDW256
		return true
	case ssaop.OpSaturateToInt16Int32x4:
		v.Op = ssaop.OpAMD64VPMOVSDW128_128
		return true
	case ssaop.OpSaturateToInt16Int32x8:
		v.Op = ssaop.OpAMD64VPMOVSDW128_256
		return true
	case ssaop.OpSaturateToInt16Int64x2:
		v.Op = ssaop.OpAMD64VPMOVSQW128_128
		return true
	case ssaop.OpSaturateToInt16Int64x4:
		v.Op = ssaop.OpAMD64VPMOVSQW128_256
		return true
	case ssaop.OpSaturateToInt16Int64x8:
		v.Op = ssaop.OpAMD64VPMOVSQW128_512
		return true
	case ssaop.OpSaturateToInt32Int64x2:
		v.Op = ssaop.OpAMD64VPMOVSQD128_128
		return true
	case ssaop.OpSaturateToInt32Int64x4:
		v.Op = ssaop.OpAMD64VPMOVSQD128_256
		return true
	case ssaop.OpSaturateToInt32Int64x8:
		v.Op = ssaop.OpAMD64VPMOVSQD256
		return true
	case ssaop.OpSaturateToInt8Int16x16:
		v.Op = ssaop.OpAMD64VPMOVSWB128_256
		return true
	case ssaop.OpSaturateToInt8Int16x32:
		v.Op = ssaop.OpAMD64VPMOVSWB256
		return true
	case ssaop.OpSaturateToInt8Int16x8:
		v.Op = ssaop.OpAMD64VPMOVSWB128_128
		return true
	case ssaop.OpSaturateToInt8Int32x16:
		v.Op = ssaop.OpAMD64VPMOVSDB128_512
		return true
	case ssaop.OpSaturateToInt8Int32x4:
		v.Op = ssaop.OpAMD64VPMOVSDB128_128
		return true
	case ssaop.OpSaturateToInt8Int32x8:
		v.Op = ssaop.OpAMD64VPMOVSDB128_256
		return true
	case ssaop.OpSaturateToInt8Int64x2:
		v.Op = ssaop.OpAMD64VPMOVSQB128_128
		return true
	case ssaop.OpSaturateToInt8Int64x4:
		v.Op = ssaop.OpAMD64VPMOVSQB128_256
		return true
	case ssaop.OpSaturateToInt8Int64x8:
		v.Op = ssaop.OpAMD64VPMOVSQB128_512
		return true
	case ssaop.OpSaturateToUint16ConcatGroupedInt32x16:
		v.Op = ssaop.OpAMD64VPACKUSDW512
		return true
	case ssaop.OpSaturateToUint16ConcatGroupedInt32x8:
		v.Op = ssaop.OpAMD64VPACKUSDW256
		return true
	case ssaop.OpSaturateToUint16ConcatInt32x4:
		v.Op = ssaop.OpAMD64VPACKUSDW128
		return true
	case ssaop.OpSaturateToUint16Uint32x16:
		v.Op = ssaop.OpAMD64VPMOVUSDW256
		return true
	case ssaop.OpSaturateToUint16Uint32x4:
		v.Op = ssaop.OpAMD64VPMOVUSDW128_128
		return true
	case ssaop.OpSaturateToUint16Uint32x8:
		v.Op = ssaop.OpAMD64VPMOVUSDW128_256
		return true
	case ssaop.OpSaturateToUint16Uint64x2:
		v.Op = ssaop.OpAMD64VPMOVUSQW128_128
		return true
	case ssaop.OpSaturateToUint16Uint64x4:
		v.Op = ssaop.OpAMD64VPMOVUSQW128_256
		return true
	case ssaop.OpSaturateToUint16Uint64x8:
		v.Op = ssaop.OpAMD64VPMOVUSQW128_512
		return true
	case ssaop.OpSaturateToUint32Uint64x2:
		v.Op = ssaop.OpAMD64VPMOVUSQD128_128
		return true
	case ssaop.OpSaturateToUint32Uint64x4:
		v.Op = ssaop.OpAMD64VPMOVUSQD128_256
		return true
	case ssaop.OpSaturateToUint32Uint64x8:
		v.Op = ssaop.OpAMD64VPMOVUSQD256
		return true
	case ssaop.OpSaturateToUint8Uint16x16:
		v.Op = ssaop.OpAMD64VPMOVUSWB128_256
		return true
	case ssaop.OpSaturateToUint8Uint16x32:
		v.Op = ssaop.OpAMD64VPMOVUSWB256
		return true
	case ssaop.OpSaturateToUint8Uint16x8:
		v.Op = ssaop.OpAMD64VPMOVUSWB128_128
		return true
	case ssaop.OpSaturateToUint8Uint32x16:
		v.Op = ssaop.OpAMD64VPMOVUSDB128_512
		return true
	case ssaop.OpSaturateToUint8Uint32x4:
		v.Op = ssaop.OpAMD64VPMOVUSDB128_128
		return true
	case ssaop.OpSaturateToUint8Uint32x8:
		v.Op = ssaop.OpAMD64VPMOVUSDB128_256
		return true
	case ssaop.OpSaturateToUint8Uint64x2:
		v.Op = ssaop.OpAMD64VPMOVUSQB128_128
		return true
	case ssaop.OpSaturateToUint8Uint64x4:
		v.Op = ssaop.OpAMD64VPMOVUSQB128_256
		return true
	case ssaop.OpSaturateToUint8Uint64x8:
		v.Op = ssaop.OpAMD64VPMOVUSQB128_512
		return true
	case ssaop.OpScaleFloat32x16:
		v.Op = ssaop.OpAMD64VSCALEFPS512
		return true
	case ssaop.OpScaleFloat32x4:
		v.Op = ssaop.OpAMD64VSCALEFPS128
		return true
	case ssaop.OpScaleFloat32x8:
		v.Op = ssaop.OpAMD64VSCALEFPS256
		return true
	case ssaop.OpScaleFloat64x2:
		v.Op = ssaop.OpAMD64VSCALEFPD128
		return true
	case ssaop.OpScaleFloat64x4:
		v.Op = ssaop.OpAMD64VSCALEFPD256
		return true
	case ssaop.OpScaleFloat64x8:
		v.Op = ssaop.OpAMD64VSCALEFPD512
		return true
	case ssaop.OpSelect0:
		return rewriteValue_OpSelect0(v)
	case ssaop.OpSelect1:
		return rewriteValue_OpSelect1(v)
	case ssaop.OpSelectN:
		return rewriteValue_OpSelectN(v)
	case ssaop.OpSetElemFloat32x4:
		v.Op = ssaop.OpAMD64VPINSRD128
		return true
	case ssaop.OpSetElemFloat64x2:
		v.Op = ssaop.OpAMD64VPINSRQ128
		return true
	case ssaop.OpSetElemInt16x8:
		v.Op = ssaop.OpAMD64VPINSRW128
		return true
	case ssaop.OpSetElemInt32x4:
		v.Op = ssaop.OpAMD64VPINSRD128
		return true
	case ssaop.OpSetElemInt64x2:
		v.Op = ssaop.OpAMD64VPINSRQ128
		return true
	case ssaop.OpSetElemInt8x16:
		v.Op = ssaop.OpAMD64VPINSRB128
		return true
	case ssaop.OpSetElemUint16x8:
		v.Op = ssaop.OpAMD64VPINSRW128
		return true
	case ssaop.OpSetElemUint32x4:
		v.Op = ssaop.OpAMD64VPINSRD128
		return true
	case ssaop.OpSetElemUint64x2:
		v.Op = ssaop.OpAMD64VPINSRQ128
		return true
	case ssaop.OpSetElemUint8x16:
		v.Op = ssaop.OpAMD64VPINSRB128
		return true
	case ssaop.OpSetHiFloat32x16:
		return rewriteValue_OpSetHiFloat32x16(v)
	case ssaop.OpSetHiFloat32x8:
		return rewriteValue_OpSetHiFloat32x8(v)
	case ssaop.OpSetHiFloat64x4:
		return rewriteValue_OpSetHiFloat64x4(v)
	case ssaop.OpSetHiFloat64x8:
		return rewriteValue_OpSetHiFloat64x8(v)
	case ssaop.OpSetHiInt16x16:
		return rewriteValue_OpSetHiInt16x16(v)
	case ssaop.OpSetHiInt16x32:
		return rewriteValue_OpSetHiInt16x32(v)
	case ssaop.OpSetHiInt32x16:
		return rewriteValue_OpSetHiInt32x16(v)
	case ssaop.OpSetHiInt32x8:
		return rewriteValue_OpSetHiInt32x8(v)
	case ssaop.OpSetHiInt64x4:
		return rewriteValue_OpSetHiInt64x4(v)
	case ssaop.OpSetHiInt64x8:
		return rewriteValue_OpSetHiInt64x8(v)
	case ssaop.OpSetHiInt8x32:
		return rewriteValue_OpSetHiInt8x32(v)
	case ssaop.OpSetHiInt8x64:
		return rewriteValue_OpSetHiInt8x64(v)
	case ssaop.OpSetHiUint16x16:
		return rewriteValue_OpSetHiUint16x16(v)
	case ssaop.OpSetHiUint16x32:
		return rewriteValue_OpSetHiUint16x32(v)
	case ssaop.OpSetHiUint32x16:
		return rewriteValue_OpSetHiUint32x16(v)
	case ssaop.OpSetHiUint32x8:
		return rewriteValue_OpSetHiUint32x8(v)
	case ssaop.OpSetHiUint64x4:
		return rewriteValue_OpSetHiUint64x4(v)
	case ssaop.OpSetHiUint64x8:
		return rewriteValue_OpSetHiUint64x8(v)
	case ssaop.OpSetHiUint8x32:
		return rewriteValue_OpSetHiUint8x32(v)
	case ssaop.OpSetHiUint8x64:
		return rewriteValue_OpSetHiUint8x64(v)
	case ssaop.OpSetLoFloat32x16:
		return rewriteValue_OpSetLoFloat32x16(v)
	case ssaop.OpSetLoFloat32x8:
		return rewriteValue_OpSetLoFloat32x8(v)
	case ssaop.OpSetLoFloat64x4:
		return rewriteValue_OpSetLoFloat64x4(v)
	case ssaop.OpSetLoFloat64x8:
		return rewriteValue_OpSetLoFloat64x8(v)
	case ssaop.OpSetLoInt16x16:
		return rewriteValue_OpSetLoInt16x16(v)
	case ssaop.OpSetLoInt16x32:
		return rewriteValue_OpSetLoInt16x32(v)
	case ssaop.OpSetLoInt32x16:
		return rewriteValue_OpSetLoInt32x16(v)
	case ssaop.OpSetLoInt32x8:
		return rewriteValue_OpSetLoInt32x8(v)
	case ssaop.OpSetLoInt64x4:
		return rewriteValue_OpSetLoInt64x4(v)
	case ssaop.OpSetLoInt64x8:
		return rewriteValue_OpSetLoInt64x8(v)
	case ssaop.OpSetLoInt8x32:
		return rewriteValue_OpSetLoInt8x32(v)
	case ssaop.OpSetLoInt8x64:
		return rewriteValue_OpSetLoInt8x64(v)
	case ssaop.OpSetLoUint16x16:
		return rewriteValue_OpSetLoUint16x16(v)
	case ssaop.OpSetLoUint16x32:
		return rewriteValue_OpSetLoUint16x32(v)
	case ssaop.OpSetLoUint32x16:
		return rewriteValue_OpSetLoUint32x16(v)
	case ssaop.OpSetLoUint32x8:
		return rewriteValue_OpSetLoUint32x8(v)
	case ssaop.OpSetLoUint64x4:
		return rewriteValue_OpSetLoUint64x4(v)
	case ssaop.OpSetLoUint64x8:
		return rewriteValue_OpSetLoUint64x8(v)
	case ssaop.OpSetLoUint8x32:
		return rewriteValue_OpSetLoUint8x32(v)
	case ssaop.OpSetLoUint8x64:
		return rewriteValue_OpSetLoUint8x64(v)
	case ssaop.OpShiftAllLeftConcatMod16Int16x16:
		v.Op = ssaop.OpAMD64VPSHLDW256
		return true
	case ssaop.OpShiftAllLeftConcatMod16Int16x32:
		v.Op = ssaop.OpAMD64VPSHLDW512
		return true
	case ssaop.OpShiftAllLeftConcatMod16Int16x8:
		v.Op = ssaop.OpAMD64VPSHLDW128
		return true
	case ssaop.OpShiftAllLeftConcatMod16Uint16x16:
		v.Op = ssaop.OpAMD64VPSHLDW256
		return true
	case ssaop.OpShiftAllLeftConcatMod16Uint16x32:
		v.Op = ssaop.OpAMD64VPSHLDW512
		return true
	case ssaop.OpShiftAllLeftConcatMod16Uint16x8:
		v.Op = ssaop.OpAMD64VPSHLDW128
		return true
	case ssaop.OpShiftAllLeftConcatMod32Int32x16:
		v.Op = ssaop.OpAMD64VPSHLDD512
		return true
	case ssaop.OpShiftAllLeftConcatMod32Int32x4:
		v.Op = ssaop.OpAMD64VPSHLDD128
		return true
	case ssaop.OpShiftAllLeftConcatMod32Int32x8:
		v.Op = ssaop.OpAMD64VPSHLDD256
		return true
	case ssaop.OpShiftAllLeftConcatMod32Uint32x16:
		v.Op = ssaop.OpAMD64VPSHLDD512
		return true
	case ssaop.OpShiftAllLeftConcatMod32Uint32x4:
		v.Op = ssaop.OpAMD64VPSHLDD128
		return true
	case ssaop.OpShiftAllLeftConcatMod32Uint32x8:
		v.Op = ssaop.OpAMD64VPSHLDD256
		return true
	case ssaop.OpShiftAllLeftConcatMod64Int64x2:
		v.Op = ssaop.OpAMD64VPSHLDQ128
		return true
	case ssaop.OpShiftAllLeftConcatMod64Int64x4:
		v.Op = ssaop.OpAMD64VPSHLDQ256
		return true
	case ssaop.OpShiftAllLeftConcatMod64Int64x8:
		v.Op = ssaop.OpAMD64VPSHLDQ512
		return true
	case ssaop.OpShiftAllLeftConcatMod64Uint64x2:
		v.Op = ssaop.OpAMD64VPSHLDQ128
		return true
	case ssaop.OpShiftAllLeftConcatMod64Uint64x4:
		v.Op = ssaop.OpAMD64VPSHLDQ256
		return true
	case ssaop.OpShiftAllLeftConcatMod64Uint64x8:
		v.Op = ssaop.OpAMD64VPSHLDQ512
		return true
	case ssaop.OpShiftAllLeftInt16x16:
		v.Op = ssaop.OpAMD64VPSLLW256
		return true
	case ssaop.OpShiftAllLeftInt16x32:
		v.Op = ssaop.OpAMD64VPSLLW512
		return true
	case ssaop.OpShiftAllLeftInt16x8:
		v.Op = ssaop.OpAMD64VPSLLW128
		return true
	case ssaop.OpShiftAllLeftInt32x16:
		v.Op = ssaop.OpAMD64VPSLLD512
		return true
	case ssaop.OpShiftAllLeftInt32x4:
		v.Op = ssaop.OpAMD64VPSLLD128
		return true
	case ssaop.OpShiftAllLeftInt32x8:
		v.Op = ssaop.OpAMD64VPSLLD256
		return true
	case ssaop.OpShiftAllLeftInt64x2:
		v.Op = ssaop.OpAMD64VPSLLQ128
		return true
	case ssaop.OpShiftAllLeftInt64x4:
		v.Op = ssaop.OpAMD64VPSLLQ256
		return true
	case ssaop.OpShiftAllLeftInt64x8:
		v.Op = ssaop.OpAMD64VPSLLQ512
		return true
	case ssaop.OpShiftAllLeftUint16x16:
		v.Op = ssaop.OpAMD64VPSLLW256
		return true
	case ssaop.OpShiftAllLeftUint16x32:
		v.Op = ssaop.OpAMD64VPSLLW512
		return true
	case ssaop.OpShiftAllLeftUint16x8:
		v.Op = ssaop.OpAMD64VPSLLW128
		return true
	case ssaop.OpShiftAllLeftUint32x16:
		v.Op = ssaop.OpAMD64VPSLLD512
		return true
	case ssaop.OpShiftAllLeftUint32x4:
		v.Op = ssaop.OpAMD64VPSLLD128
		return true
	case ssaop.OpShiftAllLeftUint32x8:
		v.Op = ssaop.OpAMD64VPSLLD256
		return true
	case ssaop.OpShiftAllLeftUint64x2:
		v.Op = ssaop.OpAMD64VPSLLQ128
		return true
	case ssaop.OpShiftAllLeftUint64x4:
		v.Op = ssaop.OpAMD64VPSLLQ256
		return true
	case ssaop.OpShiftAllLeftUint64x8:
		v.Op = ssaop.OpAMD64VPSLLQ512
		return true
	case ssaop.OpShiftAllRightConcatMod16Int16x16:
		v.Op = ssaop.OpAMD64VPSHRDW256
		return true
	case ssaop.OpShiftAllRightConcatMod16Int16x32:
		v.Op = ssaop.OpAMD64VPSHRDW512
		return true
	case ssaop.OpShiftAllRightConcatMod16Int16x8:
		v.Op = ssaop.OpAMD64VPSHRDW128
		return true
	case ssaop.OpShiftAllRightConcatMod16Uint16x16:
		v.Op = ssaop.OpAMD64VPSHRDW256
		return true
	case ssaop.OpShiftAllRightConcatMod16Uint16x32:
		v.Op = ssaop.OpAMD64VPSHRDW512
		return true
	case ssaop.OpShiftAllRightConcatMod16Uint16x8:
		v.Op = ssaop.OpAMD64VPSHRDW128
		return true
	case ssaop.OpShiftAllRightConcatMod32Int32x16:
		v.Op = ssaop.OpAMD64VPSHRDD512
		return true
	case ssaop.OpShiftAllRightConcatMod32Int32x4:
		v.Op = ssaop.OpAMD64VPSHRDD128
		return true
	case ssaop.OpShiftAllRightConcatMod32Int32x8:
		v.Op = ssaop.OpAMD64VPSHRDD256
		return true
	case ssaop.OpShiftAllRightConcatMod32Uint32x16:
		v.Op = ssaop.OpAMD64VPSHRDD512
		return true
	case ssaop.OpShiftAllRightConcatMod32Uint32x4:
		v.Op = ssaop.OpAMD64VPSHRDD128
		return true
	case ssaop.OpShiftAllRightConcatMod32Uint32x8:
		v.Op = ssaop.OpAMD64VPSHRDD256
		return true
	case ssaop.OpShiftAllRightConcatMod64Int64x2:
		v.Op = ssaop.OpAMD64VPSHRDQ128
		return true
	case ssaop.OpShiftAllRightConcatMod64Int64x4:
		v.Op = ssaop.OpAMD64VPSHRDQ256
		return true
	case ssaop.OpShiftAllRightConcatMod64Int64x8:
		v.Op = ssaop.OpAMD64VPSHRDQ512
		return true
	case ssaop.OpShiftAllRightConcatMod64Uint64x2:
		v.Op = ssaop.OpAMD64VPSHRDQ128
		return true
	case ssaop.OpShiftAllRightConcatMod64Uint64x4:
		v.Op = ssaop.OpAMD64VPSHRDQ256
		return true
	case ssaop.OpShiftAllRightConcatMod64Uint64x8:
		v.Op = ssaop.OpAMD64VPSHRDQ512
		return true
	case ssaop.OpShiftAllRightInt16x16:
		v.Op = ssaop.OpAMD64VPSRAW256
		return true
	case ssaop.OpShiftAllRightInt16x32:
		v.Op = ssaop.OpAMD64VPSRAW512
		return true
	case ssaop.OpShiftAllRightInt16x8:
		v.Op = ssaop.OpAMD64VPSRAW128
		return true
	case ssaop.OpShiftAllRightInt32x16:
		v.Op = ssaop.OpAMD64VPSRAD512
		return true
	case ssaop.OpShiftAllRightInt32x4:
		v.Op = ssaop.OpAMD64VPSRAD128
		return true
	case ssaop.OpShiftAllRightInt32x8:
		v.Op = ssaop.OpAMD64VPSRAD256
		return true
	case ssaop.OpShiftAllRightInt64x2:
		v.Op = ssaop.OpAMD64VPSRAQ128
		return true
	case ssaop.OpShiftAllRightInt64x4:
		v.Op = ssaop.OpAMD64VPSRAQ256
		return true
	case ssaop.OpShiftAllRightInt64x8:
		v.Op = ssaop.OpAMD64VPSRAQ512
		return true
	case ssaop.OpShiftAllRightUint16x16:
		v.Op = ssaop.OpAMD64VPSRLW256
		return true
	case ssaop.OpShiftAllRightUint16x32:
		v.Op = ssaop.OpAMD64VPSRLW512
		return true
	case ssaop.OpShiftAllRightUint16x8:
		v.Op = ssaop.OpAMD64VPSRLW128
		return true
	case ssaop.OpShiftAllRightUint32x16:
		v.Op = ssaop.OpAMD64VPSRLD512
		return true
	case ssaop.OpShiftAllRightUint32x4:
		v.Op = ssaop.OpAMD64VPSRLD128
		return true
	case ssaop.OpShiftAllRightUint32x8:
		v.Op = ssaop.OpAMD64VPSRLD256
		return true
	case ssaop.OpShiftAllRightUint64x2:
		v.Op = ssaop.OpAMD64VPSRLQ128
		return true
	case ssaop.OpShiftAllRightUint64x4:
		v.Op = ssaop.OpAMD64VPSRLQ256
		return true
	case ssaop.OpShiftAllRightUint64x8:
		v.Op = ssaop.OpAMD64VPSRLQ512
		return true
	case ssaop.OpShiftLeftConcatMod16Int16x16:
		v.Op = ssaop.OpAMD64VPSHLDVW256
		return true
	case ssaop.OpShiftLeftConcatMod16Int16x32:
		v.Op = ssaop.OpAMD64VPSHLDVW512
		return true
	case ssaop.OpShiftLeftConcatMod16Int16x8:
		v.Op = ssaop.OpAMD64VPSHLDVW128
		return true
	case ssaop.OpShiftLeftConcatMod16Uint16x16:
		v.Op = ssaop.OpAMD64VPSHLDVW256
		return true
	case ssaop.OpShiftLeftConcatMod16Uint16x32:
		v.Op = ssaop.OpAMD64VPSHLDVW512
		return true
	case ssaop.OpShiftLeftConcatMod16Uint16x8:
		v.Op = ssaop.OpAMD64VPSHLDVW128
		return true
	case ssaop.OpShiftLeftConcatMod32Int32x16:
		v.Op = ssaop.OpAMD64VPSHLDVD512
		return true
	case ssaop.OpShiftLeftConcatMod32Int32x4:
		v.Op = ssaop.OpAMD64VPSHLDVD128
		return true
	case ssaop.OpShiftLeftConcatMod32Int32x8:
		v.Op = ssaop.OpAMD64VPSHLDVD256
		return true
	case ssaop.OpShiftLeftConcatMod32Uint32x16:
		v.Op = ssaop.OpAMD64VPSHLDVD512
		return true
	case ssaop.OpShiftLeftConcatMod32Uint32x4:
		v.Op = ssaop.OpAMD64VPSHLDVD128
		return true
	case ssaop.OpShiftLeftConcatMod32Uint32x8:
		v.Op = ssaop.OpAMD64VPSHLDVD256
		return true
	case ssaop.OpShiftLeftConcatMod64Int64x2:
		v.Op = ssaop.OpAMD64VPSHLDVQ128
		return true
	case ssaop.OpShiftLeftConcatMod64Int64x4:
		v.Op = ssaop.OpAMD64VPSHLDVQ256
		return true
	case ssaop.OpShiftLeftConcatMod64Int64x8:
		v.Op = ssaop.OpAMD64VPSHLDVQ512
		return true
	case ssaop.OpShiftLeftConcatMod64Uint64x2:
		v.Op = ssaop.OpAMD64VPSHLDVQ128
		return true
	case ssaop.OpShiftLeftConcatMod64Uint64x4:
		v.Op = ssaop.OpAMD64VPSHLDVQ256
		return true
	case ssaop.OpShiftLeftConcatMod64Uint64x8:
		v.Op = ssaop.OpAMD64VPSHLDVQ512
		return true
	case ssaop.OpShiftLeftInt16x16:
		v.Op = ssaop.OpAMD64VPSLLVW256
		return true
	case ssaop.OpShiftLeftInt16x32:
		v.Op = ssaop.OpAMD64VPSLLVW512
		return true
	case ssaop.OpShiftLeftInt16x8:
		v.Op = ssaop.OpAMD64VPSLLVW128
		return true
	case ssaop.OpShiftLeftInt32x16:
		v.Op = ssaop.OpAMD64VPSLLVD512
		return true
	case ssaop.OpShiftLeftInt32x4:
		v.Op = ssaop.OpAMD64VPSLLVD128
		return true
	case ssaop.OpShiftLeftInt32x8:
		v.Op = ssaop.OpAMD64VPSLLVD256
		return true
	case ssaop.OpShiftLeftInt64x2:
		v.Op = ssaop.OpAMD64VPSLLVQ128
		return true
	case ssaop.OpShiftLeftInt64x4:
		v.Op = ssaop.OpAMD64VPSLLVQ256
		return true
	case ssaop.OpShiftLeftInt64x8:
		v.Op = ssaop.OpAMD64VPSLLVQ512
		return true
	case ssaop.OpShiftLeftUint16x16:
		v.Op = ssaop.OpAMD64VPSLLVW256
		return true
	case ssaop.OpShiftLeftUint16x32:
		v.Op = ssaop.OpAMD64VPSLLVW512
		return true
	case ssaop.OpShiftLeftUint16x8:
		v.Op = ssaop.OpAMD64VPSLLVW128
		return true
	case ssaop.OpShiftLeftUint32x16:
		v.Op = ssaop.OpAMD64VPSLLVD512
		return true
	case ssaop.OpShiftLeftUint32x4:
		v.Op = ssaop.OpAMD64VPSLLVD128
		return true
	case ssaop.OpShiftLeftUint32x8:
		v.Op = ssaop.OpAMD64VPSLLVD256
		return true
	case ssaop.OpShiftLeftUint64x2:
		v.Op = ssaop.OpAMD64VPSLLVQ128
		return true
	case ssaop.OpShiftLeftUint64x4:
		v.Op = ssaop.OpAMD64VPSLLVQ256
		return true
	case ssaop.OpShiftLeftUint64x8:
		v.Op = ssaop.OpAMD64VPSLLVQ512
		return true
	case ssaop.OpShiftRightConcatMod16Int16x16:
		v.Op = ssaop.OpAMD64VPSHRDVW256
		return true
	case ssaop.OpShiftRightConcatMod16Int16x32:
		v.Op = ssaop.OpAMD64VPSHRDVW512
		return true
	case ssaop.OpShiftRightConcatMod16Int16x8:
		v.Op = ssaop.OpAMD64VPSHRDVW128
		return true
	case ssaop.OpShiftRightConcatMod16Uint16x16:
		v.Op = ssaop.OpAMD64VPSHRDVW256
		return true
	case ssaop.OpShiftRightConcatMod16Uint16x32:
		v.Op = ssaop.OpAMD64VPSHRDVW512
		return true
	case ssaop.OpShiftRightConcatMod16Uint16x8:
		v.Op = ssaop.OpAMD64VPSHRDVW128
		return true
	case ssaop.OpShiftRightConcatMod32Int32x16:
		v.Op = ssaop.OpAMD64VPSHRDVD512
		return true
	case ssaop.OpShiftRightConcatMod32Int32x4:
		v.Op = ssaop.OpAMD64VPSHRDVD128
		return true
	case ssaop.OpShiftRightConcatMod32Int32x8:
		v.Op = ssaop.OpAMD64VPSHRDVD256
		return true
	case ssaop.OpShiftRightConcatMod32Uint32x16:
		v.Op = ssaop.OpAMD64VPSHRDVD512
		return true
	case ssaop.OpShiftRightConcatMod32Uint32x4:
		v.Op = ssaop.OpAMD64VPSHRDVD128
		return true
	case ssaop.OpShiftRightConcatMod32Uint32x8:
		v.Op = ssaop.OpAMD64VPSHRDVD256
		return true
	case ssaop.OpShiftRightConcatMod64Int64x2:
		v.Op = ssaop.OpAMD64VPSHRDVQ128
		return true
	case ssaop.OpShiftRightConcatMod64Int64x4:
		v.Op = ssaop.OpAMD64VPSHRDVQ256
		return true
	case ssaop.OpShiftRightConcatMod64Int64x8:
		v.Op = ssaop.OpAMD64VPSHRDVQ512
		return true
	case ssaop.OpShiftRightConcatMod64Uint64x2:
		v.Op = ssaop.OpAMD64VPSHRDVQ128
		return true
	case ssaop.OpShiftRightConcatMod64Uint64x4:
		v.Op = ssaop.OpAMD64VPSHRDVQ256
		return true
	case ssaop.OpShiftRightConcatMod64Uint64x8:
		v.Op = ssaop.OpAMD64VPSHRDVQ512
		return true
	case ssaop.OpShiftRightInt16x16:
		v.Op = ssaop.OpAMD64VPSRAVW256
		return true
	case ssaop.OpShiftRightInt16x32:
		v.Op = ssaop.OpAMD64VPSRAVW512
		return true
	case ssaop.OpShiftRightInt16x8:
		v.Op = ssaop.OpAMD64VPSRAVW128
		return true
	case ssaop.OpShiftRightInt32x16:
		v.Op = ssaop.OpAMD64VPSRAVD512
		return true
	case ssaop.OpShiftRightInt32x4:
		v.Op = ssaop.OpAMD64VPSRAVD128
		return true
	case ssaop.OpShiftRightInt32x8:
		v.Op = ssaop.OpAMD64VPSRAVD256
		return true
	case ssaop.OpShiftRightInt64x2:
		v.Op = ssaop.OpAMD64VPSRAVQ128
		return true
	case ssaop.OpShiftRightInt64x4:
		v.Op = ssaop.OpAMD64VPSRAVQ256
		return true
	case ssaop.OpShiftRightInt64x8:
		v.Op = ssaop.OpAMD64VPSRAVQ512
		return true
	case ssaop.OpShiftRightUint16x16:
		v.Op = ssaop.OpAMD64VPSRLVW256
		return true
	case ssaop.OpShiftRightUint16x32:
		v.Op = ssaop.OpAMD64VPSRLVW512
		return true
	case ssaop.OpShiftRightUint16x8:
		v.Op = ssaop.OpAMD64VPSRLVW128
		return true
	case ssaop.OpShiftRightUint32x16:
		v.Op = ssaop.OpAMD64VPSRLVD512
		return true
	case ssaop.OpShiftRightUint32x4:
		v.Op = ssaop.OpAMD64VPSRLVD128
		return true
	case ssaop.OpShiftRightUint32x8:
		v.Op = ssaop.OpAMD64VPSRLVD256
		return true
	case ssaop.OpShiftRightUint64x2:
		v.Op = ssaop.OpAMD64VPSRLVQ128
		return true
	case ssaop.OpShiftRightUint64x4:
		v.Op = ssaop.OpAMD64VPSRLVQ256
		return true
	case ssaop.OpShiftRightUint64x8:
		v.Op = ssaop.OpAMD64VPSRLVQ512
		return true
	case ssaop.OpSignExt16to32:
		v.Op = ssaop.OpAMD64MOVWQSX
		return true
	case ssaop.OpSignExt16to64:
		v.Op = ssaop.OpAMD64MOVWQSX
		return true
	case ssaop.OpSignExt32to64:
		v.Op = ssaop.OpAMD64MOVLQSX
		return true
	case ssaop.OpSignExt8to16:
		v.Op = ssaop.OpAMD64MOVBQSX
		return true
	case ssaop.OpSignExt8to32:
		v.Op = ssaop.OpAMD64MOVBQSX
		return true
	case ssaop.OpSignExt8to64:
		v.Op = ssaop.OpAMD64MOVBQSX
		return true
	case ssaop.OpSlicemask:
		return rewriteValue_OpSlicemask(v)
	case ssaop.OpSpectreIndex:
		return rewriteValue_OpSpectreIndex(v)
	case ssaop.OpSpectreSliceIndex:
		return rewriteValue_OpSpectreSliceIndex(v)
	case ssaop.OpSqrt:
		v.Op = ssaop.OpAMD64SQRTSD
		return true
	case ssaop.OpSqrt32:
		v.Op = ssaop.OpAMD64SQRTSS
		return true
	case ssaop.OpSqrtFloat32x16:
		v.Op = ssaop.OpAMD64VSQRTPS512
		return true
	case ssaop.OpSqrtFloat32x4:
		v.Op = ssaop.OpAMD64VSQRTPS128
		return true
	case ssaop.OpSqrtFloat32x8:
		v.Op = ssaop.OpAMD64VSQRTPS256
		return true
	case ssaop.OpSqrtFloat64x2:
		v.Op = ssaop.OpAMD64VSQRTPD128
		return true
	case ssaop.OpSqrtFloat64x4:
		v.Op = ssaop.OpAMD64VSQRTPD256
		return true
	case ssaop.OpSqrtFloat64x8:
		v.Op = ssaop.OpAMD64VSQRTPD512
		return true
	case ssaop.OpStaticCall:
		v.Op = ssaop.OpAMD64CALLstatic
		return true
	case ssaop.OpStore:
		return rewriteValue_OpStore(v)
	case ssaop.OpStoreMasked16:
		return rewriteValue_OpStoreMasked16(v)
	case ssaop.OpStoreMasked32:
		return rewriteValue_OpStoreMasked32(v)
	case ssaop.OpStoreMasked64:
		return rewriteValue_OpStoreMasked64(v)
	case ssaop.OpStoreMasked8:
		return rewriteValue_OpStoreMasked8(v)
	case ssaop.OpSub16:
		v.Op = ssaop.OpAMD64SUBL
		return true
	case ssaop.OpSub32:
		v.Op = ssaop.OpAMD64SUBL
		return true
	case ssaop.OpSub32F:
		v.Op = ssaop.OpAMD64SUBSS
		return true
	case ssaop.OpSub64:
		v.Op = ssaop.OpAMD64SUBQ
		return true
	case ssaop.OpSub64F:
		v.Op = ssaop.OpAMD64SUBSD
		return true
	case ssaop.OpSub8:
		v.Op = ssaop.OpAMD64SUBL
		return true
	case ssaop.OpSubFloat32x16:
		v.Op = ssaop.OpAMD64VSUBPS512
		return true
	case ssaop.OpSubFloat32x4:
		v.Op = ssaop.OpAMD64VSUBPS128
		return true
	case ssaop.OpSubFloat32x8:
		v.Op = ssaop.OpAMD64VSUBPS256
		return true
	case ssaop.OpSubFloat64x2:
		v.Op = ssaop.OpAMD64VSUBPD128
		return true
	case ssaop.OpSubFloat64x4:
		v.Op = ssaop.OpAMD64VSUBPD256
		return true
	case ssaop.OpSubFloat64x8:
		v.Op = ssaop.OpAMD64VSUBPD512
		return true
	case ssaop.OpSubInt16x16:
		v.Op = ssaop.OpAMD64VPSUBW256
		return true
	case ssaop.OpSubInt16x32:
		v.Op = ssaop.OpAMD64VPSUBW512
		return true
	case ssaop.OpSubInt16x8:
		v.Op = ssaop.OpAMD64VPSUBW128
		return true
	case ssaop.OpSubInt32x16:
		v.Op = ssaop.OpAMD64VPSUBD512
		return true
	case ssaop.OpSubInt32x4:
		v.Op = ssaop.OpAMD64VPSUBD128
		return true
	case ssaop.OpSubInt32x8:
		v.Op = ssaop.OpAMD64VPSUBD256
		return true
	case ssaop.OpSubInt64x2:
		v.Op = ssaop.OpAMD64VPSUBQ128
		return true
	case ssaop.OpSubInt64x4:
		v.Op = ssaop.OpAMD64VPSUBQ256
		return true
	case ssaop.OpSubInt64x8:
		v.Op = ssaop.OpAMD64VPSUBQ512
		return true
	case ssaop.OpSubInt8x16:
		v.Op = ssaop.OpAMD64VPSUBB128
		return true
	case ssaop.OpSubInt8x32:
		v.Op = ssaop.OpAMD64VPSUBB256
		return true
	case ssaop.OpSubInt8x64:
		v.Op = ssaop.OpAMD64VPSUBB512
		return true
	case ssaop.OpSubPtr:
		v.Op = ssaop.OpAMD64SUBQ
		return true
	case ssaop.OpSubSaturatedInt16x16:
		v.Op = ssaop.OpAMD64VPSUBSW256
		return true
	case ssaop.OpSubSaturatedInt16x32:
		v.Op = ssaop.OpAMD64VPSUBSW512
		return true
	case ssaop.OpSubSaturatedInt16x8:
		v.Op = ssaop.OpAMD64VPSUBSW128
		return true
	case ssaop.OpSubSaturatedInt8x16:
		v.Op = ssaop.OpAMD64VPSUBSB128
		return true
	case ssaop.OpSubSaturatedInt8x32:
		v.Op = ssaop.OpAMD64VPSUBSB256
		return true
	case ssaop.OpSubSaturatedInt8x64:
		v.Op = ssaop.OpAMD64VPSUBSB512
		return true
	case ssaop.OpSubSaturatedUint16x16:
		v.Op = ssaop.OpAMD64VPSUBUSW256
		return true
	case ssaop.OpSubSaturatedUint16x32:
		v.Op = ssaop.OpAMD64VPSUBUSW512
		return true
	case ssaop.OpSubSaturatedUint16x8:
		v.Op = ssaop.OpAMD64VPSUBUSW128
		return true
	case ssaop.OpSubSaturatedUint8x16:
		v.Op = ssaop.OpAMD64VPSUBUSB128
		return true
	case ssaop.OpSubSaturatedUint8x32:
		v.Op = ssaop.OpAMD64VPSUBUSB256
		return true
	case ssaop.OpSubSaturatedUint8x64:
		v.Op = ssaop.OpAMD64VPSUBUSB512
		return true
	case ssaop.OpSubUint16x16:
		v.Op = ssaop.OpAMD64VPSUBW256
		return true
	case ssaop.OpSubUint16x32:
		v.Op = ssaop.OpAMD64VPSUBW512
		return true
	case ssaop.OpSubUint16x8:
		v.Op = ssaop.OpAMD64VPSUBW128
		return true
	case ssaop.OpSubUint32x16:
		v.Op = ssaop.OpAMD64VPSUBD512
		return true
	case ssaop.OpSubUint32x4:
		v.Op = ssaop.OpAMD64VPSUBD128
		return true
	case ssaop.OpSubUint32x8:
		v.Op = ssaop.OpAMD64VPSUBD256
		return true
	case ssaop.OpSubUint64x2:
		v.Op = ssaop.OpAMD64VPSUBQ128
		return true
	case ssaop.OpSubUint64x4:
		v.Op = ssaop.OpAMD64VPSUBQ256
		return true
	case ssaop.OpSubUint64x8:
		v.Op = ssaop.OpAMD64VPSUBQ512
		return true
	case ssaop.OpSubUint8x16:
		v.Op = ssaop.OpAMD64VPSUBB128
		return true
	case ssaop.OpSubUint8x32:
		v.Op = ssaop.OpAMD64VPSUBB256
		return true
	case ssaop.OpSubUint8x64:
		v.Op = ssaop.OpAMD64VPSUBB512
		return true
	case ssaop.OpSumOf8AbsDiffUint8x16:
		v.Op = ssaop.OpAMD64VPSADBW128
		return true
	case ssaop.OpSumOf8AbsDiffUint8x32:
		v.Op = ssaop.OpAMD64VPSADBW256
		return true
	case ssaop.OpSumOf8AbsDiffUint8x64:
		v.Op = ssaop.OpAMD64VPSADBW512
		return true
	case ssaop.OpTailCall:
		v.Op = ssaop.OpAMD64CALLtail
		return true
	case ssaop.OpTailCallInter:
		v.Op = ssaop.OpAMD64CALLtailinter
		return true
	case ssaop.OpTrunc:
		return rewriteValue_OpTrunc(v)
	case ssaop.OpTrunc16to8:
		v.Op = ssaop.OpCopy
		return true
	case ssaop.OpTrunc32to16:
		v.Op = ssaop.OpCopy
		return true
	case ssaop.OpTrunc32to8:
		v.Op = ssaop.OpCopy
		return true
	case ssaop.OpTrunc64to16:
		v.Op = ssaop.OpCopy
		return true
	case ssaop.OpTrunc64to32:
		v.Op = ssaop.OpCopy
		return true
	case ssaop.OpTrunc64to8:
		v.Op = ssaop.OpCopy
		return true
	case ssaop.OpTruncFloat32x4:
		return rewriteValue_OpTruncFloat32x4(v)
	case ssaop.OpTruncFloat32x8:
		return rewriteValue_OpTruncFloat32x8(v)
	case ssaop.OpTruncFloat64x2:
		return rewriteValue_OpTruncFloat64x2(v)
	case ssaop.OpTruncFloat64x4:
		return rewriteValue_OpTruncFloat64x4(v)
	case ssaop.OpTruncScaledFloat32x16:
		return rewriteValue_OpTruncScaledFloat32x16(v)
	case ssaop.OpTruncScaledFloat32x4:
		return rewriteValue_OpTruncScaledFloat32x4(v)
	case ssaop.OpTruncScaledFloat32x8:
		return rewriteValue_OpTruncScaledFloat32x8(v)
	case ssaop.OpTruncScaledFloat64x2:
		return rewriteValue_OpTruncScaledFloat64x2(v)
	case ssaop.OpTruncScaledFloat64x4:
		return rewriteValue_OpTruncScaledFloat64x4(v)
	case ssaop.OpTruncScaledFloat64x8:
		return rewriteValue_OpTruncScaledFloat64x8(v)
	case ssaop.OpTruncScaledResidueFloat32x16:
		return rewriteValue_OpTruncScaledResidueFloat32x16(v)
	case ssaop.OpTruncScaledResidueFloat32x4:
		return rewriteValue_OpTruncScaledResidueFloat32x4(v)
	case ssaop.OpTruncScaledResidueFloat32x8:
		return rewriteValue_OpTruncScaledResidueFloat32x8(v)
	case ssaop.OpTruncScaledResidueFloat64x2:
		return rewriteValue_OpTruncScaledResidueFloat64x2(v)
	case ssaop.OpTruncScaledResidueFloat64x4:
		return rewriteValue_OpTruncScaledResidueFloat64x4(v)
	case ssaop.OpTruncScaledResidueFloat64x8:
		return rewriteValue_OpTruncScaledResidueFloat64x8(v)
	case ssaop.OpTruncToInt16Int32x16:
		v.Op = ssaop.OpAMD64VPMOVDW256
		return true
	case ssaop.OpTruncToInt16Int32x4:
		v.Op = ssaop.OpAMD64VPMOVDW128_128
		return true
	case ssaop.OpTruncToInt16Int32x8:
		v.Op = ssaop.OpAMD64VPMOVDW128_256
		return true
	case ssaop.OpTruncToInt16Int64x2:
		v.Op = ssaop.OpAMD64VPMOVQW128_128
		return true
	case ssaop.OpTruncToInt16Int64x4:
		v.Op = ssaop.OpAMD64VPMOVQW128_256
		return true
	case ssaop.OpTruncToInt16Int64x8:
		v.Op = ssaop.OpAMD64VPMOVQW128_512
		return true
	case ssaop.OpTruncToInt32Int64x2:
		v.Op = ssaop.OpAMD64VPMOVQD128_128
		return true
	case ssaop.OpTruncToInt32Int64x4:
		v.Op = ssaop.OpAMD64VPMOVQD128_256
		return true
	case ssaop.OpTruncToInt32Int64x8:
		v.Op = ssaop.OpAMD64VPMOVQD256
		return true
	case ssaop.OpTruncToInt8Int16x16:
		v.Op = ssaop.OpAMD64VPMOVWB128_256
		return true
	case ssaop.OpTruncToInt8Int16x32:
		v.Op = ssaop.OpAMD64VPMOVWB256
		return true
	case ssaop.OpTruncToInt8Int16x8:
		v.Op = ssaop.OpAMD64VPMOVWB128_128
		return true
	case ssaop.OpTruncToInt8Int32x16:
		v.Op = ssaop.OpAMD64VPMOVDB128_512
		return true
	case ssaop.OpTruncToInt8Int32x4:
		v.Op = ssaop.OpAMD64VPMOVDB128_128
		return true
	case ssaop.OpTruncToInt8Int32x8:
		v.Op = ssaop.OpAMD64VPMOVDB128_256
		return true
	case ssaop.OpTruncToInt8Int64x2:
		v.Op = ssaop.OpAMD64VPMOVQB128_128
		return true
	case ssaop.OpTruncToInt8Int64x4:
		v.Op = ssaop.OpAMD64VPMOVQB128_256
		return true
	case ssaop.OpTruncToInt8Int64x8:
		v.Op = ssaop.OpAMD64VPMOVQB128_512
		return true
	case ssaop.OpTruncToUint16Uint32x16:
		v.Op = ssaop.OpAMD64VPMOVDW256
		return true
	case ssaop.OpTruncToUint16Uint32x4:
		v.Op = ssaop.OpAMD64VPMOVDW128_128
		return true
	case ssaop.OpTruncToUint16Uint32x8:
		v.Op = ssaop.OpAMD64VPMOVDW128_256
		return true
	case ssaop.OpTruncToUint16Uint64x2:
		v.Op = ssaop.OpAMD64VPMOVQW128_128
		return true
	case ssaop.OpTruncToUint16Uint64x4:
		v.Op = ssaop.OpAMD64VPMOVQW128_256
		return true
	case ssaop.OpTruncToUint16Uint64x8:
		v.Op = ssaop.OpAMD64VPMOVQW128_512
		return true
	case ssaop.OpTruncToUint32Uint64x2:
		v.Op = ssaop.OpAMD64VPMOVQD128_128
		return true
	case ssaop.OpTruncToUint32Uint64x4:
		v.Op = ssaop.OpAMD64VPMOVQD128_256
		return true
	case ssaop.OpTruncToUint32Uint64x8:
		v.Op = ssaop.OpAMD64VPMOVQD256
		return true
	case ssaop.OpTruncToUint8Uint16x16:
		v.Op = ssaop.OpAMD64VPMOVWB128_256
		return true
	case ssaop.OpTruncToUint8Uint16x32:
		v.Op = ssaop.OpAMD64VPMOVWB256
		return true
	case ssaop.OpTruncToUint8Uint16x8:
		v.Op = ssaop.OpAMD64VPMOVWB128_128
		return true
	case ssaop.OpTruncToUint8Uint32x16:
		v.Op = ssaop.OpAMD64VPMOVDB128_512
		return true
	case ssaop.OpTruncToUint8Uint32x4:
		v.Op = ssaop.OpAMD64VPMOVDB128_128
		return true
	case ssaop.OpTruncToUint8Uint32x8:
		v.Op = ssaop.OpAMD64VPMOVDB128_256
		return true
	case ssaop.OpTruncToUint8Uint64x2:
		v.Op = ssaop.OpAMD64VPMOVQB128_128
		return true
	case ssaop.OpTruncToUint8Uint64x4:
		v.Op = ssaop.OpAMD64VPMOVQB128_256
		return true
	case ssaop.OpTruncToUint8Uint64x8:
		v.Op = ssaop.OpAMD64VPMOVQB128_512
		return true
	case ssaop.OpWB:
		v.Op = ssaop.OpAMD64LoweredWB
		return true
	case ssaop.OpXor16:
		v.Op = ssaop.OpAMD64XORL
		return true
	case ssaop.OpXor32:
		v.Op = ssaop.OpAMD64XORL
		return true
	case ssaop.OpXor64:
		v.Op = ssaop.OpAMD64XORQ
		return true
	case ssaop.OpXor8:
		v.Op = ssaop.OpAMD64XORL
		return true
	case ssaop.OpXorInt16x16:
		v.Op = ssaop.OpAMD64VPXOR256
		return true
	case ssaop.OpXorInt16x32:
		v.Op = ssaop.OpAMD64VPXORD512
		return true
	case ssaop.OpXorInt16x8:
		v.Op = ssaop.OpAMD64VPXOR128
		return true
	case ssaop.OpXorInt32x16:
		v.Op = ssaop.OpAMD64VPXORD512
		return true
	case ssaop.OpXorInt32x4:
		v.Op = ssaop.OpAMD64VPXOR128
		return true
	case ssaop.OpXorInt32x8:
		v.Op = ssaop.OpAMD64VPXOR256
		return true
	case ssaop.OpXorInt64x2:
		v.Op = ssaop.OpAMD64VPXOR128
		return true
	case ssaop.OpXorInt64x4:
		v.Op = ssaop.OpAMD64VPXOR256
		return true
	case ssaop.OpXorInt64x8:
		v.Op = ssaop.OpAMD64VPXORQ512
		return true
	case ssaop.OpXorInt8x16:
		v.Op = ssaop.OpAMD64VPXOR128
		return true
	case ssaop.OpXorInt8x32:
		v.Op = ssaop.OpAMD64VPXOR256
		return true
	case ssaop.OpXorInt8x64:
		v.Op = ssaop.OpAMD64VPXORD512
		return true
	case ssaop.OpXorUint16x16:
		v.Op = ssaop.OpAMD64VPXOR256
		return true
	case ssaop.OpXorUint16x32:
		v.Op = ssaop.OpAMD64VPXORD512
		return true
	case ssaop.OpXorUint16x8:
		v.Op = ssaop.OpAMD64VPXOR128
		return true
	case ssaop.OpXorUint32x16:
		v.Op = ssaop.OpAMD64VPXORD512
		return true
	case ssaop.OpXorUint32x4:
		v.Op = ssaop.OpAMD64VPXOR128
		return true
	case ssaop.OpXorUint32x8:
		v.Op = ssaop.OpAMD64VPXOR256
		return true
	case ssaop.OpXorUint64x2:
		v.Op = ssaop.OpAMD64VPXOR128
		return true
	case ssaop.OpXorUint64x4:
		v.Op = ssaop.OpAMD64VPXOR256
		return true
	case ssaop.OpXorUint64x8:
		v.Op = ssaop.OpAMD64VPXORQ512
		return true
	case ssaop.OpXorUint8x16:
		v.Op = ssaop.OpAMD64VPXOR128
		return true
	case ssaop.OpXorUint8x32:
		v.Op = ssaop.OpAMD64VPXOR256
		return true
	case ssaop.OpXorUint8x64:
		v.Op = ssaop.OpAMD64VPXORD512
		return true
	case ssaop.OpZero:
		return rewriteValue_OpZero(v)
	case ssaop.OpZeroExt16to32:
		v.Op = ssaop.OpAMD64MOVWQZX
		return true
	case ssaop.OpZeroExt16to64:
		v.Op = ssaop.OpAMD64MOVWQZX
		return true
	case ssaop.OpZeroExt32to64:
		v.Op = ssaop.OpAMD64MOVLQZX
		return true
	case ssaop.OpZeroExt8to16:
		v.Op = ssaop.OpAMD64MOVBQZX
		return true
	case ssaop.OpZeroExt8to32:
		v.Op = ssaop.OpAMD64MOVBQZX
		return true
	case ssaop.OpZeroExt8to64:
		v.Op = ssaop.OpAMD64MOVBQZX
		return true
	case ssaop.OpZeroSIMD:
		return rewriteValue_OpZeroSIMD(v)
	case ssaop.OpblendInt8x16:
		v.Op = ssaop.OpAMD64VPBLENDVB128
		return true
	case ssaop.OpblendInt8x32:
		v.Op = ssaop.OpAMD64VPBLENDVB256
		return true
	case ssaop.OpblendMaskedInt16x32:
		return rewriteValue_OpblendMaskedInt16x32(v)
	case ssaop.OpblendMaskedInt32x16:
		return rewriteValue_OpblendMaskedInt32x16(v)
	case ssaop.OpblendMaskedInt64x8:
		return rewriteValue_OpblendMaskedInt64x8(v)
	case ssaop.OpblendMaskedInt8x64:
		return rewriteValue_OpblendMaskedInt8x64(v)
	case ssaop.Opbroadcast1To16Float32x4:
		v.Op = ssaop.OpAMD64VBROADCASTSS512
		return true
	case ssaop.Opbroadcast1To16Int16x8:
		v.Op = ssaop.OpAMD64VPBROADCASTW256
		return true
	case ssaop.Opbroadcast1To16Int32x4:
		v.Op = ssaop.OpAMD64VPBROADCASTD512
		return true
	case ssaop.Opbroadcast1To16Int8x16:
		v.Op = ssaop.OpAMD64VPBROADCASTB128
		return true
	case ssaop.Opbroadcast1To16MaskedFloat32x4:
		return rewriteValue_Opbroadcast1To16MaskedFloat32x4(v)
	case ssaop.Opbroadcast1To16MaskedInt16x8:
		return rewriteValue_Opbroadcast1To16MaskedInt16x8(v)
	case ssaop.Opbroadcast1To16MaskedInt32x4:
		return rewriteValue_Opbroadcast1To16MaskedInt32x4(v)
	case ssaop.Opbroadcast1To16MaskedInt8x16:
		return rewriteValue_Opbroadcast1To16MaskedInt8x16(v)
	case ssaop.Opbroadcast1To16MaskedUint16x8:
		return rewriteValue_Opbroadcast1To16MaskedUint16x8(v)
	case ssaop.Opbroadcast1To16MaskedUint32x4:
		return rewriteValue_Opbroadcast1To16MaskedUint32x4(v)
	case ssaop.Opbroadcast1To16MaskedUint8x16:
		return rewriteValue_Opbroadcast1To16MaskedUint8x16(v)
	case ssaop.Opbroadcast1To16Uint16x8:
		v.Op = ssaop.OpAMD64VPBROADCASTW256
		return true
	case ssaop.Opbroadcast1To16Uint32x4:
		v.Op = ssaop.OpAMD64VPBROADCASTD512
		return true
	case ssaop.Opbroadcast1To16Uint8x16:
		v.Op = ssaop.OpAMD64VPBROADCASTB128
		return true
	case ssaop.Opbroadcast1To2Float64x2:
		v.Op = ssaop.OpAMD64VPBROADCASTQ128
		return true
	case ssaop.Opbroadcast1To2Int64x2:
		v.Op = ssaop.OpAMD64VPBROADCASTQ128
		return true
	case ssaop.Opbroadcast1To2MaskedFloat64x2:
		return rewriteValue_Opbroadcast1To2MaskedFloat64x2(v)
	case ssaop.Opbroadcast1To2MaskedInt64x2:
		return rewriteValue_Opbroadcast1To2MaskedInt64x2(v)
	case ssaop.Opbroadcast1To2MaskedUint64x2:
		return rewriteValue_Opbroadcast1To2MaskedUint64x2(v)
	case ssaop.Opbroadcast1To2Uint64x2:
		v.Op = ssaop.OpAMD64VPBROADCASTQ128
		return true
	case ssaop.Opbroadcast1To32Int16x8:
		v.Op = ssaop.OpAMD64VPBROADCASTW512
		return true
	case ssaop.Opbroadcast1To32Int8x16:
		v.Op = ssaop.OpAMD64VPBROADCASTB256
		return true
	case ssaop.Opbroadcast1To32MaskedInt16x8:
		return rewriteValue_Opbroadcast1To32MaskedInt16x8(v)
	case ssaop.Opbroadcast1To32MaskedInt8x16:
		return rewriteValue_Opbroadcast1To32MaskedInt8x16(v)
	case ssaop.Opbroadcast1To32MaskedUint16x8:
		return rewriteValue_Opbroadcast1To32MaskedUint16x8(v)
	case ssaop.Opbroadcast1To32MaskedUint8x16:
		return rewriteValue_Opbroadcast1To32MaskedUint8x16(v)
	case ssaop.Opbroadcast1To32Uint16x8:
		v.Op = ssaop.OpAMD64VPBROADCASTW512
		return true
	case ssaop.Opbroadcast1To32Uint8x16:
		v.Op = ssaop.OpAMD64VPBROADCASTB256
		return true
	case ssaop.Opbroadcast1To4Float32x4:
		v.Op = ssaop.OpAMD64VBROADCASTSS128
		return true
	case ssaop.Opbroadcast1To4Float64x2:
		v.Op = ssaop.OpAMD64VBROADCASTSD256
		return true
	case ssaop.Opbroadcast1To4Int32x4:
		v.Op = ssaop.OpAMD64VPBROADCASTD128
		return true
	case ssaop.Opbroadcast1To4Int64x2:
		v.Op = ssaop.OpAMD64VPBROADCASTQ256
		return true
	case ssaop.Opbroadcast1To4MaskedFloat32x4:
		return rewriteValue_Opbroadcast1To4MaskedFloat32x4(v)
	case ssaop.Opbroadcast1To4MaskedFloat64x2:
		return rewriteValue_Opbroadcast1To4MaskedFloat64x2(v)
	case ssaop.Opbroadcast1To4MaskedInt32x4:
		return rewriteValue_Opbroadcast1To4MaskedInt32x4(v)
	case ssaop.Opbroadcast1To4MaskedInt64x2:
		return rewriteValue_Opbroadcast1To4MaskedInt64x2(v)
	case ssaop.Opbroadcast1To4MaskedUint32x4:
		return rewriteValue_Opbroadcast1To4MaskedUint32x4(v)
	case ssaop.Opbroadcast1To4MaskedUint64x2:
		return rewriteValue_Opbroadcast1To4MaskedUint64x2(v)
	case ssaop.Opbroadcast1To4Uint32x4:
		v.Op = ssaop.OpAMD64VPBROADCASTD128
		return true
	case ssaop.Opbroadcast1To4Uint64x2:
		v.Op = ssaop.OpAMD64VPBROADCASTQ256
		return true
	case ssaop.Opbroadcast1To64Int8x16:
		v.Op = ssaop.OpAMD64VPBROADCASTB512
		return true
	case ssaop.Opbroadcast1To64MaskedInt8x16:
		return rewriteValue_Opbroadcast1To64MaskedInt8x16(v)
	case ssaop.Opbroadcast1To64MaskedUint8x16:
		return rewriteValue_Opbroadcast1To64MaskedUint8x16(v)
	case ssaop.Opbroadcast1To64Uint8x16:
		v.Op = ssaop.OpAMD64VPBROADCASTB512
		return true
	case ssaop.Opbroadcast1To8Float32x4:
		v.Op = ssaop.OpAMD64VBROADCASTSS256
		return true
	case ssaop.Opbroadcast1To8Float64x2:
		v.Op = ssaop.OpAMD64VBROADCASTSD512
		return true
	case ssaop.Opbroadcast1To8Int16x8:
		v.Op = ssaop.OpAMD64VPBROADCASTW128
		return true
	case ssaop.Opbroadcast1To8Int32x4:
		v.Op = ssaop.OpAMD64VPBROADCASTD256
		return true
	case ssaop.Opbroadcast1To8Int64x2:
		v.Op = ssaop.OpAMD64VPBROADCASTQ512
		return true
	case ssaop.Opbroadcast1To8MaskedFloat32x4:
		return rewriteValue_Opbroadcast1To8MaskedFloat32x4(v)
	case ssaop.Opbroadcast1To8MaskedFloat64x2:
		return rewriteValue_Opbroadcast1To8MaskedFloat64x2(v)
	case ssaop.Opbroadcast1To8MaskedInt16x8:
		return rewriteValue_Opbroadcast1To8MaskedInt16x8(v)
	case ssaop.Opbroadcast1To8MaskedInt32x4:
		return rewriteValue_Opbroadcast1To8MaskedInt32x4(v)
	case ssaop.Opbroadcast1To8MaskedInt64x2:
		return rewriteValue_Opbroadcast1To8MaskedInt64x2(v)
	case ssaop.Opbroadcast1To8MaskedUint16x8:
		return rewriteValue_Opbroadcast1To8MaskedUint16x8(v)
	case ssaop.Opbroadcast1To8MaskedUint32x4:
		return rewriteValue_Opbroadcast1To8MaskedUint32x4(v)
	case ssaop.Opbroadcast1To8MaskedUint64x2:
		return rewriteValue_Opbroadcast1To8MaskedUint64x2(v)
	case ssaop.Opbroadcast1To8Uint16x8:
		v.Op = ssaop.OpAMD64VPBROADCASTW128
		return true
	case ssaop.Opbroadcast1To8Uint32x4:
		v.Op = ssaop.OpAMD64VPBROADCASTD256
		return true
	case ssaop.Opbroadcast1To8Uint64x2:
		v.Op = ssaop.OpAMD64VPBROADCASTQ512
		return true
	case ssaop.OpcarrylessMultiplyUint64x2:
		v.Op = ssaop.OpAMD64VPCLMULQDQ128
		return true
	case ssaop.OpcarrylessMultiplyUint64x4:
		v.Op = ssaop.OpAMD64VPCLMULQDQ256
		return true
	case ssaop.OpcarrylessMultiplyUint64x8:
		v.Op = ssaop.OpAMD64VPCLMULQDQ512
		return true
	case ssaop.OpconcatSelectedConstantFloat32x4:
		v.Op = ssaop.OpAMD64VSHUFPS128
		return true
	case ssaop.OpconcatSelectedConstantFloat64x2:
		v.Op = ssaop.OpAMD64VSHUFPD128
		return true
	case ssaop.OpconcatSelectedConstantGroupedFloat32x16:
		v.Op = ssaop.OpAMD64VSHUFPS512
		return true
	case ssaop.OpconcatSelectedConstantGroupedFloat32x8:
		v.Op = ssaop.OpAMD64VSHUFPS256
		return true
	case ssaop.OpconcatSelectedConstantGroupedFloat64x4:
		v.Op = ssaop.OpAMD64VSHUFPD256
		return true
	case ssaop.OpconcatSelectedConstantGroupedFloat64x8:
		v.Op = ssaop.OpAMD64VSHUFPD512
		return true
	case ssaop.OpconcatSelectedConstantGroupedInt32x16:
		v.Op = ssaop.OpAMD64VSHUFPS512
		return true
	case ssaop.OpconcatSelectedConstantGroupedInt32x8:
		v.Op = ssaop.OpAMD64VSHUFPS256
		return true
	case ssaop.OpconcatSelectedConstantGroupedInt64x4:
		v.Op = ssaop.OpAMD64VSHUFPD256
		return true
	case ssaop.OpconcatSelectedConstantGroupedInt64x8:
		v.Op = ssaop.OpAMD64VSHUFPD512
		return true
	case ssaop.OpconcatSelectedConstantGroupedUint32x16:
		v.Op = ssaop.OpAMD64VSHUFPS512
		return true
	case ssaop.OpconcatSelectedConstantGroupedUint32x8:
		v.Op = ssaop.OpAMD64VSHUFPS256
		return true
	case ssaop.OpconcatSelectedConstantGroupedUint64x4:
		v.Op = ssaop.OpAMD64VSHUFPD256
		return true
	case ssaop.OpconcatSelectedConstantGroupedUint64x8:
		v.Op = ssaop.OpAMD64VSHUFPD512
		return true
	case ssaop.OpconcatSelectedConstantInt32x4:
		v.Op = ssaop.OpAMD64VSHUFPS128
		return true
	case ssaop.OpconcatSelectedConstantInt64x2:
		v.Op = ssaop.OpAMD64VSHUFPD128
		return true
	case ssaop.OpconcatSelectedConstantUint32x4:
		v.Op = ssaop.OpAMD64VSHUFPS128
		return true
	case ssaop.OpconcatSelectedConstantUint64x2:
		v.Op = ssaop.OpAMD64VSHUFPD128
		return true
	case ssaop.OppermuteScalarsGroupedInt32x16:
		v.Op = ssaop.OpAMD64VPSHUFD512
		return true
	case ssaop.OppermuteScalarsGroupedInt32x8:
		v.Op = ssaop.OpAMD64VPSHUFD256
		return true
	case ssaop.OppermuteScalarsGroupedUint32x16:
		v.Op = ssaop.OpAMD64VPSHUFD512
		return true
	case ssaop.OppermuteScalarsGroupedUint32x8:
		v.Op = ssaop.OpAMD64VPSHUFD256
		return true
	case ssaop.OppermuteScalarsHiGroupedInt16x16:
		v.Op = ssaop.OpAMD64VPSHUFHW256
		return true
	case ssaop.OppermuteScalarsHiGroupedInt16x32:
		v.Op = ssaop.OpAMD64VPSHUFHW512
		return true
	case ssaop.OppermuteScalarsHiGroupedUint16x16:
		v.Op = ssaop.OpAMD64VPSHUFHW256
		return true
	case ssaop.OppermuteScalarsHiGroupedUint16x32:
		v.Op = ssaop.OpAMD64VPSHUFHW512
		return true
	case ssaop.OppermuteScalarsHiInt16x8:
		v.Op = ssaop.OpAMD64VPSHUFHW128
		return true
	case ssaop.OppermuteScalarsHiUint16x8:
		v.Op = ssaop.OpAMD64VPSHUFHW128
		return true
	case ssaop.OppermuteScalarsInt32x4:
		v.Op = ssaop.OpAMD64VPSHUFD128
		return true
	case ssaop.OppermuteScalarsLoGroupedInt16x16:
		v.Op = ssaop.OpAMD64VPSHUFLW256
		return true
	case ssaop.OppermuteScalarsLoGroupedInt16x32:
		v.Op = ssaop.OpAMD64VPSHUFLW512
		return true
	case ssaop.OppermuteScalarsLoGroupedUint16x16:
		v.Op = ssaop.OpAMD64VPSHUFLW256
		return true
	case ssaop.OppermuteScalarsLoGroupedUint16x32:
		v.Op = ssaop.OpAMD64VPSHUFLW512
		return true
	case ssaop.OppermuteScalarsLoInt16x8:
		v.Op = ssaop.OpAMD64VPSHUFLW128
		return true
	case ssaop.OppermuteScalarsLoUint16x8:
		v.Op = ssaop.OpAMD64VPSHUFLW128
		return true
	case ssaop.OppermuteScalarsUint32x4:
		v.Op = ssaop.OpAMD64VPSHUFD128
		return true
	case ssaop.OpternInt32x16:
		v.Op = ssaop.OpAMD64VPTERNLOGD512
		return true
	case ssaop.OpternInt32x4:
		v.Op = ssaop.OpAMD64VPTERNLOGD128
		return true
	case ssaop.OpternInt32x8:
		v.Op = ssaop.OpAMD64VPTERNLOGD256
		return true
	case ssaop.OpternInt64x2:
		v.Op = ssaop.OpAMD64VPTERNLOGQ128
		return true
	case ssaop.OpternInt64x4:
		v.Op = ssaop.OpAMD64VPTERNLOGQ256
		return true
	case ssaop.OpternInt64x8:
		v.Op = ssaop.OpAMD64VPTERNLOGQ512
		return true
	case ssaop.OpternUint32x16:
		v.Op = ssaop.OpAMD64VPTERNLOGD512
		return true
	case ssaop.OpternUint32x4:
		v.Op = ssaop.OpAMD64VPTERNLOGD128
		return true
	case ssaop.OpternUint32x8:
		v.Op = ssaop.OpAMD64VPTERNLOGD256
		return true
	case ssaop.OpternUint64x2:
		v.Op = ssaop.OpAMD64VPTERNLOGQ128
		return true
	case ssaop.OpternUint64x4:
		v.Op = ssaop.OpAMD64VPTERNLOGQ256
		return true
	case ssaop.OpternUint64x8:
		v.Op = ssaop.OpAMD64VPTERNLOGQ512
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADCQ(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ADCQ x (MOVQconst [c]) carry)
	// cond: ssa.Is32Bit(c)
	// result: (ADCQconst x [int32(c)] carry)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1.AuxInt)
			carry := v_2
			if !(ssa.Is32Bit(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADCQconst)
			v.AuxInt = ssa.Int32ToAuxInt(int32(c))
			v.AddArg2(x, carry)
			return true
		}
		break
	}
	// match: (ADCQ x y (FlagEQ))
	// result: (ADDQcarry x y)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQcarry)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADCQ x y (InvertFlags f))
	// result: (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		f := v_2.Args[0]
		v.Reset(ssaop.OpAMD64ADCQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBQZX, types.Types[types.TUINT32])
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64SETA, types.Types[types.TUINT8])
		v3.AddArg(f)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg(v1)
		v.AddArg3(x, y, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADCQconst(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ADCQconst x [c] (FlagEQ))
	// result: (ADDQconstcarry x [c])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconstcarry)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (ADCQconst x [c] (InvertFlags f))
	// result: (ADCQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		f := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ADCQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBQZX, types.Types[types.TUINT32])
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64SETA, types.Types[types.TUINT8])
		v3.AddArg(f)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg(v1)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDBconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDBconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ADDBconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ADDBconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDBconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDL (SHRLconst [1] x) (SHRLconst [1] x))
	// result: (ANDLconst [-2] x)
	for {
		if v_0.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(v_0.AuxInt) != 1 {
			break
		}
		x := v_0.Args[0]
		if v_1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(v_1.AuxInt) != 1 || x != v_1.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(-2)
		v.AddArg(x)
		return true
	}
	// match: (ADDL x (MOVLconst [c]))
	// result: (ADDLconst [c] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			v.Reset(ssaop.OpAMD64ADDLconst)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ADDL x (SHLLconst [3] y))
	// result: (LEAL8 x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(v_1.AuxInt) != 3 {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64LEAL8)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDL x (SHLLconst [2] y))
	// result: (LEAL4 x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(v_1.AuxInt) != 2 {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64LEAL4)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDL x (ADDL y y))
	// result: (LEAL2 x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64ADDL {
				continue
			}
			y := v_1.Args[1]
			if y != v_1.Args[0] {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAL2)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDL x (ADDL x y))
	// result: (LEAL2 y x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64ADDL {
				continue
			}
			_ = v_1.Args[1]
			v_1_0 := v_1.Args[0]
			v_1_1 := v_1.Args[1]
			for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 {
				if x != v_1_0 {
					continue
				}
				y := v_1_1
				v.Reset(ssaop.OpAMD64LEAL2)
				v.AddArg2(y, x)
				return true
			}
		}
		break
	}
	// match: (ADDL (ADDLconst [c] x) y)
	// result: (LEAL1 [c] x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64ADDLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_0.Args[0]
			y := v_1
			v.Reset(ssaop.OpAMD64LEAL1)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDL x (LEAL [c] {s} y))
	// cond: x.Op != ssaop.OpSB && y.Op != ssaop.OpSB
	// result: (LEAL1 [c] {s} x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64LEAL {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			s := ssa.AuxToSym(v_1.Aux)
			y := v_1.Args[0]
			if !(x.Op != ssaop.OpSB && y.Op != ssaop.OpSB) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAL1)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDL x (NEGL y))
	// result: (SUBL x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64NEGL {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64SUBL)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDL x l:(MOVLload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (ADDLload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVLload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADDLload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ADDLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ADDLconst [c] (ADDL x y))
	// result: (LEAL1 [c] x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDL {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64LEAL1)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDLconst [c] (ADDL x x))
	// result: (LEAL1 [c] x x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDL {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL1)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg2(x, x)
		return true
	}
	// match: (ADDLconst [c] (LEAL [d] {s} x))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAL [c+d] {s} x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAL {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg(x)
		return true
	}
	// match: (ADDLconst [c] (LEAL1 [d] {s} x y))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAL1 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAL1 {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL1)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDLconst [c] (LEAL2 [d] {s} x y))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAL2 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAL2 {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL2)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDLconst [c] (LEAL4 [d] {s} x y))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAL4 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAL4 {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL4)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDLconst [c] (LEAL8 [d] {s} x y))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAL8 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAL8 {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL8)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDLconst [0] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (ADDLconst [c] (MOVLconst [d]))
	// result: (MOVLconst [c+d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		return true
	}
	// match: (ADDLconst [c] (ADDLconst [d] x))
	// result: (ADDLconst [c+d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ADDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.AddArg(x)
		return true
	}
	// match: (ADDLconst [off] x:(SP))
	// result: (LEAL [off] x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if x.Op != ssaop.OpSP {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDLconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ADDLconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ADDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDLconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ADDLload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ADDLload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ADDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDLload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ADDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
	// result: (ADDL x (MOVLf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSSstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ADDL)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVLf2i, typ.UInt32)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDLlock(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDLlock [off] {sym} ptr n:(NEGL val) mem)
	// cond: n.Uses == 1
	// result: (SUBLlock [off] {sym} ptr val mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		n := v_1
		if n.Op != ssaop.OpAMD64NEGL {
			break
		}
		val := n.Args[0]
		mem := v_2
		if !(n.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBLlock)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (ADDLlock [off] {sym} ptr (MOVLconst [1]) mem)
	// result: (INCLlock [off] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_1.AuxInt) != 1 {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64INCLlock)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (ADDLlock [off] {sym} ptr (MOVLconst [-1]) mem)
	// result: (DECLlock [off] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_1.AuxInt) != -1 {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64DECLlock)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDLmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ADDLmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (ADDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDLmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ADDQ x (MOVBQZX (SETB flags)))
	// result: (Select0 (ADCQconst [0] x flags))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := v_1_0.Args[0]
			v.Reset(ssaop.OpSelect0)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ADCQconst, types.NewTuple(typ.UInt64, types.TypeFlags))
			v0.AuxInt = ssa.Int32ToAuxInt(0)
			v0.AddArg2(x, flags)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (ADDQ (SHRQconst [1] x) (SHRQconst [1] x))
	// result: (ANDQconst [-2] x)
	for {
		if v_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(v_0.AuxInt) != 1 {
			break
		}
		x := v_0.Args[0]
		if v_1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(v_1.AuxInt) != 1 || x != v_1.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(-2)
		v.AddArg(x)
		return true
	}
	// match: (ADDQ x (MOVQconst <t> [c]))
	// cond: ssa.Is32Bit(c) && !t.IsPtr()
	// result: (ADDQconst [int32(c)] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			t := v_1.Type
			c := ssa.AuxIntToInt64(v_1.AuxInt)
			if !(ssa.Is32Bit(c) && !t.IsPtr()) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADDQconst)
			v.AuxInt = ssa.Int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ADDQ x (MOVLconst [c]))
	// result: (ADDQconst [c] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			v.Reset(ssaop.OpAMD64ADDQconst)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ADDQ x (SHLQconst [3] y))
	// result: (LEAQ8 x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(v_1.AuxInt) != 3 {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64LEAQ8)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDQ x (SHLQconst [2] y))
	// result: (LEAQ4 x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(v_1.AuxInt) != 2 {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64LEAQ4)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDQ x (ADDQ y y))
	// result: (LEAQ2 x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64ADDQ {
				continue
			}
			y := v_1.Args[1]
			if y != v_1.Args[0] {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAQ2)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDQ x (ADDQ x y))
	// result: (LEAQ2 y x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64ADDQ {
				continue
			}
			_ = v_1.Args[1]
			v_1_0 := v_1.Args[0]
			v_1_1 := v_1.Args[1]
			for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 {
				if x != v_1_0 {
					continue
				}
				y := v_1_1
				v.Reset(ssaop.OpAMD64LEAQ2)
				v.AddArg2(y, x)
				return true
			}
		}
		break
	}
	// match: (ADDQ (ADDQconst [c] x) y)
	// result: (LEAQ1 [c] x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64ADDQconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_0.Args[0]
			y := v_1
			v.Reset(ssaop.OpAMD64LEAQ1)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDQ x (LEAQ [c] {s} y))
	// cond: x.Op != ssaop.OpSB && y.Op != ssaop.OpSB
	// result: (LEAQ1 [c] {s} x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64LEAQ {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			s := ssa.AuxToSym(v_1.Aux)
			y := v_1.Args[0]
			if !(x.Op != ssaop.OpSB && y.Op != ssaop.OpSB) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAQ1)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDQ x (NEGQ y))
	// result: (SUBQ x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64NEGQ {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64SUBQ)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ADDQ x l:(MOVQload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (ADDQload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVQload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADDQload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ADDQcarry(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDQcarry x (MOVQconst [c]))
	// cond: ssa.Is32Bit(c)
	// result: (ADDQconstcarry x [int32(c)])
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1.AuxInt)
			if !(ssa.Is32Bit(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADDQconstcarry)
			v.AuxInt = ssa.Int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ADDQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ADDQconst [c] (ADDQ x y))
	// result: (LEAQ1 [c] x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDQ {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64LEAQ1)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDQconst [c] (ADDQ x x))
	// result: (LEAQ1 [c] x x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDQ {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ1)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg2(x, x)
		return true
	}
	// match: (ADDQconst [c] (LEAQ [d] {s} x))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAQ [c+d] {s} x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg(x)
		return true
	}
	// match: (ADDQconst [c] (LEAQ1 [d] {s} x y))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAQ1 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAQ1 {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ1)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDQconst [c] (LEAQ2 [d] {s} x y))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAQ2 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAQ2 {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ2)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDQconst [c] (LEAQ4 [d] {s} x y))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAQ4 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAQ4 {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ4)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDQconst [c] (LEAQ8 [d] {s} x y))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAQ8 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64LEAQ8 {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		s := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ8)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (ADDQconst [0] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (ADDQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [int64(c)+d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(c) + d)
		return true
	}
	// match: (ADDQconst [c] (ADDQconst [d] x))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (ADDQconst [c+d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.AddArg(x)
		return true
	}
	// match: (ADDQconst [off] x:(SP))
	// result: (LEAQ [off] x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if x.Op != ssaop.OpSP {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDQconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ADDQconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ADDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDQconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ADDQload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ADDQload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ADDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDQload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ADDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
	// result: (ADDQ x (MOVQf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSDstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQ)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVQf2i, typ.UInt64)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDQlock(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDQlock [off] {sym} ptr n:(NEGQ val) mem)
	// cond: n.Uses == 1
	// result: (SUBQlock [off] {sym} ptr val mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		n := v_1
		if n.Op != ssaop.OpAMD64NEGQ {
			break
		}
		val := n.Args[0]
		mem := v_2
		if !(n.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQlock)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (ADDQlock [off] {sym} ptr (MOVQconst [1]) mem)
	// result: (INCQlock [off] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_1.AuxInt) != 1 {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64INCQlock)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (ADDQlock [off] {sym} ptr (MOVQconst [-1]) mem)
	// result: (DECQlock [off] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_1.AuxInt) != -1 {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64DECQlock)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDQmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ADDQmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (ADDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDQmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDSD(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDSD x l:(MOVSDload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (ADDSDload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVSDload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADDSDload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	// match: (ADDSD (MULSD x y) z)
	// cond: buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)
	// result: (VFMADD231SD z x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MULSD {
				continue
			}
			y := v_0.Args[1]
			x := v_0.Args[0]
			z := v_1
			if !(buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VFMADD231SD)
			v.AddArg3(z, x, y)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ADDSDload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ADDSDload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ADDSDload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ADDSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDSDload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ADDSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _))
	// result: (ADDSD x (MOVQi2f y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVQstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ADDSD)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVQi2f, typ.Float64)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDSS(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDSS x l:(MOVSSload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (ADDSSload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVSSload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADDSSload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	// match: (ADDSS (MULSS x y) z)
	// cond: buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)
	// result: (VFMADD231SS z x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MULSS {
				continue
			}
			y := v_0.Args[1]
			x := v_0.Args[0]
			z := v_1
			if !(buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VFMADD231SS)
			v.AddArg3(z, x, y)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ADDSSload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ADDSSload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ADDSSload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ADDSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDSSload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ADDSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _))
	// result: (ADDSS x (MOVLi2f y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVLstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ADDSS)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVLi2f, typ.Float32)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ADDWconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ADDWconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ADDWconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ADDWconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ADDWconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDBconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ANDBconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ANDBconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ANDBconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ANDBconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ANDL (NOTL (SHLL (MOVLconst [1]) y)) x)
	// result: (BTRL x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64NOTL {
				continue
			}
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SHLL {
				continue
			}
			y := v_0_0.Args[1]
			v_0_0_0 := v_0_0.Args[0]
			if v_0_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0_0_0.AuxInt) != 1 {
				continue
			}
			x := v_1
			v.Reset(ssaop.OpAMD64BTRL)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ANDL x (MOVLconst [c]))
	// result: (ANDLconst [c] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			v.Reset(ssaop.OpAMD64ANDLconst)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ANDL x x)
	// result: x
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (ANDL x l:(MOVLload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (ANDLload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVLload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ANDLload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	// match: (ANDL x (NOTL y))
	// cond: buildcfg.GOAMD64 >= 3
	// result: (ANDNL x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64NOTL {
				continue
			}
			y := v_1.Args[0]
			if !(buildcfg.GOAMD64 >= 3) {
				continue
			}
			v.Reset(ssaop.OpAMD64ANDNL)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ANDL x (NEGL x))
	// cond: buildcfg.GOAMD64 >= 3
	// result: (BLSIL x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64NEGL || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) {
				continue
			}
			v.Reset(ssaop.OpAMD64BLSIL)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ANDL <t> x (ADDLconst [-1] x))
	// cond: buildcfg.GOAMD64 >= 3
	// result: (Select0 <t> (BLSRL x))
	for {
		t := v.Type
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64ADDLconst || ssa.AuxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) {
				continue
			}
			v.Reset(ssaop.OpSelect0)
			v.Type = t
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BLSRL, types.NewTuple(typ.UInt32, types.TypeFlags))
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ANDLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ANDLconst [c] (ANDLconst [d] x))
	// result: (ANDLconst [c & d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c & d)
		v.AddArg(x)
		return true
	}
	// match: (ANDLconst [ 0xFF] x)
	// result: (MOVBQZX x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0xFF {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64MOVBQZX)
		v.AddArg(x)
		return true
	}
	// match: (ANDLconst [0xFFFF] x)
	// result: (MOVWQZX x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0xFFFF {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64MOVWQZX)
		v.AddArg(x)
		return true
	}
	// match: (ANDLconst [0] _)
	// result: (MOVLconst [0])
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (ANDLconst [-1] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != -1 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (ANDLconst [c] (MOVLconst [d]))
	// result: (MOVLconst [c&d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c & d)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDLconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ANDLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ANDLconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ANDLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ANDLconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ANDLload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ANDLload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ANDLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ANDLload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ANDLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
	// result: (ANDL x (MOVLf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSSstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVLf2i, typ.UInt32)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDLmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ANDLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ANDLmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (ANDLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ANDLmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDNL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ANDNL x (SHLL (MOVLconst [1]) y))
	// result: (BTRL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64SHLL {
			break
		}
		y := v_1.Args[1]
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_1_0.AuxInt) != 1 {
			break
		}
		v.Reset(ssaop.OpAMD64BTRL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDNQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ANDNQ x (SHLQ (MOVQconst [1]) y))
	// result: (BTRQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64SHLQ {
			break
		}
		y := v_1.Args[1]
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_1_0.AuxInt) != 1 {
			break
		}
		v.Reset(ssaop.OpAMD64BTRQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ANDQ (NOTQ (SHLQ (MOVQconst [1]) y)) x)
	// result: (BTRQ x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64NOTQ {
				continue
			}
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SHLQ {
				continue
			}
			y := v_0_0.Args[1]
			v_0_0_0 := v_0_0.Args[0]
			if v_0_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_0_0_0.AuxInt) != 1 {
				continue
			}
			x := v_1
			v.Reset(ssaop.OpAMD64BTRQ)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ANDQ (MOVQconst [c]) x)
	// cond: ssa.IsPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31
	// result: (BTRQconst [int8(ssa.Log64u(uint64(^c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_0.AuxInt)
			x := v_1
			if !(ssa.IsPowerOfTwo(uint64(^c)) && uint64(^c) >= 1<<31) {
				continue
			}
			v.Reset(ssaop.OpAMD64BTRQconst)
			v.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(^c))))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ANDQ x (MOVQconst [c]))
	// cond: ssa.Is32Bit(c)
	// result: (ANDQconst [int32(c)] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1.AuxInt)
			if !(ssa.Is32Bit(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ANDQconst)
			v.AuxInt = ssa.Int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ANDQ x x)
	// result: x
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (ANDQ x l:(MOVQload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (ANDQload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVQload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ANDQload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	// match: (ANDQ x (NOTQ y))
	// cond: buildcfg.GOAMD64 >= 3
	// result: (ANDNQ x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64NOTQ {
				continue
			}
			y := v_1.Args[0]
			if !(buildcfg.GOAMD64 >= 3) {
				continue
			}
			v.Reset(ssaop.OpAMD64ANDNQ)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ANDQ x (NEGQ x))
	// cond: buildcfg.GOAMD64 >= 3
	// result: (BLSIQ x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64NEGQ || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) {
				continue
			}
			v.Reset(ssaop.OpAMD64BLSIQ)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ANDQ <t> x (ADDQconst [-1] x))
	// cond: buildcfg.GOAMD64 >= 3
	// result: (Select0 <t> (BLSRQ x))
	for {
		t := v.Type
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64ADDQconst || ssa.AuxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) {
				continue
			}
			v.Reset(ssaop.OpSelect0)
			v.Type = t
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BLSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ANDQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ANDQconst [c] (ANDQconst [d] x))
	// result: (ANDQconst [c & d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c & d)
		v.AddArg(x)
		return true
	}
	// match: (ANDQconst [ 0xFF] x)
	// result: (MOVBQZX x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0xFF {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64MOVBQZX)
		v.AddArg(x)
		return true
	}
	// match: (ANDQconst [0xFFFF] x)
	// result: (MOVWQZX x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0xFFFF {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64MOVWQZX)
		v.AddArg(x)
		return true
	}
	// match: (ANDQconst [0] _)
	// result: (MOVLconst [0])
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (ANDQconst [-1] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != -1 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (ANDQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [int64(c)&d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(c) & d)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDQconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ANDQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ANDQconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ANDQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ANDQconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ANDQload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ANDQload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ANDQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ANDQload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ANDQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
	// result: (ANDQ x (MOVQf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSDstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVQf2i, typ.UInt64)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDQmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ANDQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ANDQmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (ANDQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ANDQmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ANDWconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ANDWconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ANDWconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ANDWconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ANDWconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64AddTupleFirst32(v *ssa.Value) bool {
	// match: (AddTupleFirst32 _ _)
	// cond: v.Uses == 0
	// result: (Invalid)
	for {
		if !(v.Uses == 0) {
			break
		}
		v.Reset(ssaop.OpInvalid)
		return true
	}
	return false
}
func rewriteValue_OpAMD64AddTupleFirst64(v *ssa.Value) bool {
	// match: (AddTupleFirst64 _ _)
	// cond: v.Uses == 0
	// result: (Invalid)
	for {
		if !(v.Uses == 0) {
			break
		}
		v.Reset(ssaop.OpInvalid)
		return true
	}
	return false
}
func rewriteValue_OpAMD64BSFQ(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (BSFQ (ORQconst <t> [1<<8] (MOVBQZX x)))
	// result: (BSFQ (ORQconst <t> [1<<8] x))
	for {
		if v_0.Op != ssaop.OpAMD64ORQconst {
			break
		}
		t := v_0.Type
		if ssa.AuxIntToInt32(v_0.AuxInt) != 1<<8 {
			break
		}
		v_0_0 := v_0.Args[0]
		if v_0_0.Op != ssaop.OpAMD64MOVBQZX {
			break
		}
		x := v_0_0.Args[0]
		v.Reset(ssaop.OpAMD64BSFQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORQconst, t)
		v0.AuxInt = ssa.Int32ToAuxInt(1 << 8)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (BSFQ (ORQconst <t> [1<<16] (MOVWQZX x)))
	// result: (BSFQ (ORQconst <t> [1<<16] x))
	for {
		if v_0.Op != ssaop.OpAMD64ORQconst {
			break
		}
		t := v_0.Type
		if ssa.AuxIntToInt32(v_0.AuxInt) != 1<<16 {
			break
		}
		v_0_0 := v_0.Args[0]
		if v_0_0.Op != ssaop.OpAMD64MOVWQZX {
			break
		}
		x := v_0_0.Args[0]
		v.Reset(ssaop.OpAMD64BSFQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORQconst, t)
		v0.AuxInt = ssa.Int32ToAuxInt(1 << 16)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64BSWAPL(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (BSWAPL (BSWAPL p))
	// result: p
	for {
		if v_0.Op != ssaop.OpAMD64BSWAPL {
			break
		}
		p := v_0.Args[0]
		v.CopyOf(p)
		return true
	}
	// match: (BSWAPL x:(MOVLload [i] {s} p mem))
	// cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3
	// result: @x.Block (MOVBELload [i] {s} p mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVLload {
			break
		}
		i := ssa.AuxIntToInt32(x.AuxInt)
		s := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		p := x.Args[0]
		if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBELload, typ.UInt32)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(i)
		v0.Aux = ssa.SymToAux(s)
		v0.AddArg2(p, mem)
		return true
	}
	// match: (BSWAPL x:(MOVBELload [i] {s} p mem))
	// cond: x.Uses == 1
	// result: @x.Block (MOVLload [i] {s} p mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVBELload {
			break
		}
		i := ssa.AuxIntToInt32(x.AuxInt)
		s := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		p := x.Args[0]
		if !(x.Uses == 1) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(i)
		v0.Aux = ssa.SymToAux(s)
		v0.AddArg2(p, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64BSWAPQ(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (BSWAPQ (BSWAPQ p))
	// result: p
	for {
		if v_0.Op != ssaop.OpAMD64BSWAPQ {
			break
		}
		p := v_0.Args[0]
		v.CopyOf(p)
		return true
	}
	// match: (BSWAPQ x:(MOVQload [i] {s} p mem))
	// cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3
	// result: @x.Block (MOVBEQload [i] {s} p mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVQload {
			break
		}
		i := ssa.AuxIntToInt32(x.AuxInt)
		s := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		p := x.Args[0]
		if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBEQload, typ.UInt64)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(i)
		v0.Aux = ssa.SymToAux(s)
		v0.AddArg2(p, mem)
		return true
	}
	// match: (BSWAPQ x:(MOVBEQload [i] {s} p mem))
	// cond: x.Uses == 1
	// result: @x.Block (MOVQload [i] {s} p mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVBEQload {
			break
		}
		i := ssa.AuxIntToInt32(x.AuxInt)
		s := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		p := x.Args[0]
		if !(x.Uses == 1) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(i)
		v0.Aux = ssa.SymToAux(s)
		v0.AddArg2(p, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64BTCQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (BTCQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [d^(1<<uint32(c))])
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(d ^ (1 << uint32(c)))
		return true
	}
	return false
}
func rewriteValue_OpAMD64BTLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (BTLconst [c] (SHRQconst [d] x))
	// cond: (c+d)<64
	// result: (BTQconst [c+d] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SHRQconst {
			break
		}
		d := ssa.AuxIntToInt8(v_0.AuxInt)
		x := v_0.Args[0]
		if !((c + d) < 64) {
			break
		}
		v.Reset(ssaop.OpAMD64BTQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c + d)
		v.AddArg(x)
		return true
	}
	// match: (BTLconst [c] (ADDQ x x))
	// cond: c>1
	// result: (BTLconst [c-1] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDQ {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || !(c > 1) {
			break
		}
		v.Reset(ssaop.OpAMD64BTLconst)
		v.AuxInt = ssa.Int8ToAuxInt(c - 1)
		v.AddArg(x)
		return true
	}
	// match: (BTLconst [c] (SHLQconst [d] x))
	// cond: c>d
	// result: (BTLconst [c-d] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SHLQconst {
			break
		}
		d := ssa.AuxIntToInt8(v_0.AuxInt)
		x := v_0.Args[0]
		if !(c > d) {
			break
		}
		v.Reset(ssaop.OpAMD64BTLconst)
		v.AuxInt = ssa.Int8ToAuxInt(c - d)
		v.AddArg(x)
		return true
	}
	// match: (BTLconst [0] s:(SHRQ x y))
	// result: (BTQ y x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		s := v_0
		if s.Op != ssaop.OpAMD64SHRQ {
			break
		}
		y := s.Args[1]
		x := s.Args[0]
		v.Reset(ssaop.OpAMD64BTQ)
		v.AddArg2(y, x)
		return true
	}
	// match: (BTLconst [c] (SHRLconst [d] x))
	// cond: (c+d)<32
	// result: (BTLconst [c+d] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SHRLconst {
			break
		}
		d := ssa.AuxIntToInt8(v_0.AuxInt)
		x := v_0.Args[0]
		if !((c + d) < 32) {
			break
		}
		v.Reset(ssaop.OpAMD64BTLconst)
		v.AuxInt = ssa.Int8ToAuxInt(c + d)
		v.AddArg(x)
		return true
	}
	// match: (BTLconst [c] (ADDL x x))
	// cond: c>1
	// result: (BTLconst [c-1] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDL {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || !(c > 1) {
			break
		}
		v.Reset(ssaop.OpAMD64BTLconst)
		v.AuxInt = ssa.Int8ToAuxInt(c - 1)
		v.AddArg(x)
		return true
	}
	// match: (BTLconst [c] (SHLLconst [d] x))
	// cond: c>d
	// result: (BTLconst [c-d] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SHLLconst {
			break
		}
		d := ssa.AuxIntToInt8(v_0.AuxInt)
		x := v_0.Args[0]
		if !(c > d) {
			break
		}
		v.Reset(ssaop.OpAMD64BTLconst)
		v.AuxInt = ssa.Int8ToAuxInt(c - d)
		v.AddArg(x)
		return true
	}
	// match: (BTLconst [0] s:(SHRL x y))
	// result: (BTL y x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		s := v_0
		if s.Op != ssaop.OpAMD64SHRL {
			break
		}
		y := s.Args[1]
		x := s.Args[0]
		v.Reset(ssaop.OpAMD64BTL)
		v.AddArg2(y, x)
		return true
	}
	// match: (BTLconst [0] s:(SHRXL x y))
	// result: (BTL y x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		s := v_0
		if s.Op != ssaop.OpAMD64SHRXL {
			break
		}
		y := s.Args[1]
		x := s.Args[0]
		v.Reset(ssaop.OpAMD64BTL)
		v.AddArg2(y, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64BTQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (BTQconst [c] (SHRQconst [d] x))
	// cond: (c+d)<64
	// result: (BTQconst [c+d] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SHRQconst {
			break
		}
		d := ssa.AuxIntToInt8(v_0.AuxInt)
		x := v_0.Args[0]
		if !((c + d) < 64) {
			break
		}
		v.Reset(ssaop.OpAMD64BTQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c + d)
		v.AddArg(x)
		return true
	}
	// match: (BTQconst [c] (ADDQ x x))
	// cond: c>1
	// result: (BTQconst [c-1] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDQ {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || !(c > 1) {
			break
		}
		v.Reset(ssaop.OpAMD64BTQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c - 1)
		v.AddArg(x)
		return true
	}
	// match: (BTQconst [c] (SHLQconst [d] x))
	// cond: c>d
	// result: (BTQconst [c-d] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SHLQconst {
			break
		}
		d := ssa.AuxIntToInt8(v_0.AuxInt)
		x := v_0.Args[0]
		if !(c > d) {
			break
		}
		v.Reset(ssaop.OpAMD64BTQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c - d)
		v.AddArg(x)
		return true
	}
	// match: (BTQconst [0] s:(SHRQ x y))
	// result: (BTQ y x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		s := v_0
		if s.Op != ssaop.OpAMD64SHRQ {
			break
		}
		y := s.Args[1]
		x := s.Args[0]
		v.Reset(ssaop.OpAMD64BTQ)
		v.AddArg2(y, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64BTRQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (BTRQconst [c] (BTSQconst [c] x))
	// result: (BTRQconst [c] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64BTSQconst || ssa.AuxIntToInt8(v_0.AuxInt) != c {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64BTRQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (BTRQconst [c] (BTCQconst [c] x))
	// result: (BTRQconst [c] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64BTCQconst || ssa.AuxIntToInt8(v_0.AuxInt) != c {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64BTRQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (BTRQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [d&^(1<<uint32(c))])
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(d &^ (1 << uint32(c)))
		return true
	}
	return false
}
func rewriteValue_OpAMD64BTSQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (BTSQconst [c] (BTRQconst [c] x))
	// result: (BTSQconst [c] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64BTRQconst || ssa.AuxIntToInt8(v_0.AuxInt) != c {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64BTSQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (BTSQconst [c] (BTCQconst [c] x))
	// result: (BTSQconst [c] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64BTCQconst || ssa.AuxIntToInt8(v_0.AuxInt) != c {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64BTSQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (BTSQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [d|(1<<uint32(c))])
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(d | (1 << uint32(c)))
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLCC(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVLCC x y (InvertFlags cond))
	// result: (CMOVLLS x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLLS)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLCC _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLCC _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLCC y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLCC y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLCC _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLCS(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVLCS x y (InvertFlags cond))
	// result: (CMOVLHI x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLHI)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLCS y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLCS y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLCS _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLCS _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLCS y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLEQ(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMOVLEQ x y (InvertFlags cond))
	// result: (CMOVLEQ x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLEQ)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLEQ _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLEQ y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLEQ y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLEQ y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLEQ y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLEQ x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s))
	// result: (CMOVLEQ x y (Select1 <types.TypeFlags> blsr))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_2.Args[1]
		v_2_0 := v_2.Args[0]
		v_2_1 := v_2.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 {
			s := v_2_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRQ || s != v_2_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg3(x, y, v0)
			return true
		}
		break
	}
	// match: (CMOVLEQ x y (TESTL s:(Select0 blsr:(BLSRL _)) s))
	// result: (CMOVLEQ x y (Select1 <types.TypeFlags> blsr))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_2.Args[1]
		v_2_0 := v_2.Args[0]
		v_2_1 := v_2.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 {
			s := v_2_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRL || s != v_2_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg3(x, y, v0)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETEQ flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETNE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETL flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETG flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETLE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETGE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETA flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETB flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETAE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLEQ yes no t:(TESTB s:(SETBE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64CMOVLGE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMOVLGE x y (InvertFlags cond))
	// result: (CMOVLLE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLLE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLGE _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLGE _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLGE _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLGE y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLGE y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLGE x y c:(CMPQconst [128] z))
	// cond: c.Uses == 1
	// result: (CMOVLGT x y (CMPQconst [127] z))
	for {
		x := v_0
		y := v_1
		c := v_2
		if c.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		z := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLGT)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(z)
		v.AddArg3(x, y, v0)
		return true
	}
	// match: (CMOVLGE x y c:(CMPLconst [128] z))
	// cond: c.Uses == 1
	// result: (CMOVLGT x y (CMPLconst [127] z))
	for {
		x := v_0
		y := v_1
		c := v_2
		if c.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		z := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLGT)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(z)
		v.AddArg3(x, y, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLGT(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVLGT x y (InvertFlags cond))
	// result: (CMOVLLT x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLLT)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLGT y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLGT _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLGT _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLGT y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLGT y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLHI(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVLHI x y (InvertFlags cond))
	// result: (CMOVLCS x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLCS)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLHI y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLHI _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLHI y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLHI y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLHI _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLLE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVLLE x y (InvertFlags cond))
	// result: (CMOVLGE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLGE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLLE _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLLE y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLLE y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLLE _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLLE _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLLS(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVLLS x y (InvertFlags cond))
	// result: (CMOVLCC x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLCC)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLLS _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLLS y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLLS _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLLS _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLLS y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLLT(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMOVLLT x y (InvertFlags cond))
	// result: (CMOVLGT x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLGT)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLLT y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLLT y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLLT y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLLT _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLLT _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLLT x y c:(CMPQconst [128] z))
	// cond: c.Uses == 1
	// result: (CMOVLLE x y (CMPQconst [127] z))
	for {
		x := v_0
		y := v_1
		c := v_2
		if c.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		z := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(z)
		v.AddArg3(x, y, v0)
		return true
	}
	// match: (CMOVLLT x y c:(CMPLconst [128] z))
	// cond: c.Uses == 1
	// result: (CMOVLLE x y (CMPLconst [127] z))
	for {
		x := v_0
		y := v_1
		c := v_2
		if c.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		z := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(z)
		v.AddArg3(x, y, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVLNE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMOVLNE x y (InvertFlags cond))
	// result: (CMOVLNE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVLNE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVLNE y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVLNE _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLNE _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLNE _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLNE _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVLNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s))
	// result: (CMOVLNE x y (Select1 <types.TypeFlags> blsr))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_2.Args[1]
		v_2_0 := v_2.Args[0]
		v_2_1 := v_2.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 {
			s := v_2_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRQ || s != v_2_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg3(x, y, v0)
			return true
		}
		break
	}
	// match: (CMOVLNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s))
	// result: (CMOVLNE x y (Select1 <types.TypeFlags> blsr))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_2.Args[1]
		v_2_0 := v_2.Args[0]
		v_2_1 := v_2.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 {
			s := v_2_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRL || s != v_2_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg3(x, y, v0)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVLGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETEQ flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETNE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETL flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETG flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETLE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETGE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETA flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETB flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETAE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETBE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETEQF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETNEF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETGF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVLNE yes no t:(TESTB s:(SETGEF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVLGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVLGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64CMOVQCC(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVQCC x y (InvertFlags cond))
	// result: (CMOVQLS x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQLS)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQCC _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQCC _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQCC y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQCC y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQCC _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVQCS(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVQCS x y (InvertFlags cond))
	// result: (CMOVQHI x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQHI)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQCS y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQCS y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQCS _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQCS _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQCS y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVQEQ(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMOVQEQ x y (InvertFlags cond))
	// result: (CMOVQEQ x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQEQ)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQEQ _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQEQ y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQEQ y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQEQ y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQEQ y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQEQ x _ (Select1 (BSFQ (ORQconst [c] _))))
	// cond: c != 0
	// result: x
	for {
		x := v_0
		if v_2.Op != ssaop.OpSelect1 {
			break
		}
		v_2_0 := v_2.Args[0]
		if v_2_0.Op != ssaop.OpAMD64BSFQ {
			break
		}
		v_2_0_0 := v_2_0.Args[0]
		if v_2_0_0.Op != ssaop.OpAMD64ORQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_2_0_0.AuxInt)
		if !(c != 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQEQ x _ (Select1 (BSRQ (ORQconst [c] _))))
	// cond: c != 0
	// result: x
	for {
		x := v_0
		if v_2.Op != ssaop.OpSelect1 {
			break
		}
		v_2_0 := v_2.Args[0]
		if v_2_0.Op != ssaop.OpAMD64BSRQ {
			break
		}
		v_2_0_0 := v_2_0.Args[0]
		if v_2_0_0.Op != ssaop.OpAMD64ORQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_2_0_0.AuxInt)
		if !(c != 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQEQ x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s))
	// result: (CMOVQEQ x y (Select1 <types.TypeFlags> blsr))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_2.Args[1]
		v_2_0 := v_2.Args[0]
		v_2_1 := v_2.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 {
			s := v_2_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRQ || s != v_2_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg3(x, y, v0)
			return true
		}
		break
	}
	// match: (CMOVQEQ x y (TESTL s:(Select0 blsr:(BLSRL _)) s))
	// result: (CMOVQEQ x y (Select1 <types.TypeFlags> blsr))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_2.Args[1]
		v_2_0 := v_2.Args[0]
		v_2_1 := v_2.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 {
			s := v_2_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRL || s != v_2_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg3(x, y, v0)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETEQ flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETNE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETL flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETG flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETLE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETGE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETA flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETB flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETAE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQEQ yes no t:(TESTB s:(SETBE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64CMOVQGE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMOVQGE x y (InvertFlags cond))
	// result: (CMOVQLE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQLE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQGE _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQGE _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQGE _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQGE y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQGE y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQGE x y c:(CMPQconst [128] z))
	// cond: c.Uses == 1
	// result: (CMOVQGT x y (CMPQconst [127] z))
	for {
		x := v_0
		y := v_1
		c := v_2
		if c.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		z := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQGT)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(z)
		v.AddArg3(x, y, v0)
		return true
	}
	// match: (CMOVQGE x y c:(CMPLconst [128] z))
	// cond: c.Uses == 1
	// result: (CMOVQGT x y (CMPLconst [127] z))
	for {
		x := v_0
		y := v_1
		c := v_2
		if c.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		z := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQGT)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(z)
		v.AddArg3(x, y, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVQGT(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVQGT x y (InvertFlags cond))
	// result: (CMOVQLT x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQLT)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQGT y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQGT _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQGT _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQGT y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQGT y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVQHI(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVQHI x y (InvertFlags cond))
	// result: (CMOVQCS x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQCS)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQHI y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQHI _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQHI y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQHI y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQHI _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVQLE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVQLE x y (InvertFlags cond))
	// result: (CMOVQGE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQGE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQLE _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQLE y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQLE y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQLE _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQLE _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVQLS(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVQLS x y (InvertFlags cond))
	// result: (CMOVQCC x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQCC)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQLS _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQLS y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQLS _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQLS _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQLS y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVQLT(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMOVQLT x y (InvertFlags cond))
	// result: (CMOVQGT x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQGT)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQLT y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQLT y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQLT y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQLT _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQLT _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQLT x y c:(CMPQconst [128] z))
	// cond: c.Uses == 1
	// result: (CMOVQLE x y (CMPQconst [127] z))
	for {
		x := v_0
		y := v_1
		c := v_2
		if c.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		z := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(z)
		v.AddArg3(x, y, v0)
		return true
	}
	// match: (CMOVQLT x y c:(CMPLconst [128] z))
	// cond: c.Uses == 1
	// result: (CMOVQLE x y (CMPLconst [127] z))
	for {
		x := v_0
		y := v_1
		c := v_2
		if c.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		z := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(z)
		v.AddArg3(x, y, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVQNE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMOVQNE x y (InvertFlags cond))
	// result: (CMOVQNE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVQNE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVQNE y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVQNE _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQNE _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQNE _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQNE _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVQNE x y (TESTQ s:(Select0 blsr:(BLSRQ _)) s))
	// result: (CMOVQNE x y (Select1 <types.TypeFlags> blsr))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_2.Args[1]
		v_2_0 := v_2.Args[0]
		v_2_1 := v_2.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 {
			s := v_2_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRQ || s != v_2_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg3(x, y, v0)
			return true
		}
		break
	}
	// match: (CMOVQNE x y (TESTL s:(Select0 blsr:(BLSRL _)) s))
	// result: (CMOVQNE x y (Select1 <types.TypeFlags> blsr))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_2.Args[1]
		v_2_0 := v_2.Args[0]
		v_2_1 := v_2.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_2_0, v_2_1 = _i0+1, v_2_1, v_2_0 {
			s := v_2_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRL || s != v_2_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg3(x, y, v0)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVQGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETEQ flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETNE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETL flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETG flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETLE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETGE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETA flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETB flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETAE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETBE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETEQF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETNEF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETGF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVQNE yes no t:(TESTB s:(SETGEF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVQGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVQGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64CMOVWCC(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWCC x y (InvertFlags cond))
	// result: (CMOVWLS x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWLS)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWCC _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWCC _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWCC y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWCC y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWCC _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVWCS(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWCS x y (InvertFlags cond))
	// result: (CMOVWHI x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWHI)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWCS y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWCS y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWCS _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWCS _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWCS y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVWEQ(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWEQ x y (InvertFlags cond))
	// result: (CMOVWEQ x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWEQ)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWEQ _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWEQ y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWEQ y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWEQ y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWEQ y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETEQ flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETNE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETL flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETG flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETLE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETGE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETA flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETB flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETAE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWEQ yes no t:(TESTB s:(SETBE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64CMOVWGE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWGE x y (InvertFlags cond))
	// result: (CMOVWLE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWLE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWGE _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWGE _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWGE _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWGE y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWGE y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVWGT(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWGT x y (InvertFlags cond))
	// result: (CMOVWLT x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWLT)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWGT y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWGT _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWGT _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWGT y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWGT y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVWHI(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWHI x y (InvertFlags cond))
	// result: (CMOVWCS x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWCS)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWHI y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWHI _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWHI y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWHI y _ (FlagLT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWHI _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVWLE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWLE x y (InvertFlags cond))
	// result: (CMOVWGE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWGE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWLE _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWLE y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWLE y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWLE _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWLE _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVWLS(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWLS x y (InvertFlags cond))
	// result: (CMOVWCC x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWCC)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWLS _ x (FlagEQ))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWLS y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWLS _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWLS _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWLS y _ (FlagLT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVWLT(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWLT x y (InvertFlags cond))
	// result: (CMOVWGT x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWGT)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWLT y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWLT y _ (FlagGT_UGT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWLT y _ (FlagGT_ULT))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWLT _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWLT _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMOVWNE(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMOVWNE x y (InvertFlags cond))
	// result: (CMOVWNE x y cond)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		cond := v_2.Args[0]
		v.Reset(ssaop.OpAMD64CMOVWNE)
		v.AddArg3(x, y, cond)
		return true
	}
	// match: (CMOVWNE y _ (FlagEQ))
	// result: y
	for {
		y := v_0
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.CopyOf(y)
		return true
	}
	// match: (CMOVWNE _ x (FlagGT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWNE _ x (FlagGT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWNE _ x (FlagLT_ULT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWNE _ x (FlagLT_UGT))
	// result: x
	for {
		x := v_1
		if v_2.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: (CMOVWGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETEQ flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWEQ yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQ)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETNE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWNE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETL flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWLT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETG flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWGT yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGT)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETLE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWLE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETGE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWGE yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGE)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETA flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWHI yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWHI)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETB flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWCS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETAE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWCC yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWCC)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETBE flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWLS yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWLS)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETEQF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWEQF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWEQF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETNEF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWNEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWNEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETGF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWGTF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGTF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	// match: (CMOVWNE yes no t:(TESTB s:(SETGEF flags) s))
	// cond: t.Block == s.Block
	// result: (CMOVWGEF yes no flags)
	for {
		yes := v_0
		no := v_1
		t := v_2
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64CMOVWGEF)
			v.AddArg3(yes, no, flags)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64CMPB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMPB x (MOVLconst [c]))
	// result: (CMPBconst x [int8(c)])
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64CMPBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c))
		v.AddArg(x)
		return true
	}
	// match: (CMPB (MOVLconst [c]) x)
	// result: (InvertFlags (CMPBconst x [int8(c)]))
	for {
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_1
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(c))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (CMPB x y)
	// cond: ssa.CanonLessThan(x,y)
	// result: (InvertFlags (CMPB y x))
	for {
		x := v_0
		y := v_1
		if !(ssa.CanonLessThan(x, y)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(y, x)
		v.AddArg(v0)
		return true
	}
	// match: (CMPB l:(MOVBload {sym} [off] ptr mem) x)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (CMPBload {sym} [off] ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVBload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPBload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (CMPB x l:(MOVBload {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (InvertFlags (CMPBload {sym} [off] ptr x mem))
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVBload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPBload, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg3(ptr, x, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPBconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMPBconst (MOVLconst [x]) [y])
	// cond: int8(x)==y
	// result: (FlagEQ)
	for {
		y := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int8(x) == y) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagEQ)
		return true
	}
	// match: (CMPBconst (MOVLconst [x]) [y])
	// cond: int8(x)<y && uint8(x)<uint8(y)
	// result: (FlagLT_ULT)
	for {
		y := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int8(x) < y && uint8(x) < uint8(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPBconst (MOVLconst [x]) [y])
	// cond: int8(x)<y && uint8(x)>uint8(y)
	// result: (FlagLT_UGT)
	for {
		y := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int8(x) < y && uint8(x) > uint8(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_UGT)
		return true
	}
	// match: (CMPBconst (MOVLconst [x]) [y])
	// cond: int8(x)>y && uint8(x)<uint8(y)
	// result: (FlagGT_ULT)
	for {
		y := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int8(x) > y && uint8(x) < uint8(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_ULT)
		return true
	}
	// match: (CMPBconst (MOVLconst [x]) [y])
	// cond: int8(x)>y && uint8(x)>uint8(y)
	// result: (FlagGT_UGT)
	for {
		y := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int8(x) > y && uint8(x) > uint8(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_UGT)
		return true
	}
	// match: (CMPBconst (ANDLconst _ [m]) [n])
	// cond: 0 <= int8(m) && int8(m) < n
	// result: (FlagLT_ULT)
	for {
		n := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		m := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(0 <= int8(m) && int8(m) < n) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPBconst a:(ANDL x y) [0])
	// cond: a.Uses == 1
	// result: (TESTB x y)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		a := v_0
		if a.Op != ssaop.OpAMD64ANDL {
			break
		}
		y := a.Args[1]
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTB)
		v.AddArg2(x, y)
		return true
	}
	// match: (CMPBconst a:(ANDLconst [c] x) [0])
	// cond: a.Uses == 1
	// result: (TESTBconst [int8(c)] x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		a := v_0
		if a.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c))
		v.AddArg(x)
		return true
	}
	// match: (CMPBconst x [0])
	// result: (TESTB x x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64TESTB)
		v.AddArg2(x, x)
		return true
	}
	// match: (CMPBconst l:(MOVBload {sym} [off] ptr mem) [c])
	// cond: l.Uses == 1 && ssa.Clobber(l)
	// result: @l.Block (CMPBconstload {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64MOVBload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(l.Uses == 1 && ssa.Clobber(l)) {
			break
		}
		b = l.Block
		v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPBconstload, types.TypeFlags)
		v.CopyOf(v0)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPBconstload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPBconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (CMPBconstload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPBconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (CMPBconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (CMPBconstload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPBconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPBload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPBload [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (CMPBload [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPBload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (CMPBload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (CMPBload [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPBload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (CMPBload {sym} [off] ptr (MOVLconst [c]) mem)
	// result: (CMPBconstload {sym} [ssa.MakeValAndOff(int32(int8(c)),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64CMPBconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(int8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMPL x (MOVLconst [c]))
	// result: (CMPLconst x [c])
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64CMPLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (CMPL (MOVLconst [c]) x)
	// result: (InvertFlags (CMPLconst x [c]))
	for {
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_1
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(c)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (CMPL x y)
	// cond: ssa.CanonLessThan(x,y)
	// result: (InvertFlags (CMPL y x))
	for {
		x := v_0
		y := v_1
		if !(ssa.CanonLessThan(x, y)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPL, types.TypeFlags)
		v0.AddArg2(y, x)
		v.AddArg(v0)
		return true
	}
	// match: (CMPL l:(MOVLload {sym} [off] ptr mem) x)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (CMPLload {sym} [off] ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPLload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (CMPL x l:(MOVLload {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (InvertFlags (CMPLload {sym} [off] ptr x mem))
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPLload, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg3(ptr, x, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMPLconst (MOVLconst [x]) [y])
	// cond: x==y
	// result: (FlagEQ)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(x == y) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagEQ)
		return true
	}
	// match: (CMPLconst (MOVLconst [x]) [y])
	// cond: x<y && uint32(x)<uint32(y)
	// result: (FlagLT_ULT)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(x < y && uint32(x) < uint32(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPLconst (MOVLconst [x]) [y])
	// cond: x<y && uint32(x)>uint32(y)
	// result: (FlagLT_UGT)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(x < y && uint32(x) > uint32(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_UGT)
		return true
	}
	// match: (CMPLconst (MOVLconst [x]) [y])
	// cond: x>y && uint32(x)<uint32(y)
	// result: (FlagGT_ULT)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(x > y && uint32(x) < uint32(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_ULT)
		return true
	}
	// match: (CMPLconst (MOVLconst [x]) [y])
	// cond: x>y && uint32(x)>uint32(y)
	// result: (FlagGT_UGT)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(x > y && uint32(x) > uint32(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_UGT)
		return true
	}
	// match: (CMPLconst (SHRLconst _ [c]) [n])
	// cond: 0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)
	// result: (FlagLT_ULT)
	for {
		n := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SHRLconst {
			break
		}
		c := ssa.AuxIntToInt8(v_0.AuxInt)
		if !(0 <= n && 0 < c && c <= 32 && (1<<uint64(32-c)) <= uint64(n)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPLconst (ANDLconst _ [m]) [n])
	// cond: 0 <= m && m < n
	// result: (FlagLT_ULT)
	for {
		n := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		m := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(0 <= m && m < n) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPLconst a:(ANDL x y) [0])
	// cond: a.Uses == 1
	// result: (TESTL x y)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		a := v_0
		if a.Op != ssaop.OpAMD64ANDL {
			break
		}
		y := a.Args[1]
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTL)
		v.AddArg2(x, y)
		return true
	}
	// match: (CMPLconst a:(ANDLconst [c] x) [0])
	// cond: a.Uses == 1
	// result: (TESTLconst [c] x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		a := v_0
		if a.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (CMPLconst x [0])
	// result: (TESTL x x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64TESTL)
		v.AddArg2(x, x)
		return true
	}
	// match: (CMPLconst l:(MOVLload {sym} [off] ptr mem) [c])
	// cond: l.Uses == 1 && ssa.Clobber(l)
	// result: @l.Block (CMPLconstload {sym} [ssa.MakeValAndOff(c,off)] ptr mem)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(l.Uses == 1 && ssa.Clobber(l)) {
			break
		}
		b = l.Block
		v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPLconstload, types.TypeFlags)
		v.CopyOf(v0)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(c, off))
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPLconstload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPLconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (CMPLconstload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPLconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (CMPLconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (CMPLconstload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPLconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPLload [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (CMPLload [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (CMPLload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (CMPLload [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (CMPLload {sym} [off] ptr (MOVLconst [c]) mem)
	// result: (CMPLconstload {sym} [ssa.MakeValAndOff(c,off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64CMPLconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(c, off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMPQ x (MOVQconst [c]))
	// cond: ssa.Is32Bit(c)
	// result: (CMPQconst x [int32(c)])
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(ssa.Is32Bit(c)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPQconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(c))
		v.AddArg(x)
		return true
	}
	// match: (CMPQ (MOVQconst [c]) x)
	// cond: ssa.Is32Bit(c)
	// result: (InvertFlags (CMPQconst x [int32(c)]))
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_0.AuxInt)
		x := v_1
		if !(ssa.Is32Bit(c)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(int32(c))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (CMPQ x y)
	// cond: ssa.CanonLessThan(x,y)
	// result: (InvertFlags (CMPQ y x))
	for {
		x := v_0
		y := v_1
		if !(ssa.CanonLessThan(x, y)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(y, x)
		v.AddArg(v0)
		return true
	}
	// match: (CMPQ (MOVQconst [x]) (MOVQconst [y]))
	// cond: x==y
	// result: (FlagEQ)
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		y := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(x == y) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagEQ)
		return true
	}
	// match: (CMPQ (MOVQconst [x]) (MOVQconst [y]))
	// cond: x<y && uint64(x)<uint64(y)
	// result: (FlagLT_ULT)
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		y := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(x < y && uint64(x) < uint64(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPQ (MOVQconst [x]) (MOVQconst [y]))
	// cond: x<y && uint64(x)>uint64(y)
	// result: (FlagLT_UGT)
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		y := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(x < y && uint64(x) > uint64(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_UGT)
		return true
	}
	// match: (CMPQ (MOVQconst [x]) (MOVQconst [y]))
	// cond: x>y && uint64(x)<uint64(y)
	// result: (FlagGT_ULT)
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		y := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(x > y && uint64(x) < uint64(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_ULT)
		return true
	}
	// match: (CMPQ (MOVQconst [x]) (MOVQconst [y]))
	// cond: x>y && uint64(x)>uint64(y)
	// result: (FlagGT_UGT)
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		y := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(x > y && uint64(x) > uint64(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_UGT)
		return true
	}
	// match: (CMPQ l:(MOVQload {sym} [off] ptr mem) x)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (CMPQload {sym} [off] ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPQload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (CMPQ x l:(MOVQload {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (InvertFlags (CMPQload {sym} [off] ptr x mem))
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPQload, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg3(ptr, x, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMPQconst (MOVQconst [x]) [y])
	// cond: x==int64(y)
	// result: (FlagEQ)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if !(x == int64(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagEQ)
		return true
	}
	// match: (CMPQconst (MOVQconst [x]) [y])
	// cond: x<int64(y) && uint64(x)<uint64(int64(y))
	// result: (FlagLT_ULT)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if !(x < int64(y) && uint64(x) < uint64(int64(y))) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPQconst (MOVQconst [x]) [y])
	// cond: x<int64(y) && uint64(x)>uint64(int64(y))
	// result: (FlagLT_UGT)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if !(x < int64(y) && uint64(x) > uint64(int64(y))) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_UGT)
		return true
	}
	// match: (CMPQconst (MOVQconst [x]) [y])
	// cond: x>int64(y) && uint64(x)<uint64(int64(y))
	// result: (FlagGT_ULT)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if !(x > int64(y) && uint64(x) < uint64(int64(y))) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_ULT)
		return true
	}
	// match: (CMPQconst (MOVQconst [x]) [y])
	// cond: x>int64(y) && uint64(x)>uint64(int64(y))
	// result: (FlagGT_UGT)
	for {
		y := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		x := ssa.AuxIntToInt64(v_0.AuxInt)
		if !(x > int64(y) && uint64(x) > uint64(int64(y))) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_UGT)
		return true
	}
	// match: (CMPQconst (MOVBQZX _) [c])
	// cond: 0xFF < c
	// result: (FlagLT_ULT)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVBQZX || !(0xFF < c) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPQconst (MOVWQZX _) [c])
	// cond: 0xFFFF < c
	// result: (FlagLT_ULT)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVWQZX || !(0xFFFF < c) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPQconst (SHRQconst _ [c]) [n])
	// cond: 0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n)
	// result: (FlagLT_ULT)
	for {
		n := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SHRQconst {
			break
		}
		c := ssa.AuxIntToInt8(v_0.AuxInt)
		if !(0 <= n && 0 < c && c <= 64 && (1<<uint64(64-c)) <= uint64(n)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPQconst (ANDQconst _ [m]) [n])
	// cond: 0 <= m && m < n
	// result: (FlagLT_ULT)
	for {
		n := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		m := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(0 <= m && m < n) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPQconst (ANDLconst _ [m]) [n])
	// cond: 0 <= m && m < n
	// result: (FlagLT_ULT)
	for {
		n := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		m := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(0 <= m && m < n) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPQconst a:(ANDQ x y) [0])
	// cond: a.Uses == 1
	// result: (TESTQ x y)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		a := v_0
		if a.Op != ssaop.OpAMD64ANDQ {
			break
		}
		y := a.Args[1]
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (CMPQconst a:(ANDQconst [c] x) [0])
	// cond: a.Uses == 1
	// result: (TESTQconst [c] x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		a := v_0
		if a.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (CMPQconst x [0])
	// result: (TESTQ x x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64TESTQ)
		v.AddArg2(x, x)
		return true
	}
	// match: (CMPQconst l:(MOVQload {sym} [off] ptr mem) [c])
	// cond: l.Uses == 1 && ssa.Clobber(l)
	// result: @l.Block (CMPQconstload {sym} [ssa.MakeValAndOff(c,off)] ptr mem)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(l.Uses == 1 && ssa.Clobber(l)) {
			break
		}
		b = l.Block
		v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPQconstload, types.TypeFlags)
		v.CopyOf(v0)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(c, off))
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPQconstload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPQconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (CMPQconstload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPQconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (CMPQconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (CMPQconstload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPQconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPQload [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (CMPQload [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (CMPQload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (CMPQload [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (CMPQload {sym} [off] ptr (MOVQconst [c]) mem)
	// cond: validVal(c)
	// result: (CMPQconstload {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		if !(validVal(c)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPQconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPW(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMPW x (MOVLconst [c]))
	// result: (CMPWconst x [int16(c)])
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64CMPWconst)
		v.AuxInt = ssa.Int16ToAuxInt(int16(c))
		v.AddArg(x)
		return true
	}
	// match: (CMPW (MOVLconst [c]) x)
	// result: (InvertFlags (CMPWconst x [int16(c)]))
	for {
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_1
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v0.AuxInt = ssa.Int16ToAuxInt(int16(c))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (CMPW x y)
	// cond: ssa.CanonLessThan(x,y)
	// result: (InvertFlags (CMPW y x))
	for {
		x := v_0
		y := v_1
		if !(ssa.CanonLessThan(x, y)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPW, types.TypeFlags)
		v0.AddArg2(y, x)
		v.AddArg(v0)
		return true
	}
	// match: (CMPW l:(MOVWload {sym} [off] ptr mem) x)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (CMPWload {sym} [off] ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVWload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPWload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (CMPW x l:(MOVWload {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (InvertFlags (CMPWload {sym} [off] ptr x mem))
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVWload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64InvertFlags)
		v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPWload, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg3(ptr, x, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPWconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CMPWconst (MOVLconst [x]) [y])
	// cond: int16(x)==y
	// result: (FlagEQ)
	for {
		y := ssa.AuxIntToInt16(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int16(x) == y) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagEQ)
		return true
	}
	// match: (CMPWconst (MOVLconst [x]) [y])
	// cond: int16(x)<y && uint16(x)<uint16(y)
	// result: (FlagLT_ULT)
	for {
		y := ssa.AuxIntToInt16(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int16(x) < y && uint16(x) < uint16(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPWconst (MOVLconst [x]) [y])
	// cond: int16(x)<y && uint16(x)>uint16(y)
	// result: (FlagLT_UGT)
	for {
		y := ssa.AuxIntToInt16(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int16(x) < y && uint16(x) > uint16(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_UGT)
		return true
	}
	// match: (CMPWconst (MOVLconst [x]) [y])
	// cond: int16(x)>y && uint16(x)<uint16(y)
	// result: (FlagGT_ULT)
	for {
		y := ssa.AuxIntToInt16(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int16(x) > y && uint16(x) < uint16(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_ULT)
		return true
	}
	// match: (CMPWconst (MOVLconst [x]) [y])
	// cond: int16(x)>y && uint16(x)>uint16(y)
	// result: (FlagGT_UGT)
	for {
		y := ssa.AuxIntToInt16(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		x := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(int16(x) > y && uint16(x) > uint16(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_UGT)
		return true
	}
	// match: (CMPWconst (ANDLconst _ [m]) [n])
	// cond: 0 <= int16(m) && int16(m) < n
	// result: (FlagLT_ULT)
	for {
		n := ssa.AuxIntToInt16(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		m := ssa.AuxIntToInt32(v_0.AuxInt)
		if !(0 <= int16(m) && int16(m) < n) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_ULT)
		return true
	}
	// match: (CMPWconst a:(ANDL x y) [0])
	// cond: a.Uses == 1
	// result: (TESTW x y)
	for {
		if ssa.AuxIntToInt16(v.AuxInt) != 0 {
			break
		}
		a := v_0
		if a.Op != ssaop.OpAMD64ANDL {
			break
		}
		y := a.Args[1]
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTW)
		v.AddArg2(x, y)
		return true
	}
	// match: (CMPWconst a:(ANDLconst [c] x) [0])
	// cond: a.Uses == 1
	// result: (TESTWconst [int16(c)] x)
	for {
		if ssa.AuxIntToInt16(v.AuxInt) != 0 {
			break
		}
		a := v_0
		if a.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTWconst)
		v.AuxInt = ssa.Int16ToAuxInt(int16(c))
		v.AddArg(x)
		return true
	}
	// match: (CMPWconst x [0])
	// result: (TESTW x x)
	for {
		if ssa.AuxIntToInt16(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64TESTW)
		v.AddArg2(x, x)
		return true
	}
	// match: (CMPWconst l:(MOVWload {sym} [off] ptr mem) [c])
	// cond: l.Uses == 1 && ssa.Clobber(l)
	// result: @l.Block (CMPWconstload {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		c := ssa.AuxIntToInt16(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64MOVWload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(l.Uses == 1 && ssa.Clobber(l)) {
			break
		}
		b = l.Block
		v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPWconstload, types.TypeFlags)
		v.CopyOf(v0)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPWconstload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPWconstload [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (CMPWconstload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPWconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (CMPWconstload [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (CMPWconstload [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPWconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPWload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPWload [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (CMPWload [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPWload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (CMPWload [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (CMPWload [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPWload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (CMPWload {sym} [off] ptr (MOVLconst [c]) mem)
	// result: (CMPWconstload {sym} [ssa.MakeValAndOff(int32(int16(c)),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64CMPWconstload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(int16(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPXCHGLlock(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPXCHGLlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (CMPXCHGLlock [off1+off2] {sym} ptr old new_ mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		old := v_1
		new_ := v_2
		mem := v_3
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPXCHGLlock)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(ptr, old, new_, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CMPXCHGQlock(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (CMPXCHGQlock [off1] {sym} (ADDQconst [off2] ptr) old new_ mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (CMPXCHGQlock [off1+off2] {sym} ptr old new_ mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		old := v_1
		new_ := v_2
		mem := v_3
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMPXCHGQlock)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(ptr, old, new_, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64CVTSD2SS(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CVTSD2SS (ROUNDSD [c] (CVTSS2SD x)))
	// result: (ROUNDSS [c] x)
	for {
		if v_0.Op != ssaop.OpAMD64ROUNDSD {
			break
		}
		c := ssa.AuxIntToInt8(v_0.AuxInt)
		v_0_0 := v_0.Args[0]
		if v_0_0.Op != ssaop.OpAMD64CVTSS2SD {
			break
		}
		x := v_0_0.Args[0]
		v.Reset(ssaop.OpAMD64ROUNDSS)
		v.AuxInt = ssa.Int8ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64DIVSD(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (DIVSD x l:(MOVSDload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (DIVSDload x [off] {sym} ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVSDload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64DIVSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64DIVSDload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (DIVSDload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (DIVSDload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64DIVSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (DIVSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (DIVSDload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64DIVSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64DIVSS(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (DIVSS x l:(MOVSSload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (DIVSSload x [off] {sym} ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVSSload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64DIVSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64DIVSSload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (DIVSSload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (DIVSSload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64DIVSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (DIVSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (DIVSSload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64DIVSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64HMULL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (HMULL x y)
	// cond: !x.Rematerializeable() && y.Rematerializeable()
	// result: (HMULL y x)
	for {
		x := v_0
		y := v_1
		if !(!x.Rematerializeable() && y.Rematerializeable()) {
			break
		}
		v.Reset(ssaop.OpAMD64HMULL)
		v.AddArg2(y, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64HMULLU(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (HMULLU x y)
	// cond: !x.Rematerializeable() && y.Rematerializeable()
	// result: (HMULLU y x)
	for {
		x := v_0
		y := v_1
		if !(!x.Rematerializeable() && y.Rematerializeable()) {
			break
		}
		v.Reset(ssaop.OpAMD64HMULLU)
		v.AddArg2(y, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64HMULQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (HMULQ x y)
	// cond: !x.Rematerializeable() && y.Rematerializeable()
	// result: (HMULQ y x)
	for {
		x := v_0
		y := v_1
		if !(!x.Rematerializeable() && y.Rematerializeable()) {
			break
		}
		v.Reset(ssaop.OpAMD64HMULQ)
		v.AddArg2(y, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64HMULQU(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (HMULQU x y)
	// cond: !x.Rematerializeable() && y.Rematerializeable()
	// result: (HMULQU y x)
	for {
		x := v_0
		y := v_1
		if !(!x.Rematerializeable() && y.Rematerializeable()) {
			break
		}
		v.Reset(ssaop.OpAMD64HMULQU)
		v.AddArg2(y, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64KANDB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (KANDB (VCMPPD512 [3] x x) (VCMPPD512 [3] y y))
	// result: (VCMPPD512 [3] x x)
	for {
		if v_0.Op != ssaop.OpAMD64VCMPPD512 || ssa.AuxIntToUint8(v_0.AuxInt) != 3 {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || v_1.Op != ssaop.OpAMD64VCMPPD512 || ssa.AuxIntToUint8(v_1.AuxInt) != 3 {
			break
		}
		y := v_1.Args[1]
		if y != v_1.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg2(x, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64KANDW(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (KANDW (VCMPPS512 [3] x x) (VCMPPS512 [3] y y))
	// result: (VCMPPS512 [3] x y)
	for {
		if v_0.Op != ssaop.OpAMD64VCMPPS512 || ssa.AuxIntToUint8(v_0.AuxInt) != 3 {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || v_1.Op != ssaop.OpAMD64VCMPPS512 || ssa.AuxIntToUint8(v_1.AuxInt) != 3 {
			break
		}
		y := v_1.Args[1]
		if y != v_1.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64KMOVBk(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (KMOVBk l:(MOVBload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (KMOVBload [off] {sym} ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVBload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64KMOVBload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64KMOVDk(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (KMOVDk l:(MOVLload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (KMOVDload [off] {sym} ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64KMOVDload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64KMOVQk(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (KMOVQk l:(MOVQload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (KMOVQload [off] {sym} ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64KMOVQload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64KMOVWk(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (KMOVWk l:(MOVWload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (KMOVWload [off] {sym} ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVWload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64KMOVWload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LEAL(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (LEAL [c] {s} (ADDLconst [d] x))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAL [c+d] {s} x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg(x)
		return true
	}
	// match: (LEAL [c] {s} (ADDL x y))
	// cond: x.Op != ssaop.OpSB && y.Op != ssaop.OpSB
	// result: (LEAL1 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			x := v_0_0
			y := v_0_1
			if !(x.Op != ssaop.OpSB && y.Op != ssaop.OpSB) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAL1)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64LEAL1(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LEAL1 [c] {s} (ADDLconst [d] x) y)
	// cond: ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB
	// result: (LEAL1 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64ADDLconst {
				continue
			}
			d := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_0.Args[0]
			y := v_1
			if !(ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAL1)
			v.AuxInt = ssa.Int32ToAuxInt(c + d)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAL1 [c] {s} x z:(ADDL y y))
	// cond: x != z
	// result: (LEAL2 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			z := v_1
			if z.Op != ssaop.OpAMD64ADDL {
				continue
			}
			y := z.Args[1]
			if y != z.Args[0] || !(x != z) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAL2)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAL1 [c] {s} x (SHLLconst [2] y))
	// result: (LEAL4 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(v_1.AuxInt) != 2 {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64LEAL4)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAL1 [c] {s} x (SHLLconst [3] y))
	// result: (LEAL8 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(v_1.AuxInt) != 3 {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64LEAL8)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64LEAL2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LEAL2 [c] {s} (ADDLconst [d] x) y)
	// cond: ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB
	// result: (LEAL2 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL2)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAL2 [c] {s} x (ADDLconst [d] y))
	// cond: ssa.Is32Bit(int64(c)+2*int64(d)) && y.Op != ssaop.OpSB
	// result: (LEAL2 [c+2*d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(ssa.Is32Bit(int64(c)+2*int64(d)) && y.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL2)
		v.AuxInt = ssa.Int32ToAuxInt(c + 2*d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAL2 [c] {s} x z:(ADDL y y))
	// cond: x != z
	// result: (LEAL4 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		z := v_1
		if z.Op != ssaop.OpAMD64ADDL {
			break
		}
		y := z.Args[1]
		if y != z.Args[0] || !(x != z) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL4)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAL2 [c] {s} x (SHLLconst [2] y))
	// result: (LEAL8 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(v_1.AuxInt) != 2 {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64LEAL8)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAL2 [0] {s} (ADDL x x) x)
	// cond: s == nil
	// result: (SHLLconst [2] x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDL {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || x != v_1 || !(s == nil) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(2)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LEAL4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LEAL4 [c] {s} (ADDLconst [d] x) y)
	// cond: ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB
	// result: (LEAL4 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL4)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAL4 [c] {s} x (ADDLconst [d] y))
	// cond: ssa.Is32Bit(int64(c)+4*int64(d)) && y.Op != ssaop.OpSB
	// result: (LEAL4 [c+4*d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(ssa.Is32Bit(int64(c)+4*int64(d)) && y.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL4)
		v.AuxInt = ssa.Int32ToAuxInt(c + 4*d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAL4 [c] {s} x z:(ADDL y y))
	// cond: x != z
	// result: (LEAL8 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		z := v_1
		if z.Op != ssaop.OpAMD64ADDL {
			break
		}
		y := z.Args[1]
		if y != z.Args[0] || !(x != z) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL8)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LEAL8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LEAL8 [c] {s} (ADDLconst [d] x) y)
	// cond: ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB
	// result: (LEAL8 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL8)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAL8 [c] {s} x (ADDLconst [d] y))
	// cond: ssa.Is32Bit(int64(c)+8*int64(d)) && y.Op != ssaop.OpSB
	// result: (LEAL8 [c+8*d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(ssa.Is32Bit(int64(c)+8*int64(d)) && y.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAL8)
		v.AuxInt = ssa.Int32ToAuxInt(c + 8*d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LEAQ(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (LEAQ [c] {s} (ADDQconst [d] x))
	// cond: ssa.Is32Bit(int64(c)+int64(d))
	// result: (LEAQ [c+d] {s} x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) + int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg(x)
		return true
	}
	// match: (LEAQ [c] {s} (ADDQ x y))
	// cond: x.Op != ssaop.OpSB && y.Op != ssaop.OpSB
	// result: (LEAQ1 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			x := v_0_0
			y := v_0_1
			if !(x.Op != ssaop.OpSB && y.Op != ssaop.OpSB) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAQ1)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAQ [off1] {sym1} (LEAQ [off2] {sym2} x))
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (LEAQ [off1+off2] {ssa.MergeSym(sym1,sym2)} x)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg(x)
		return true
	}
	// match: (LEAQ [off1] {sym1} (LEAQ1 [off2] {sym2} x y))
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (LEAQ1 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ1 {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ1)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ [off1] {sym1} (LEAQ2 [off2] {sym2} x y))
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (LEAQ2 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ2 {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ2)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ [off1] {sym1} (LEAQ4 [off2] {sym2} x y))
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (LEAQ4 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ4 {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ4)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ [off1] {sym1} (LEAQ8 [off2] {sym2} x y))
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (LEAQ8 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ8 {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		y := v_0.Args[1]
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ8)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LEAQ1(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LEAQ1 [c] {s} (ADDQconst [d] x) y)
	// cond: ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB
	// result: (LEAQ1 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64ADDQconst {
				continue
			}
			d := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_0.Args[0]
			y := v_1
			if !(ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAQ1)
			v.AuxInt = ssa.Int32ToAuxInt(c + d)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAQ1 [c] {s} x z:(ADDQ y y))
	// cond: x != z
	// result: (LEAQ2 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			z := v_1
			if z.Op != ssaop.OpAMD64ADDQ {
				continue
			}
			y := z.Args[1]
			if y != z.Args[0] || !(x != z) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAQ2)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAQ1 [c] {s} x (SHLQconst [2] y))
	// result: (LEAQ4 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(v_1.AuxInt) != 2 {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64LEAQ4)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAQ1 [c] {s} x (SHLQconst [3] y))
	// result: (LEAQ8 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(v_1.AuxInt) != 3 {
				continue
			}
			y := v_1.Args[0]
			v.Reset(ssaop.OpAMD64LEAQ8)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.Aux = ssa.SymToAux(s)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAQ1 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB
	// result: (LEAQ1 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64LEAQ {
				continue
			}
			off2 := ssa.AuxIntToInt32(v_0.AuxInt)
			sym2 := ssa.AuxToSym(v_0.Aux)
			x := v_0.Args[0]
			y := v_1
			if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAQ1)
			v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
			v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y))
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (LEAQ2 [off1+off2] {ssa.MergeSym(sym1, sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64LEAQ1 {
				continue
			}
			off2 := ssa.AuxIntToInt32(v_1.AuxInt)
			sym2 := ssa.AuxToSym(v_1.Aux)
			y := v_1.Args[1]
			if y != v_1.Args[0] || !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
				continue
			}
			v.Reset(ssaop.OpAMD64LEAQ2)
			v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
			v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (LEAQ1 [off1] {sym1} x (LEAQ1 [off2] {sym2} x y))
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (LEAQ2 [off1+off2] {ssa.MergeSym(sym1, sym2)} y x)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64LEAQ1 {
				continue
			}
			off2 := ssa.AuxIntToInt32(v_1.AuxInt)
			sym2 := ssa.AuxToSym(v_1.Aux)
			_ = v_1.Args[1]
			v_1_0 := v_1.Args[0]
			v_1_1 := v_1.Args[1]
			for _i1 := 0; _i1 <= 1; _i1, v_1_0, v_1_1 = _i1+1, v_1_1, v_1_0 {
				if x != v_1_0 {
					continue
				}
				y := v_1_1
				if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
					continue
				}
				v.Reset(ssaop.OpAMD64LEAQ2)
				v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
				v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
				v.AddArg2(y, x)
				return true
			}
		}
		break
	}
	// match: (LEAQ1 [0] x y)
	// cond: v.Aux == nil
	// result: (ADDQ x y)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		y := v_1
		if !(v.Aux == nil) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LEAQ2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LEAQ2 [c] {s} (ADDQconst [d] x) y)
	// cond: ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB
	// result: (LEAQ2 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ2)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ2 [c] {s} x (ADDQconst [d] y))
	// cond: ssa.Is32Bit(int64(c)+2*int64(d)) && y.Op != ssaop.OpSB
	// result: (LEAQ2 [c+2*d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(ssa.Is32Bit(int64(c)+2*int64(d)) && y.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ2)
		v.AuxInt = ssa.Int32ToAuxInt(c + 2*d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ2 [c] {s} x z:(ADDQ y y))
	// cond: x != z
	// result: (LEAQ4 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		z := v_1
		if z.Op != ssaop.OpAMD64ADDQ {
			break
		}
		y := z.Args[1]
		if y != z.Args[0] || !(x != z) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ4)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ2 [c] {s} x (SHLQconst [2] y))
	// result: (LEAQ8 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(v_1.AuxInt) != 2 {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64LEAQ8)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ2 [0] {s} (ADDQ x x) x)
	// cond: s == nil
	// result: (SHLQconst [2] x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQ {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || x != v_1 || !(s == nil) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(2)
		v.AddArg(x)
		return true
	}
	// match: (LEAQ2 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB
	// result: (LEAQ2 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ2)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ2 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y))
	// cond: ssa.Is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil
	// result: (LEAQ4 [off1+2*off2] {sym1} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ1 {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		y := v_1.Args[1]
		if y != v_1.Args[0] || !(ssa.Is32Bit(int64(off1)+2*int64(off2)) && sym2 == nil) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ4)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + 2*off2)
		v.Aux = ssa.SymToAux(sym1)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ2 [off] {sym} x (MOVQconst [scale]))
	// cond: ssa.Is32Bit(int64(off)+int64(scale)*2)
	// result: (LEAQ [off+int32(scale)*2] {sym} x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		scale := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(ssa.Is32Bit(int64(off) + int64(scale)*2)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(off + int32(scale)*2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg(x)
		return true
	}
	// match: (LEAQ2 [off] {sym} x (MOVLconst [scale]))
	// cond: ssa.Is32Bit(int64(off)+int64(scale)*2)
	// result: (LEAQ [off+int32(scale)*2] {sym} x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		scale := ssa.AuxIntToInt32(v_1.AuxInt)
		if !(ssa.Is32Bit(int64(off) + int64(scale)*2)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(off + int32(scale)*2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LEAQ4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LEAQ4 [c] {s} (ADDQconst [d] x) y)
	// cond: ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB
	// result: (LEAQ4 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ4)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ4 [c] {s} x (ADDQconst [d] y))
	// cond: ssa.Is32Bit(int64(c)+4*int64(d)) && y.Op != ssaop.OpSB
	// result: (LEAQ4 [c+4*d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(ssa.Is32Bit(int64(c)+4*int64(d)) && y.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ4)
		v.AuxInt = ssa.Int32ToAuxInt(c + 4*d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ4 [c] {s} x z:(ADDQ y y))
	// cond: x != z
	// result: (LEAQ8 [c] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		z := v_1
		if z.Op != ssaop.OpAMD64ADDQ {
			break
		}
		y := z.Args[1]
		if y != z.Args[0] || !(x != z) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ8)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ4 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB
	// result: (LEAQ4 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ4)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ4 [off1] {sym1} x (LEAQ1 [off2] {sym2} y y))
	// cond: ssa.Is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil
	// result: (LEAQ8 [off1+4*off2] {sym1} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ1 {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		y := v_1.Args[1]
		if y != v_1.Args[0] || !(ssa.Is32Bit(int64(off1)+4*int64(off2)) && sym2 == nil) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ8)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + 4*off2)
		v.Aux = ssa.SymToAux(sym1)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ4 [off] {sym} x (MOVQconst [scale]))
	// cond: ssa.Is32Bit(int64(off)+int64(scale)*4)
	// result: (LEAQ [off+int32(scale)*4] {sym} x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		scale := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(ssa.Is32Bit(int64(off) + int64(scale)*4)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(off + int32(scale)*4)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg(x)
		return true
	}
	// match: (LEAQ4 [off] {sym} x (MOVLconst [scale]))
	// cond: ssa.Is32Bit(int64(off)+int64(scale)*4)
	// result: (LEAQ [off+int32(scale)*4] {sym} x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		scale := ssa.AuxIntToInt32(v_1.AuxInt)
		if !(ssa.Is32Bit(int64(off) + int64(scale)*4)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(off + int32(scale)*4)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LEAQ8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LEAQ8 [c] {s} (ADDQconst [d] x) y)
	// cond: ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB
	// result: (LEAQ8 [c+d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(c)+int64(d)) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ8)
		v.AuxInt = ssa.Int32ToAuxInt(c + d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ8 [c] {s} x (ADDQconst [d] y))
	// cond: ssa.Is32Bit(int64(c)+8*int64(d)) && y.Op != ssaop.OpSB
	// result: (LEAQ8 [c+8*d] {s} x y)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(ssa.Is32Bit(int64(c)+8*int64(d)) && y.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ8)
		v.AuxInt = ssa.Int32ToAuxInt(c + 8*d)
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ8 [off1] {sym1} (LEAQ [off2] {sym2} x) y)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB
	// result: (LEAQ8 [off1+off2] {ssa.MergeSym(sym1,sym2)} x y)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		x := v_0.Args[0]
		y := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && x.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ8)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(x, y)
		return true
	}
	// match: (LEAQ8 [off] {sym} x (MOVQconst [scale]))
	// cond: ssa.Is32Bit(int64(off)+int64(scale)*8)
	// result: (LEAQ [off+int32(scale)*8] {sym} x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		scale := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(ssa.Is32Bit(int64(off) + int64(scale)*8)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(off + int32(scale)*8)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg(x)
		return true
	}
	// match: (LEAQ8 [off] {sym} x (MOVLconst [scale]))
	// cond: ssa.Is32Bit(int64(off)+int64(scale)*8)
	// result: (LEAQ [off+int32(scale)*8] {sym} x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		scale := ssa.AuxIntToInt32(v_1.AuxInt)
		if !(ssa.Is32Bit(int64(off) + int64(scale)*8)) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.AuxInt = ssa.Int32ToAuxInt(off + int32(scale)*8)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LoweredPanicBoundsCR(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LoweredPanicBoundsCR [kind] {p} (MOVQconst [c]) mem)
	// result: (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:p.C, Cy:c}} mem)
	for {
		kind := ssa.AuxIntToInt64(v.AuxInt)
		p := ssa.AuxToPanicBoundsC(v.Aux)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_0.AuxInt)
		mem := v_1
		v.Reset(ssaop.OpAMD64LoweredPanicBoundsCC)
		v.AuxInt = ssa.Int64ToAuxInt(kind)
		v.Aux = ssa.PanicBoundsCCToAux(ssa.PanicBoundsCC{Cx: p.C, Cy: c})
		v.AddArg(mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LoweredPanicBoundsRC(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LoweredPanicBoundsRC [kind] {p} (MOVQconst [c]) mem)
	// result: (LoweredPanicBoundsCC [kind] {ssa.PanicBoundsCC{Cx:c, Cy:p.C}} mem)
	for {
		kind := ssa.AuxIntToInt64(v.AuxInt)
		p := ssa.AuxToPanicBoundsC(v.Aux)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_0.AuxInt)
		mem := v_1
		v.Reset(ssaop.OpAMD64LoweredPanicBoundsCC)
		v.AuxInt = ssa.Int64ToAuxInt(kind)
		v.Aux = ssa.PanicBoundsCCToAux(ssa.PanicBoundsCC{Cx: c, Cy: p.C})
		v.AddArg(mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64LoweredPanicBoundsRR(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LoweredPanicBoundsRR [kind] x (MOVQconst [c]) mem)
	// result: (LoweredPanicBoundsRC [kind] x {ssa.PanicBoundsC{C:c}} mem)
	for {
		kind := ssa.AuxIntToInt64(v.AuxInt)
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64LoweredPanicBoundsRC)
		v.AuxInt = ssa.Int64ToAuxInt(kind)
		v.Aux = ssa.PanicBoundsCToAux(ssa.PanicBoundsC{C: c})
		v.AddArg2(x, mem)
		return true
	}
	// match: (LoweredPanicBoundsRR [kind] (MOVQconst [c]) y mem)
	// result: (LoweredPanicBoundsCR [kind] {ssa.PanicBoundsC{C:c}} y mem)
	for {
		kind := ssa.AuxIntToInt64(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_0.AuxInt)
		y := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64LoweredPanicBoundsCR)
		v.AuxInt = ssa.Int64ToAuxInt(kind)
		v.Aux = ssa.PanicBoundsCToAux(ssa.PanicBoundsC{C: c})
		v.AddArg2(y, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBELstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVBELstore [i] {s} p x:(BSWAPL w) mem)
	// cond: x.Uses == 1
	// result: (MOVLstore [i] {s} p w mem)
	for {
		i := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		p := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64BSWAPL {
			break
		}
		w := x.Args[0]
		mem := v_2
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(i)
		v.Aux = ssa.SymToAux(s)
		v.AddArg3(p, w, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBEQstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVBEQstore [i] {s} p x:(BSWAPQ w) mem)
	// cond: x.Uses == 1
	// result: (MOVQstore [i] {s} p w mem)
	for {
		i := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		p := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64BSWAPQ {
			break
		}
		w := x.Args[0]
		mem := v_2
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstore)
		v.AuxInt = ssa.Int32ToAuxInt(i)
		v.Aux = ssa.SymToAux(s)
		v.AddArg3(p, w, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBEWstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVBEWstore [i] {s} p x:(ROLWconst [8] w) mem)
	// cond: x.Uses == 1
	// result: (MOVWstore [i] {s} p w mem)
	for {
		i := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		p := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64ROLWconst || ssa.AuxIntToInt8(x.AuxInt) != 8 {
			break
		}
		w := x.Args[0]
		mem := v_2
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWstore)
		v.AuxInt = ssa.Int32ToAuxInt(i)
		v.Aux = ssa.SymToAux(s)
		v.AddArg3(p, w, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBQSX(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVBQSX x:(MOVBload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVBload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBQSX x:(MOVWload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVWload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBQSX x:(MOVLload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBQSX x:(MOVQload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVBQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBQSX (ANDLconst [c] x))
	// cond: c & 0x80 == 0
	// result: (ANDLconst [c & 0x7f] x)
	for {
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(c&0x80 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c & 0x7f)
		v.AddArg(x)
		return true
	}
	// match: (MOVBQSX (MOVBQSX x))
	// result: (MOVBQSX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVBQSX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVBQSX)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBQSXload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVBQSXload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
	// cond: sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)
	// result: (MOVBQSX x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVBstore {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		x := v_1.Args[1]
		ptr2 := v_1.Args[0]
		if !(sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBQSX)
		v.AddArg(x)
		return true
	}
	// match: (MOVBQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVBQSXload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBQSXload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVBQSXload [off] {sym} (SB) _)
	// cond: ssa.SymIsRO(sym)
	// result: (MOVQconst [int64(int8(ssa.Read8(sym, int64(off))))])
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpSB || !(ssa.SymIsRO(sym)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(int8(ssa.Read8(sym, int64(off)))))
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBQZX(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVBQZX x:(MOVBload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVBload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBQZX x:(MOVWload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVWload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBQZX x:(MOVLload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBQZX x:(MOVQload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVBload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVBload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBQZX (ANDLconst [c] x))
	// result: (ANDLconst [c & 0xff] x)
	for {
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c & 0xff)
		v.AddArg(x)
		return true
	}
	// match: (MOVBQZX (MOVBQZX x))
	// result: (MOVBQZX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVBQZX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVBQZX)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBatomicload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVBatomicload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVBatomicload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBatomicload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVBatomicload [off1+off2] {ssa.MergeSym(sym1, sym2)} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBatomicload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _))
	// cond: sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)
	// result: (MOVBQZX x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVBstore {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		x := v_1.Args[1]
		ptr2 := v_1.Args[0]
		if !(sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBQZX)
		v.AddArg(x)
		return true
	}
	// match: (MOVBload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVBload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVBload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVBload [off] {sym} (SB) _)
	// cond: ssa.SymIsRO(sym)
	// result: (MOVLconst [int32(ssa.Read8(sym, int64(off)))])
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpSB || !(ssa.SymIsRO(sym)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(ssa.Read8(sym, int64(off))))
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVBstore [off] {sym} ptr y:(SETL x) mem)
	// cond: y.Uses == 1
	// result: (SETLstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETL {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETLE x) mem)
	// cond: y.Uses == 1
	// result: (SETLEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETLE {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETLEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETG x) mem)
	// cond: y.Uses == 1
	// result: (SETGstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETG {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETGstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETGE x) mem)
	// cond: y.Uses == 1
	// result: (SETGEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETGE {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETGEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETEQ x) mem)
	// cond: y.Uses == 1
	// result: (SETEQstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETEQ {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETNE x) mem)
	// cond: y.Uses == 1
	// result: (SETNEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETNE {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETNEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETB x) mem)
	// cond: y.Uses == 1
	// result: (SETBstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETB {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETBE x) mem)
	// cond: y.Uses == 1
	// result: (SETBEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETBE {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETA x) mem)
	// cond: y.Uses == 1
	// result: (SETAstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETA {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr y:(SETAE x) mem)
	// cond: y.Uses == 1
	// result: (SETAEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SETAE {
			break
		}
		x := y.Args[0]
		mem := v_2
		if !(y.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr (MOVBQSX x) mem)
	// result: (MOVBstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVBQSX {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr (MOVBQZX x) mem)
	// result: (MOVBstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVBQZX {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVBstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVBstore [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (MOVBstoreconst [ssa.MakeValAndOff(int32(int8(c)),off)] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(int8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr (MOVQconst [c]) mem)
	// result: (MOVBstoreconst [ssa.MakeValAndOff(int32(int8(c)),off)] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(int8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVBstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVBload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)
	// result: (ADDBconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVBload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVBload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)
	// result: (ANDBconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVBload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr a:(ORLconst [c] l:(MOVBload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)
	// result: (ORBconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ORLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVBload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr a:(XORLconst [c] l:(MOVBload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)
	// result: (XORBconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64XORLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVBload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBstore [off] {sym} ptr (KMOVBi mask) mem)
	// result: (KMOVBstore [off] {sym} ptr mask mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64KMOVBi {
			break
		}
		mask := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64KMOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVBstoreconst(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVBstoreconst [sc] {s} (ADDQconst [off] ptr) mem)
	// cond: ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVBstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {s} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVBstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
	// cond: ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVBstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {ssa.MergeSym(sym1, sym2)} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLQSX(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVLQSX x:(MOVLload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVLQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLQSX x:(MOVQload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVLQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVLQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLQSX (ANDLconst [c] x))
	// cond: uint32(c) & 0x80000000 == 0
	// result: (ANDLconst [c & 0x7fffffff] x)
	for {
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(uint32(c)&0x80000000 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c & 0x7fffffff)
		v.AddArg(x)
		return true
	}
	// match: (MOVLQSX (MOVLQSX x))
	// result: (MOVLQSX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVLQSX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVLQSX)
		v.AddArg(x)
		return true
	}
	// match: (MOVLQSX (MOVWQSX x))
	// result: (MOVWQSX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVWQSX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVWQSX)
		v.AddArg(x)
		return true
	}
	// match: (MOVLQSX (MOVBQSX x))
	// result: (MOVBQSX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVBQSX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVBQSX)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLQSXload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	// match: (MOVLQSXload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _))
	// cond: sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)
	// result: (MOVLQSX x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLstore {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		x := v_1.Args[1]
		ptr2 := v_1.Args[0]
		if !(sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLQSX)
		v.AddArg(x)
		return true
	}
	// match: (MOVLQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVLQSXload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLQSXload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVLQSXload [off] {sym} (SB) _)
	// cond: ssa.SymIsRO(sym)
	// result: (MOVQconst [int64(int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpSB || !(ssa.SymIsRO(sym)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))))
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLQZX(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVLQZX x:(MOVLload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVLload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLQZX x:(MOVQload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVLload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVLload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLQZX (ANDLconst [c] x))
	// result: (ANDLconst [c] x)
	for {
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (MOVLQZX (MOVLQZX x))
	// result: (MOVLQZX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVLQZX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVLQZX)
		v.AddArg(x)
		return true
	}
	// match: (MOVLQZX (MOVWQZX x))
	// result: (MOVWQZX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVWQZX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVWQZX)
		v.AddArg(x)
		return true
	}
	// match: (MOVLQZX (MOVBQZX x))
	// result: (MOVBQZX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVBQZX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVBQZX)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLatomicload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVLatomicload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVLatomicload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLatomicload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVLatomicload [off1+off2] {ssa.MergeSym(sym1, sym2)} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLatomicload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLf2i(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVLf2i <t> (Arg <u> [off] {sym}))
	// cond: t.Size() == u.Size()
	// result: @b.Func.Entry (Arg <t> [off] {sym})
	for {
		t := v.Type
		if v_0.Op != ssaop.OpArg {
			break
		}
		u := v_0.Type
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym := ssa.AuxToSym(v_0.Aux)
		if !(t.Size() == u.Size()) {
			break
		}
		b = b.Func.Entry
		v0 := b.NewValue0(v.Pos, ssaop.OpArg, t)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLi2f(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVLi2f <t> (Arg <u> [off] {sym}))
	// cond: t.Size() == u.Size()
	// result: @b.Func.Entry (Arg <t> [off] {sym})
	for {
		t := v.Type
		if v_0.Op != ssaop.OpArg {
			break
		}
		u := v_0.Type
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym := ssa.AuxToSym(v_0.Aux)
		if !(t.Size() == u.Size()) {
			break
		}
		b = b.Func.Entry
		v0 := b.NewValue0(v.Pos, ssaop.OpArg, t)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	// match: (MOVLload [off] {sym} ptr (MOVLstore [off2] {sym2} ptr2 x _))
	// cond: sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)
	// result: (MOVLQZX x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLstore {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		x := v_1.Args[1]
		ptr2 := v_1.Args[0]
		if !(sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLQZX)
		v.AddArg(x)
		return true
	}
	// match: (MOVLload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVLload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVLload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVLload [off] {sym} ptr (MOVSSstore [off] {sym} ptr val _))
	// result: (MOVLf2i val)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVSSstore || ssa.AuxIntToInt32(v_1.AuxInt) != off || ssa.AuxToSym(v_1.Aux) != sym {
			break
		}
		val := v_1.Args[1]
		if ptr != v_1.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLf2i)
		v.AddArg(val)
		return true
	}
	// match: (MOVLload <t> [off] {sym} (SB) _)
	// cond: ssa.SymIsRO(sym) && ssa.Is32BitInt(t)
	// result: (MOVLconst [int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
	for {
		t := v.Type
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpSB || !(ssa.SymIsRO(sym) && ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder)))
		return true
	}
	// match: (MOVLload <t> [off] {sym} (SB) _)
	// cond: ssa.SymIsRO(sym) && ssa.Is64BitInt(t)
	// result: (MOVQconst [int64(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
	for {
		t := v.Type
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpSB || !(ssa.SymIsRO(sym) && ssa.Is64BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(ssa.Read32(sym, int64(off), config.Ctxt.Arch.ByteOrder)))
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVLstore [off] {sym} ptr (MOVLQSX x) mem)
	// result: (MOVLstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLQSX {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVLstore [off] {sym} ptr (MOVLQZX x) mem)
	// result: (MOVLstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLQZX {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVLstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVLstore [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVLstore [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (MOVLstoreconst [ssa.MakeValAndOff(int32(c),off)] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLstore [off] {sym} ptr (MOVQconst [c]) mem)
	// result: (MOVLstoreconst [ssa.MakeValAndOff(int32(c),off)] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVLstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (MOVLstore {sym} [off] ptr y:(ADDLload x [off] {sym} ptr mem) mem)
	// cond: y.Uses==1 && ssa.Clobber(y)
	// result: (ADDLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ADDLload || ssa.AuxIntToInt32(y.AuxInt) != off || ssa.AuxToSym(y.Aux) != sym {
			break
		}
		mem := y.Args[2]
		x := y.Args[0]
		if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && ssa.Clobber(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVLstore {sym} [off] ptr y:(ANDLload x [off] {sym} ptr mem) mem)
	// cond: y.Uses==1 && ssa.Clobber(y)
	// result: (ANDLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ANDLload || ssa.AuxIntToInt32(y.AuxInt) != off || ssa.AuxToSym(y.Aux) != sym {
			break
		}
		mem := y.Args[2]
		x := y.Args[0]
		if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && ssa.Clobber(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVLstore {sym} [off] ptr y:(ORLload x [off] {sym} ptr mem) mem)
	// cond: y.Uses==1 && ssa.Clobber(y)
	// result: (ORLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ORLload || ssa.AuxIntToInt32(y.AuxInt) != off || ssa.AuxToSym(y.Aux) != sym {
			break
		}
		mem := y.Args[2]
		x := y.Args[0]
		if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && ssa.Clobber(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVLstore {sym} [off] ptr y:(XORLload x [off] {sym} ptr mem) mem)
	// cond: y.Uses==1 && ssa.Clobber(y)
	// result: (XORLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64XORLload || ssa.AuxIntToInt32(y.AuxInt) != off || ssa.AuxToSym(y.Aux) != sym {
			break
		}
		mem := y.Args[2]
		x := y.Args[0]
		if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && ssa.Clobber(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVLstore {sym} [off] ptr y:(ADDL l:(MOVLload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (ADDLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ADDL {
			break
		}
		_ = y.Args[1]
		y_0 := y.Args[0]
		y_1 := y.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 {
			l := y_0
			if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
				continue
			}
			mem := l.Args[1]
			if ptr != l.Args[0] {
				continue
			}
			x := y_1
			if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADDLmodify)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(ptr, x, mem)
			return true
		}
		break
	}
	// match: (MOVLstore {sym} [off] ptr y:(SUBL l:(MOVLload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (SUBLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SUBL {
			break
		}
		x := y.Args[1]
		l := y.Args[0]
		if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVLstore {sym} [off] ptr y:(ANDL l:(MOVLload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (ANDLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ANDL {
			break
		}
		_ = y.Args[1]
		y_0 := y.Args[0]
		y_1 := y.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 {
			l := y_0
			if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
				continue
			}
			mem := l.Args[1]
			if ptr != l.Args[0] {
				continue
			}
			x := y_1
			if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ANDLmodify)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(ptr, x, mem)
			return true
		}
		break
	}
	// match: (MOVLstore {sym} [off] ptr y:(ORL l:(MOVLload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (ORLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ORL {
			break
		}
		_ = y.Args[1]
		y_0 := y.Args[0]
		y_1 := y.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 {
			l := y_0
			if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
				continue
			}
			mem := l.Args[1]
			if ptr != l.Args[0] {
				continue
			}
			x := y_1
			if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ORLmodify)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(ptr, x, mem)
			return true
		}
		break
	}
	// match: (MOVLstore {sym} [off] ptr y:(XORL l:(MOVLload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (XORLmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64XORL {
			break
		}
		_ = y.Args[1]
		y_0 := y.Args[0]
		y_1 := y.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 {
			l := y_0
			if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
				continue
			}
			mem := l.Args[1]
			if ptr != l.Args[0] {
				continue
			}
			x := y_1
			if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64XORLmodify)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(ptr, x, mem)
			return true
		}
		break
	}
	// match: (MOVLstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)
	// result: (ADDLconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)
	// result: (ANDLconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLstore [off] {sym} ptr a:(ORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)
	// result: (ORLconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ORLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLstore [off] {sym} ptr a:(XORLconst [c] l:(MOVLload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)
	// result: (XORLconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64XORLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVLload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLstore [off] {sym} ptr (MOVLf2i val) mem)
	// result: (MOVSSstore [off] {sym} ptr val mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLf2i {
			break
		}
		val := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVSSstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVLstore [i] {s} p x:(BSWAPL w) mem)
	// cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3
	// result: (MOVBELstore [i] {s} p w mem)
	for {
		i := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		p := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64BSWAPL {
			break
		}
		w := x.Args[0]
		mem := v_2
		if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBELstore)
		v.AuxInt = ssa.Int32ToAuxInt(i)
		v.Aux = ssa.SymToAux(s)
		v.AddArg3(p, w, mem)
		return true
	}
	// match: (MOVLstore [off] {sym} ptr (KMOVDi mask) mem)
	// result: (KMOVDstore [off] {sym} ptr mask mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64KMOVDi {
			break
		}
		mask := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64KMOVDstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVLstoreconst(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVLstoreconst [sc] {s} (ADDQconst [off] ptr) mem)
	// cond: ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVLstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {s} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVLstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
	// cond: ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVLstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {ssa.MergeSym(sym1, sym2)} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVOload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVOload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVOload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVOload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVOload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVOload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVOload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVOstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	typ := &b.Func.Config.Types
	// match: (MOVOstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVOstore [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVOstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVOstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVOstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVOstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (MOVOstore [dstOff] {dstSym} ptr (MOVOload [srcOff] {srcSym} (SB) _) mem)
	// cond: ssa.SymIsRO(srcSym)
	// result: (MOVQstore [dstOff+8] {dstSym} ptr (MOVQconst [int64(ssa.Read64(srcSym, int64(srcOff)+8, config.Ctxt.Arch.ByteOrder))]) (MOVQstore [dstOff] {dstSym} ptr (MOVQconst [int64(ssa.Read64(srcSym, int64(srcOff), config.Ctxt.Arch.ByteOrder))]) mem))
	for {
		dstOff := ssa.AuxIntToInt32(v.AuxInt)
		dstSym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVOload {
			break
		}
		srcOff := ssa.AuxIntToInt32(v_1.AuxInt)
		srcSym := ssa.AuxToSym(v_1.Aux)
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpSB {
			break
		}
		mem := v_2
		if !(ssa.SymIsRO(srcSym)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstore)
		v.AuxInt = ssa.Int32ToAuxInt(dstOff + 8)
		v.Aux = ssa.SymToAux(dstSym)
		v0 := b.NewValue0(v_1.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v0.AuxInt = ssa.Int64ToAuxInt(int64(ssa.Read64(srcSym, int64(srcOff)+8, config.Ctxt.Arch.ByteOrder)))
		v1 := b.NewValue0(v_1.Pos, ssaop.OpAMD64MOVQstore, types.TypeMem)
		v1.AuxInt = ssa.Int32ToAuxInt(dstOff)
		v1.Aux = ssa.SymToAux(dstSym)
		v2 := b.NewValue0(v_1.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v2.AuxInt = ssa.Int64ToAuxInt(int64(ssa.Read64(srcSym, int64(srcOff), config.Ctxt.Arch.ByteOrder)))
		v1.AddArg3(ptr, v2, mem)
		v.AddArg3(ptr, v0, v1)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVOstoreconst(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVOstoreconst [sc] {s} (ADDQconst [off] ptr) mem)
	// cond: ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVOstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {s} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVOstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVOstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
	// cond: ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVOstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {ssa.MergeSym(sym1, sym2)} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVOstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVQatomicload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVQatomicload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVQatomicload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQatomicload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQatomicload [off1] {sym1} (LEAQ [off2] {sym2} ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVQatomicload [off1+off2] {ssa.MergeSym(sym1, sym2)} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQatomicload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVQf2i(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVQf2i <t> (Arg <u> [off] {sym}))
	// cond: t.Size() == u.Size()
	// result: @b.Func.Entry (Arg <t> [off] {sym})
	for {
		t := v.Type
		if v_0.Op != ssaop.OpArg {
			break
		}
		u := v_0.Type
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym := ssa.AuxToSym(v_0.Aux)
		if !(t.Size() == u.Size()) {
			break
		}
		b = b.Func.Entry
		v0 := b.NewValue0(v.Pos, ssaop.OpArg, t)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVQi2f(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVQi2f <t> (Arg <u> [off] {sym}))
	// cond: t.Size() == u.Size()
	// result: @b.Func.Entry (Arg <t> [off] {sym})
	for {
		t := v.Type
		if v_0.Op != ssaop.OpArg {
			break
		}
		u := v_0.Type
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym := ssa.AuxToSym(v_0.Aux)
		if !(t.Size() == u.Size()) {
			break
		}
		b = b.Func.Entry
		v0 := b.NewValue0(v.Pos, ssaop.OpArg, t)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVQload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	// match: (MOVQload [off] {sym} ptr (MOVQstore [off2] {sym2} ptr2 x _))
	// cond: sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)
	// result: x
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQstore {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		x := v_1.Args[1]
		ptr2 := v_1.Args[0]
		if !(sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (MOVQload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVQload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVQload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVQload [off] {sym} ptr (MOVSDstore [off] {sym} ptr val _))
	// result: (MOVQf2i val)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVSDstore || ssa.AuxIntToInt32(v_1.AuxInt) != off || ssa.AuxToSym(v_1.Aux) != sym {
			break
		}
		val := v_1.Args[1]
		if ptr != v_1.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQf2i)
		v.AddArg(val)
		return true
	}
	// match: (MOVQload [off] {sym} (SB) _)
	// cond: ssa.SymIsRO(sym)
	// result: (MOVQconst [int64(ssa.Read64(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpSB || !(ssa.SymIsRO(sym)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(ssa.Read64(sym, int64(off), config.Ctxt.Arch.ByteOrder)))
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVQstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVQstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVQstore [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVQstore [off] {sym} ptr (MOVQconst [c]) mem)
	// cond: validVal(c)
	// result: (MOVQstoreconst [ssa.MakeValAndOff(int32(c),off)] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		if !(validVal(c)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVQstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (MOVQstore {sym} [off] ptr y:(ADDQload x [off] {sym} ptr mem) mem)
	// cond: y.Uses==1 && ssa.Clobber(y)
	// result: (ADDQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ADDQload || ssa.AuxIntToInt32(y.AuxInt) != off || ssa.AuxToSym(y.Aux) != sym {
			break
		}
		mem := y.Args[2]
		x := y.Args[0]
		if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && ssa.Clobber(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVQstore {sym} [off] ptr y:(ANDQload x [off] {sym} ptr mem) mem)
	// cond: y.Uses==1 && ssa.Clobber(y)
	// result: (ANDQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ANDQload || ssa.AuxIntToInt32(y.AuxInt) != off || ssa.AuxToSym(y.Aux) != sym {
			break
		}
		mem := y.Args[2]
		x := y.Args[0]
		if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && ssa.Clobber(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVQstore {sym} [off] ptr y:(ORQload x [off] {sym} ptr mem) mem)
	// cond: y.Uses==1 && ssa.Clobber(y)
	// result: (ORQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ORQload || ssa.AuxIntToInt32(y.AuxInt) != off || ssa.AuxToSym(y.Aux) != sym {
			break
		}
		mem := y.Args[2]
		x := y.Args[0]
		if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && ssa.Clobber(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVQstore {sym} [off] ptr y:(XORQload x [off] {sym} ptr mem) mem)
	// cond: y.Uses==1 && ssa.Clobber(y)
	// result: (XORQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64XORQload || ssa.AuxIntToInt32(y.AuxInt) != off || ssa.AuxToSym(y.Aux) != sym {
			break
		}
		mem := y.Args[2]
		x := y.Args[0]
		if ptr != y.Args[1] || mem != v_2 || !(y.Uses == 1 && ssa.Clobber(y)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVQstore {sym} [off] ptr y:(ADDQ l:(MOVQload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (ADDQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ADDQ {
			break
		}
		_ = y.Args[1]
		y_0 := y.Args[0]
		y_1 := y.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 {
			l := y_0
			if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
				continue
			}
			mem := l.Args[1]
			if ptr != l.Args[0] {
				continue
			}
			x := y_1
			if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ADDQmodify)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(ptr, x, mem)
			return true
		}
		break
	}
	// match: (MOVQstore {sym} [off] ptr y:(SUBQ l:(MOVQload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (SUBQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64SUBQ {
			break
		}
		x := y.Args[1]
		l := y.Args[0]
		if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		if ptr != l.Args[0] || mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVQstore {sym} [off] ptr y:(ANDQ l:(MOVQload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (ANDQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ANDQ {
			break
		}
		_ = y.Args[1]
		y_0 := y.Args[0]
		y_1 := y.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 {
			l := y_0
			if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
				continue
			}
			mem := l.Args[1]
			if ptr != l.Args[0] {
				continue
			}
			x := y_1
			if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ANDQmodify)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(ptr, x, mem)
			return true
		}
		break
	}
	// match: (MOVQstore {sym} [off] ptr y:(ORQ l:(MOVQload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (ORQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64ORQ {
			break
		}
		_ = y.Args[1]
		y_0 := y.Args[0]
		y_1 := y.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 {
			l := y_0
			if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
				continue
			}
			mem := l.Args[1]
			if ptr != l.Args[0] {
				continue
			}
			x := y_1
			if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ORQmodify)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(ptr, x, mem)
			return true
		}
		break
	}
	// match: (MOVQstore {sym} [off] ptr y:(XORQ l:(MOVQload [off] {sym} ptr mem) x) mem)
	// cond: y.Uses==1 && l.Uses==1 && ssa.Clobber(y, l)
	// result: (XORQmodify [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		y := v_1
		if y.Op != ssaop.OpAMD64XORQ {
			break
		}
		_ = y.Args[1]
		y_0 := y.Args[0]
		y_1 := y.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, y_0, y_1 = _i0+1, y_1, y_0 {
			l := y_0
			if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
				continue
			}
			mem := l.Args[1]
			if ptr != l.Args[0] {
				continue
			}
			x := y_1
			if mem != v_2 || !(y.Uses == 1 && l.Uses == 1 && ssa.Clobber(y, l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64XORQmodify)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(ptr, x, mem)
			return true
		}
		break
	}
	// match: (MOVQstore {sym} [off] ptr x:(BTSQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem)
	// cond: x.Uses == 1 && l.Uses == 1 && ssa.Clobber(x, l)
	// result: (BTSQconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64BTSQconst {
			break
		}
		c := ssa.AuxIntToInt8(x.AuxInt)
		l := x.Args[0]
		if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && ssa.Clobber(x, l)) {
			break
		}
		v.Reset(ssaop.OpAMD64BTSQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstore {sym} [off] ptr x:(BTRQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem)
	// cond: x.Uses == 1 && l.Uses == 1 && ssa.Clobber(x, l)
	// result: (BTRQconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64BTRQconst {
			break
		}
		c := ssa.AuxIntToInt8(x.AuxInt)
		l := x.Args[0]
		if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && ssa.Clobber(x, l)) {
			break
		}
		v.Reset(ssaop.OpAMD64BTRQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstore {sym} [off] ptr x:(BTCQconst [c] l:(MOVQload {sym} [off] ptr mem)) mem)
	// cond: x.Uses == 1 && l.Uses == 1 && ssa.Clobber(x, l)
	// result: (BTCQconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64BTCQconst {
			break
		}
		c := ssa.AuxIntToInt8(x.AuxInt)
		l := x.Args[0]
		if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		if ptr != l.Args[0] || mem != v_2 || !(x.Uses == 1 && l.Uses == 1 && ssa.Clobber(x, l)) {
			break
		}
		v.Reset(ssaop.OpAMD64BTCQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstore [off] {sym} ptr a:(ADDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)
	// result: (ADDQconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstore [off] {sym} ptr a:(ANDQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)
	// result: (ANDQconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstore [off] {sym} ptr a:(ORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)
	// result: (ORQconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ORQconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstore [off] {sym} ptr a:(XORQconst [c] l:(MOVQload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)
	// result: (XORQconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64XORQconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVQload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstore [off] {sym} ptr (MOVQf2i val) mem)
	// result: (MOVSDstore [off] {sym} ptr val mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQf2i {
			break
		}
		val := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVSDstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVQstore [i] {s} p x:(BSWAPQ w) mem)
	// cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3
	// result: (MOVBEQstore [i] {s} p w mem)
	for {
		i := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		p := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64BSWAPQ {
			break
		}
		w := x.Args[0]
		mem := v_2
		if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBEQstore)
		v.AuxInt = ssa.Int32ToAuxInt(i)
		v.Aux = ssa.SymToAux(s)
		v.AddArg3(p, w, mem)
		return true
	}
	// match: (MOVQstore [off] {sym} ptr (KMOVQi mask) mem)
	// result: (KMOVQstore [off] {sym} ptr mask mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64KMOVQi {
			break
		}
		mask := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64KMOVQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVQstoreconst(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVQstoreconst [sc] {s} (ADDQconst [off] ptr) mem)
	// cond: ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVQstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {s} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
	// cond: ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVQstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {ssa.MergeSym(sym1, sym2)} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVQstoreconst [c] {s} p1 x:(MOVQstoreconst [a] {s} p0 mem))
	// cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && ssa.SetPos(v, x.Pos) && ssa.Clobber(x)
	// result: (MOVOstoreconst [ssa.MakeValAndOff(0,a.Off())] {s} p0 mem)
	for {
		c := ssa.AuxIntToValAndOff(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		p1 := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64MOVQstoreconst {
			break
		}
		a := ssa.AuxIntToValAndOff(x.AuxInt)
		if ssa.AuxToSym(x.Aux) != s {
			break
		}
		mem := x.Args[1]
		p0 := x.Args[0]
		if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && ssa.SetPos(v, x.Pos) && ssa.Clobber(x)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVOstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, a.Off()))
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(p0, mem)
		return true
	}
	// match: (MOVQstoreconst [a] {s} p0 x:(MOVQstoreconst [c] {s} p1 mem))
	// cond: x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && ssa.SetPos(v, x.Pos) && ssa.Clobber(x)
	// result: (MOVOstoreconst [ssa.MakeValAndOff(0,a.Off())] {s} p0 mem)
	for {
		a := ssa.AuxIntToValAndOff(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		p0 := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64MOVQstoreconst {
			break
		}
		c := ssa.AuxIntToValAndOff(x.AuxInt)
		if ssa.AuxToSym(x.Aux) != s {
			break
		}
		mem := x.Args[1]
		p1 := x.Args[0]
		if !(x.Uses == 1 && sequentialAddresses(p0, p1, int64(a.Off()+8-c.Off())) && a.Val() == 0 && c.Val() == 0 && ssa.SetPos(v, x.Pos) && ssa.Clobber(x)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVOstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, a.Off()))
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(p0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVSDload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVSDload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVSDload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVSDload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVSDload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVSDload [off] {sym} ptr (MOVQstore [off] {sym} ptr val _))
	// result: (MOVQi2f val)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQstore || ssa.AuxIntToInt32(v_1.AuxInt) != off || ssa.AuxToSym(v_1.Aux) != sym {
			break
		}
		val := v_1.Args[1]
		if ptr != v_1.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQi2f)
		v.AddArg(val)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVSDstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (MOVSDstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVSDstore [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSDstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVSDstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVSDstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSDstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (MOVSDstore [off] {sym} ptr (MOVQi2f val) mem)
	// result: (MOVQstore [off] {sym} ptr val mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQi2f {
			break
		}
		val := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVSDstore [off] {sym} ptr (MOVSDconst [f]) mem)
	// cond: f == f
	// result: (MOVQstore [off] {sym} ptr (MOVQconst [int64(math.Float64bits(f))]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVSDconst {
			break
		}
		f := ssa.AuxIntToFloat64(v_1.AuxInt)
		mem := v_2
		if !(f == f) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v0.AuxInt = ssa.Int64ToAuxInt(int64(math.Float64bits(f)))
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVSSload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVSSload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVSSload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVSSload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVSSload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVSSload [off] {sym} ptr (MOVLstore [off] {sym} ptr val _))
	// result: (MOVLi2f val)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLstore || ssa.AuxIntToInt32(v_1.AuxInt) != off || ssa.AuxToSym(v_1.Aux) != sym {
			break
		}
		val := v_1.Args[1]
		if ptr != v_1.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLi2f)
		v.AddArg(val)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVSSstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (MOVSSstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVSSstore [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSSstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVSSstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVSSstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSSstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (MOVSSstore [off] {sym} ptr (MOVLi2f val) mem)
	// result: (MOVLstore [off] {sym} ptr val mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLi2f {
			break
		}
		val := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVSSstore [off] {sym} ptr (MOVSSconst [f]) mem)
	// cond: f == f
	// result: (MOVLstore [off] {sym} ptr (MOVLconst [int32(math.Float32bits(f))]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVSSconst {
			break
		}
		f := ssa.AuxIntToFloat32(v_1.AuxInt)
		mem := v_2
		if !(f == f) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(int32(math.Float32bits(f)))
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVWQSX(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVWQSX x:(MOVWload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVWload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVWQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWQSX x:(MOVLload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVWQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWQSX x:(MOVQload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVWQSXload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVWQSXload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWQSX (ANDLconst [c] x))
	// cond: c & 0x8000 == 0
	// result: (ANDLconst [c & 0x7fff] x)
	for {
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(c&0x8000 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c & 0x7fff)
		v.AddArg(x)
		return true
	}
	// match: (MOVWQSX (MOVWQSX x))
	// result: (MOVWQSX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVWQSX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVWQSX)
		v.AddArg(x)
		return true
	}
	// match: (MOVWQSX (MOVBQSX x))
	// result: (MOVBQSX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVBQSX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVBQSX)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVWQSXload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	// match: (MOVWQSXload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
	// cond: sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)
	// result: (MOVWQSX x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVWstore {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		x := v_1.Args[1]
		ptr2 := v_1.Args[0]
		if !(sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWQSX)
		v.AddArg(x)
		return true
	}
	// match: (MOVWQSXload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVWQSXload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWQSXload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVWQSXload [off] {sym} (SB) _)
	// cond: ssa.SymIsRO(sym)
	// result: (MOVQconst [int64(int16(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder)))])
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpSB || !(ssa.SymIsRO(sym)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(int16(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder))))
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVWQZX(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (MOVWQZX x:(MOVWload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVWload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVWload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWQZX x:(MOVLload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVWload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWQZX x:(MOVQload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (MOVWload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64MOVWload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWQZX (ANDLconst [c] x))
	// result: (ANDLconst [c & 0xffff] x)
	for {
		if v_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c & 0xffff)
		v.AddArg(x)
		return true
	}
	// match: (MOVWQZX (MOVWQZX x))
	// result: (MOVWQZX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVWQZX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVWQZX)
		v.AddArg(x)
		return true
	}
	// match: (MOVWQZX (MOVBQZX x))
	// result: (MOVBQZX x)
	for {
		if v_0.Op != ssaop.OpAMD64MOVBQZX {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MOVBQZX)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVWload(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	// match: (MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _))
	// cond: sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)
	// result: (MOVWQZX x)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVWstore {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		x := v_1.Args[1]
		ptr2 := v_1.Args[0]
		if !(sym == sym2 && off == off2 && ssa.IsSamePtr(ptr, ptr2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWQZX)
		v.AddArg(x)
		return true
	}
	// match: (MOVWload [off1] {sym} (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVWload [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWload [off1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVWload [off1+off2] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	// match: (MOVWload [off] {sym} (SB) _)
	// cond: ssa.SymIsRO(sym)
	// result: (MOVLconst [int32(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder))])
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpSB || !(ssa.SymIsRO(sym)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(ssa.Read16(sym, int64(off), config.Ctxt.Arch.ByteOrder)))
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVWstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVWstore [off] {sym} ptr (MOVWQSX x) mem)
	// result: (MOVWstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVWQSX {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVWstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVWstore [off] {sym} ptr (MOVWQZX x) mem)
	// result: (MOVWstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVWQZX {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVWstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (MOVWstore [off1] {sym} (ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MOVWstore [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (MOVWstore [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (MOVWstoreconst [ssa.MakeValAndOff(int32(int16(c)),off)] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVWstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(int16(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWstore [off] {sym} ptr (MOVQconst [c]) mem)
	// result: (MOVWstoreconst [ssa.MakeValAndOff(int32(int16(c)),off)] {sym} ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVWstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(int16(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MOVWstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (MOVWstore [off] {sym} ptr a:(ADDLconst [c] l:(MOVWload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)
	// result: (ADDWconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVWload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWstore [off] {sym} ptr a:(ANDLconst [c] l:(MOVWload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)
	// result: (ANDWconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVWload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWstore [off] {sym} ptr a:(ORLconst [c] l:(MOVWload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)
	// result: (ORWconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64ORLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVWload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWstore [off] {sym} ptr a:(XORLconst [c] l:(MOVWload [off] {sym} ptr2 mem)) mem)
	// cond: ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)
	// result: (XORWconstmodify {sym} [ssa.MakeValAndOff(int32(c),off)] ptr mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		a := v_1
		if a.Op != ssaop.OpAMD64XORLconst {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		l := a.Args[0]
		if l.Op != ssaop.OpAMD64MOVWload || ssa.AuxIntToInt32(l.AuxInt) != off || ssa.AuxToSym(l.Aux) != sym {
			break
		}
		mem := l.Args[1]
		ptr2 := l.Args[0]
		if mem != v_2 || !(ssa.IsSamePtr(ptr, ptr2) && a.Uses == 1 && l.Uses == 1 && c == int32(int8(c)) && ssa.Clobber(l, a)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(c), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWstore [i] {s} p x:(ROLWconst [8] w) mem)
	// cond: x.Uses == 1 && buildcfg.GOAMD64 >= 3
	// result: (MOVBEWstore [i] {s} p w mem)
	for {
		i := ssa.AuxIntToInt32(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		p := v_0
		x := v_1
		if x.Op != ssaop.OpAMD64ROLWconst || ssa.AuxIntToInt8(x.AuxInt) != 8 {
			break
		}
		w := x.Args[0]
		mem := v_2
		if !(x.Uses == 1 && buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBEWstore)
		v.AuxInt = ssa.Int32ToAuxInt(i)
		v.Aux = ssa.SymToAux(s)
		v.AddArg3(p, w, mem)
		return true
	}
	// match: (MOVWstore [off] {sym} ptr (KMOVWi mask) mem)
	// result: (KMOVWstore [off] {sym} ptr mask mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64KMOVWi {
			break
		}
		mask := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64KMOVWstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MOVWstoreconst(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MOVWstoreconst [sc] {s} (ADDQconst [off] ptr) mem)
	// cond: ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVWstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {s} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		s := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(s)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (MOVWstoreconst [sc] {sym1} (LEAQ [off] {sym2} ptr) mem)
	// cond: ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)
	// result: (MOVWstoreconst [ssa.ValAndOff(sc).AddOffset32(off)] {ssa.MergeSym(sym1, sym2)} ptr mem)
	for {
		sc := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		ptr := v_0.Args[0]
		mem := v_1
		if !(ssa.CanMergeSym(sym1, sym2) && ssa.ValAndOff(sc).CanAdd32(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(sc).AddOffset32(off))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MULL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MULL x (MOVLconst [c]))
	// result: (MULLconst [c] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			v.Reset(ssaop.OpAMD64MULLconst)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg(x)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64MULLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	// match: (MULLconst [c] (MULLconst [d] x))
	// result: (MULLconst [c * d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MULLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64MULLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c * d)
		v.AddArg(x)
		return true
	}
	// match: (MULLconst [ 0] _)
	// result: (MOVLconst [0])
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (MULLconst [ 1] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (MULLconst [c] x)
	// cond: v.Type.Size() <= 4 && ssa.CanMulStrengthReduce32(config, c)
	// result: {ssa.MulStrengthReduce32(v, x, c)}
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if !(v.Type.Size() <= 4 && ssa.CanMulStrengthReduce32(config, c)) {
			break
		}
		v.CopyOf(ssa.MulStrengthReduce32(v, x, c))
		return true
	}
	// match: (MULLconst [c] (MOVLconst [d]))
	// result: (MOVLconst [c*d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c * d)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MULQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MULQ x (MOVQconst [c]))
	// cond: ssa.Is32Bit(c)
	// result: (MULQconst [int32(c)] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1.AuxInt)
			if !(ssa.Is32Bit(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64MULQconst)
			v.AuxInt = ssa.Int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64MULQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	// match: (MULQconst [c] (MULQconst [d] x))
	// cond: ssa.Is32Bit(int64(c)*int64(d))
	// result: (MULQconst [c * d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MULQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(c) * int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64MULQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c * d)
		v.AddArg(x)
		return true
	}
	// match: (MULQconst [ 0] _)
	// result: (MOVQconst [0])
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(0)
		return true
	}
	// match: (MULQconst [ 1] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (MULQconst [c] x)
	// cond: ssa.CanMulStrengthReduce(config, int64(c))
	// result: {ssa.MulStrengthReduce(v, x, int64(c))}
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if !(ssa.CanMulStrengthReduce(config, int64(c))) {
			break
		}
		v.CopyOf(ssa.MulStrengthReduce(v, x, int64(c)))
		return true
	}
	// match: (MULQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [int64(c)*d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(c) * d)
		return true
	}
	// match: (MULQconst [c] (NEGQ x))
	// cond: c != -(1<<31)
	// result: (MULQconst [-c] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64NEGQ {
			break
		}
		x := v_0.Args[0]
		if !(c != -(1 << 31)) {
			break
		}
		v.Reset(ssaop.OpAMD64MULQconst)
		v.AuxInt = ssa.Int32ToAuxInt(-c)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MULSD(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MULSD x l:(MOVSDload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (MULSDload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVSDload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64MULSDload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64MULSDload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (MULSDload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MULSDload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MULSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (MULSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MULSDload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MULSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (MULSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _))
	// result: (MULSD x (MOVQi2f y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVQstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64MULSD)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVQi2f, typ.Float64)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64MULSS(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (MULSS x l:(MOVSSload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (MULSSload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVSSload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64MULSSload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64MULSSload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (MULSSload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (MULSSload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64MULSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (MULSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (MULSSload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64MULSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (MULSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _))
	// result: (MULSS x (MOVLi2f y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVLstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64MULSS)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVLi2f, typ.Float32)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64NEGL(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (NEGL (NEGL x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64NEGL {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	// match: (NEGL s:(SUBL x y))
	// cond: s.Uses == 1
	// result: (SUBL y x)
	for {
		s := v_0
		if s.Op != ssaop.OpAMD64SUBL {
			break
		}
		y := s.Args[1]
		x := s.Args[0]
		if !(s.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBL)
		v.AddArg2(y, x)
		return true
	}
	// match: (NEGL (MOVLconst [c]))
	// result: (MOVLconst [-c])
	for {
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(-c)
		return true
	}
	return false
}
func rewriteValue_OpAMD64NEGQ(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (NEGQ (NEGQ x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64NEGQ {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	// match: (NEGQ s:(SUBQ x y))
	// cond: s.Uses == 1
	// result: (SUBQ y x)
	for {
		s := v_0
		if s.Op != ssaop.OpAMD64SUBQ {
			break
		}
		y := s.Args[1]
		x := s.Args[0]
		if !(s.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQ)
		v.AddArg2(y, x)
		return true
	}
	// match: (NEGQ (MOVQconst [c]))
	// result: (MOVQconst [-c])
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(-c)
		return true
	}
	// match: (NEGQ (ADDQconst [c] (NEGQ x)))
	// cond: c != -(1<<31)
	// result: (ADDQconst [-c] x)
	for {
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		v_0_0 := v_0.Args[0]
		if v_0_0.Op != ssaop.OpAMD64NEGQ {
			break
		}
		x := v_0_0.Args[0]
		if !(c != -(1 << 31)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(-c)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64NOTL(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (NOTL (MOVLconst [c]))
	// result: (MOVLconst [^c])
	for {
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(^c)
		return true
	}
	return false
}
func rewriteValue_OpAMD64NOTQ(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (NOTQ (MOVQconst [c]))
	// result: (MOVQconst [^c])
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(^c)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORBconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ORBconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ORBconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ORBconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ORBconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ORL (SHLL (MOVLconst [1]) y) x)
	// result: (BTSL x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64SHLL {
				continue
			}
			y := v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0_0.AuxInt) != 1 {
				continue
			}
			x := v_1
			v.Reset(ssaop.OpAMD64BTSL)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ORL x (MOVLconst [c]))
	// result: (ORLconst [c] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			v.Reset(ssaop.OpAMD64ORLconst)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ORL x x)
	// result: x
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (ORL x l:(MOVLload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (ORLload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVLload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ORLload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ORLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ORLconst [c] (ORLconst [d] x))
	// result: (ORLconst [c | d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ORLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ORLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c | d)
		v.AddArg(x)
		return true
	}
	// match: (ORLconst [0] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (ORLconst [-1] _)
	// result: (MOVLconst [-1])
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != -1 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(-1)
		return true
	}
	// match: (ORLconst [c] (MOVLconst [d]))
	// result: (MOVLconst [c|d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c | d)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORLconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ORLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ORLconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ORLconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ORLload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ORLload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ORLload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: ( ORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
	// result: ( ORL x (MOVLf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSSstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ORL)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVLf2i, typ.UInt32)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORLmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ORLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ORLmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (ORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ORLmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ORQ (SHLQ (MOVQconst [1]) y) x)
	// result: (BTSQ x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64SHLQ {
				continue
			}
			y := v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_0_0.AuxInt) != 1 {
				continue
			}
			x := v_1
			v.Reset(ssaop.OpAMD64BTSQ)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (ORQ (MOVQconst [c]) x)
	// cond: ssa.IsPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31
	// result: (BTSQconst [int8(ssa.Log64u(uint64(c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_0.AuxInt)
			x := v_1
			if !(ssa.IsPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31) {
				continue
			}
			v.Reset(ssaop.OpAMD64BTSQconst)
			v.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(c))))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ORQ x (MOVQconst [c]))
	// cond: ssa.Is32Bit(c)
	// result: (ORQconst [int32(c)] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1.AuxInt)
			if !(ssa.Is32Bit(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ORQconst)
			v.AuxInt = ssa.Int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ORQ x (MOVLconst [c]))
	// result: (ORQconst [c] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			v.Reset(ssaop.OpAMD64ORQconst)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (ORQ (MOVQconst [c]) (MOVQconst [d]))
	// result: (MOVQconst [c|d])
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_0.AuxInt)
			if v_1.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			d := ssa.AuxIntToInt64(v_1.AuxInt)
			v.Reset(ssaop.OpAMD64MOVQconst)
			v.AuxInt = ssa.Int64ToAuxInt(c | d)
			return true
		}
		break
	}
	// match: (ORQ x x)
	// result: x
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (ORQ x l:(MOVQload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (ORQload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVQload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64ORQload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64ORQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ORQconst [c] (ORQconst [d] x))
	// result: (ORQconst [c | d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ORQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ORQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c | d)
		v.AddArg(x)
		return true
	}
	// match: (ORQconst [0] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (ORQconst [-1] _)
	// result: (MOVQconst [-1])
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != -1 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(-1)
		return true
	}
	// match: (ORQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [int64(c)|d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(c) | d)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORQconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ORQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ORQconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ORQconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (ORQload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ORQload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (ORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ORQload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: ( ORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
	// result: ( ORQ x (MOVQf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSDstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ORQ)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVQf2i, typ.UInt64)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORQmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ORQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (ORQmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (ORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (ORQmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ORWconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ORWconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (ORWconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (ORWconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (ORWconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ROLB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ROLB x (NEGQ y))
	// result: (RORB x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64RORB)
		v.AddArg2(x, y)
		return true
	}
	// match: (ROLB x (NEGL y))
	// result: (RORB x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64RORB)
		v.AddArg2(x, y)
		return true
	}
	// match: (ROLB x (MOVQconst [c]))
	// result: (ROLBconst [int8(c&7) ] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 7))
		v.AddArg(x)
		return true
	}
	// match: (ROLB x (MOVLconst [c]))
	// result: (ROLBconst [int8(c&7) ] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 7))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ROLBconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ROLBconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ROLL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ROLL x (NEGQ y))
	// result: (RORL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64RORL)
		v.AddArg2(x, y)
		return true
	}
	// match: (ROLL x (NEGL y))
	// result: (RORL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64RORL)
		v.AddArg2(x, y)
		return true
	}
	// match: (ROLL x (MOVQconst [c]))
	// result: (ROLLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (ROLL x (MOVLconst [c]))
	// result: (ROLLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ROLLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ROLLconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ROLQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ROLQ x (NEGQ y))
	// result: (RORQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64RORQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (ROLQ x (NEGL y))
	// result: (RORQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64RORQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (ROLQ x (MOVQconst [c]))
	// result: (ROLQconst [int8(c&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v.AddArg(x)
		return true
	}
	// match: (ROLQ x (MOVLconst [c]))
	// result: (ROLQconst [int8(c&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ROLQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ROLQconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ROLW(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (ROLW x (NEGQ y))
	// result: (RORW x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64RORW)
		v.AddArg2(x, y)
		return true
	}
	// match: (ROLW x (NEGL y))
	// result: (RORW x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64RORW)
		v.AddArg2(x, y)
		return true
	}
	// match: (ROLW x (MOVQconst [c]))
	// result: (ROLWconst [int8(c&15)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLWconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 15))
		v.AddArg(x)
		return true
	}
	// match: (ROLW x (MOVLconst [c]))
	// result: (ROLWconst [int8(c&15)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLWconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 15))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64ROLWconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (ROLWconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64RORB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (RORB x (NEGQ y))
	// result: (ROLB x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ROLB)
		v.AddArg2(x, y)
		return true
	}
	// match: (RORB x (NEGL y))
	// result: (ROLB x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ROLB)
		v.AddArg2(x, y)
		return true
	}
	// match: (RORB x (MOVQconst [c]))
	// result: (ROLBconst [int8((-c)&7) ] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8((-c) & 7))
		v.AddArg(x)
		return true
	}
	// match: (RORB x (MOVLconst [c]))
	// result: (ROLBconst [int8((-c)&7) ] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8((-c) & 7))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64RORL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (RORL x (NEGQ y))
	// result: (ROLL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ROLL)
		v.AddArg2(x, y)
		return true
	}
	// match: (RORL x (NEGL y))
	// result: (ROLL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ROLL)
		v.AddArg2(x, y)
		return true
	}
	// match: (RORL x (MOVQconst [c]))
	// result: (ROLLconst [int8((-c)&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8((-c) & 31))
		v.AddArg(x)
		return true
	}
	// match: (RORL x (MOVLconst [c]))
	// result: (ROLLconst [int8((-c)&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8((-c) & 31))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64RORQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (RORQ x (NEGQ y))
	// result: (ROLQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ROLQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (RORQ x (NEGL y))
	// result: (ROLQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ROLQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (RORQ x (MOVQconst [c]))
	// result: (ROLQconst [int8((-c)&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8((-c) & 63))
		v.AddArg(x)
		return true
	}
	// match: (RORQ x (MOVLconst [c]))
	// result: (ROLQconst [int8((-c)&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8((-c) & 63))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64RORW(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (RORW x (NEGQ y))
	// result: (ROLW x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ROLW)
		v.AddArg2(x, y)
		return true
	}
	// match: (RORW x (NEGL y))
	// result: (ROLW x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		y := v_1.Args[0]
		v.Reset(ssaop.OpAMD64ROLW)
		v.AddArg2(x, y)
		return true
	}
	// match: (RORW x (MOVQconst [c]))
	// result: (ROLWconst [int8((-c)&15)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLWconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8((-c) & 15))
		v.AddArg(x)
		return true
	}
	// match: (RORW x (MOVLconst [c]))
	// result: (ROLWconst [int8((-c)&15)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64ROLWconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8((-c) & 15))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SARB x (MOVQconst [c]))
	// result: (SARBconst [int8(min(int64(c)&31,7))] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SARBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(min(int64(c)&31, 7)))
		v.AddArg(x)
		return true
	}
	// match: (SARB x (MOVLconst [c]))
	// result: (SARBconst [int8(min(int64(c)&31,7))] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SARBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(min(int64(c)&31, 7)))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARBconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SARBconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (SARBconst [c] (MOVQconst [d]))
	// result: (MOVQconst [int64(int8(d))>>uint64(c)])
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(int8(d)) >> uint64(c))
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (SARL x (MOVQconst [c]))
	// result: (SARLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SARLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SARL x (MOVLconst [c]))
	// result: (SARLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SARLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SARL x (ADDQconst [c] y))
	// cond: c & 31 == 0
	// result: (SARL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SARL x (NEGQ <t> (ADDQconst [c] y)))
	// cond: c & 31 == 0
	// result: (SARL x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SARL x (ANDQconst [c] y))
	// cond: c & 31 == 31
	// result: (SARL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SARL x (NEGQ <t> (ANDQconst [c] y)))
	// cond: c & 31 == 31
	// result: (SARL x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SARL x (ADDLconst [c] y))
	// cond: c & 31 == 0
	// result: (SARL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SARL x (NEGL <t> (ADDLconst [c] y)))
	// cond: c & 31 == 0
	// result: (SARL x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SARL x (ANDLconst [c] y))
	// cond: c & 31 == 31
	// result: (SARL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SARL x (NEGL <t> (ANDLconst [c] y)))
	// cond: c & 31 == 31
	// result: (SARL x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SARL l:(MOVLload [off] {sym} ptr mem) x)
	// cond: buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (SARXLload [off] {sym} ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARXLload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SARLconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (SARLconst [c] (MOVQconst [d]))
	// result: (MOVQconst [int64(int32(d))>>uint64(c)])
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(int32(d)) >> uint64(c))
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (SARQ x (MOVQconst [c]))
	// result: (SARQconst [int8(c&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SARQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v.AddArg(x)
		return true
	}
	// match: (SARQ x (MOVLconst [c]))
	// result: (SARQconst [int8(c&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SARQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v.AddArg(x)
		return true
	}
	// match: (SARQ x (ADDQconst [c] y))
	// cond: c & 63 == 0
	// result: (SARQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SARQ x (NEGQ <t> (ADDQconst [c] y)))
	// cond: c & 63 == 0
	// result: (SARQ x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SARQ x (ANDQconst [c] y))
	// cond: c & 63 == 63
	// result: (SARQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SARQ x (NEGQ <t> (ANDQconst [c] y)))
	// cond: c & 63 == 63
	// result: (SARQ x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SARQ x (ADDLconst [c] y))
	// cond: c & 63 == 0
	// result: (SARQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SARQ x (NEGL <t> (ADDLconst [c] y)))
	// cond: c & 63 == 0
	// result: (SARQ x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SARQ x (ANDLconst [c] y))
	// cond: c & 63 == 63
	// result: (SARQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SARQ x (NEGL <t> (ANDLconst [c] y)))
	// cond: c & 63 == 63
	// result: (SARQ x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SARQ l:(MOVQload [off] {sym} ptr mem) x)
	// cond: buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (SARXQload [off] {sym} ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARXQload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SARQconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (SARQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [d>>uint64(c)])
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(d >> uint64(c))
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARW(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SARW x (MOVQconst [c]))
	// result: (SARWconst [int8(min(int64(c)&31,15))] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SARWconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(min(int64(c)&31, 15)))
		v.AddArg(x)
		return true
	}
	// match: (SARW x (MOVLconst [c]))
	// result: (SARWconst [int8(min(int64(c)&31,15))] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SARWconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(min(int64(c)&31, 15)))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARWconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SARWconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (SARWconst [c] (MOVQconst [d]))
	// result: (MOVQconst [int64(int16(d))>>uint64(c)])
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(int16(d)) >> uint64(c))
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARXLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SARXLload [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (SARLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SARLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SARXQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SARXQload [off] {sym} ptr (MOVQconst [c]) mem)
	// result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SARQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	// match: (SARXQload [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (SARQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SARQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SBBLcarrymask(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SBBLcarrymask (FlagEQ))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SBBLcarrymask (FlagLT_ULT))
	// result: (MOVLconst [-1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(-1)
		return true
	}
	// match: (SBBLcarrymask (FlagLT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SBBLcarrymask (FlagGT_ULT))
	// result: (MOVLconst [-1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(-1)
		return true
	}
	// match: (SBBLcarrymask (FlagGT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SBBQ(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SBBQ x (MOVQconst [c]) borrow)
	// cond: ssa.Is32Bit(c)
	// result: (SBBQconst x [int32(c)] borrow)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		borrow := v_2
		if !(ssa.Is32Bit(c)) {
			break
		}
		v.Reset(ssaop.OpAMD64SBBQconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(c))
		v.AddArg2(x, borrow)
		return true
	}
	// match: (SBBQ x y (FlagEQ))
	// result: (SUBQborrow x y)
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQborrow)
		v.AddArg2(x, y)
		return true
	}
	// match: (SBBQ x y (InvertFlags f))
	// result: (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
	for {
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		f := v_2.Args[0]
		v.Reset(ssaop.OpAMD64SBBQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBQZX, types.Types[types.TUINT32])
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64SETA, types.Types[types.TUINT8])
		v3.AddArg(f)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg(v1)
		v.AddArg3(x, y, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SBBQcarrymask(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SBBQcarrymask (FlagEQ))
	// result: (MOVQconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(0)
		return true
	}
	// match: (SBBQcarrymask (FlagLT_ULT))
	// result: (MOVQconst [-1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(-1)
		return true
	}
	// match: (SBBQcarrymask (FlagLT_UGT))
	// result: (MOVQconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(0)
		return true
	}
	// match: (SBBQcarrymask (FlagGT_ULT))
	// result: (MOVQconst [-1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(-1)
		return true
	}
	// match: (SBBQcarrymask (FlagGT_UGT))
	// result: (MOVQconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SBBQconst(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SBBQconst x [c] (FlagEQ))
	// result: (SUBQconstborrow x [c])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQconstborrow)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (SBBQconst x [c] (InvertFlags f))
	// result: (SBBQconst x [c] (Select1 <types.TypeFlags> (NEGLflags (MOVBQZX <types.Types[types.TUINT32]> (SETA <types.Types[types.TUINT8]> f)))))
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		f := v_1.Args[0]
		v.Reset(ssaop.OpAMD64SBBQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBQZX, types.Types[types.TUINT32])
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64SETA, types.Types[types.TUINT8])
		v3.AddArg(f)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg(v1)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETA(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SETA (InvertFlags x))
	// result: (SETB x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETB)
		v.AddArg(x)
		return true
	}
	// match: (SETA (FlagEQ))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETA (FlagLT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETA (FlagLT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETA (FlagGT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETA (FlagGT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETAE(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETAE (TESTQ x x))
	// result: (ConstBool [true])
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpConstBool)
		v.AuxInt = ssa.BoolToAuxInt(true)
		return true
	}
	// match: (SETAE (TESTL x x))
	// result: (ConstBool [true])
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpConstBool)
		v.AuxInt = ssa.BoolToAuxInt(true)
		return true
	}
	// match: (SETAE (TESTW x x))
	// result: (ConstBool [true])
	for {
		if v_0.Op != ssaop.OpAMD64TESTW {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpConstBool)
		v.AuxInt = ssa.BoolToAuxInt(true)
		return true
	}
	// match: (SETAE (TESTB x x))
	// result: (ConstBool [true])
	for {
		if v_0.Op != ssaop.OpAMD64TESTB {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpConstBool)
		v.AuxInt = ssa.BoolToAuxInt(true)
		return true
	}
	// match: (SETAE (BTLconst [0] x))
	// result: (XORLconst [1] (ANDLconst <typ.Bool> [1] x))
	for {
		if v_0.Op != ssaop.OpAMD64BTLconst || ssa.AuxIntToInt8(v_0.AuxInt) != 0 {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64XORLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ANDLconst, typ.Bool)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETAE (BTQconst [0] x))
	// result: (XORLconst [1] (ANDLconst <typ.Bool> [1] x))
	for {
		if v_0.Op != ssaop.OpAMD64BTQconst || ssa.AuxIntToInt8(v_0.AuxInt) != 0 {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64XORLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ANDLconst, typ.Bool)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETAE c:(CMPQconst [128] x))
	// cond: c.Uses == 1
	// result: (SETA (CMPQconst [127] x))
	for {
		c := v_0
		if c.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		x := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETA)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETAE c:(CMPLconst [128] x))
	// cond: c.Uses == 1
	// result: (SETA (CMPLconst [127] x))
	for {
		c := v_0
		if c.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		x := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETA)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETAE (InvertFlags x))
	// result: (SETBE x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETBE)
		v.AddArg(x)
		return true
	}
	// match: (SETAE (FlagEQ))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETAE (FlagLT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETAE (FlagLT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETAE (FlagGT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETAE (FlagGT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETAEstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETAEstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETBEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETBEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETAEstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETAEstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETAEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETAEstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETAEstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETAEstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETAEstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETAEstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETAEstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETAstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETAstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETBstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETAstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETAstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETAstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETAstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETAstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETAstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETAstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETAstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETAstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETB(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (SETB (TESTQ x x))
	// result: (ConstBool [false])
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpConstBool)
		v.AuxInt = ssa.BoolToAuxInt(false)
		return true
	}
	// match: (SETB (TESTL x x))
	// result: (ConstBool [false])
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpConstBool)
		v.AuxInt = ssa.BoolToAuxInt(false)
		return true
	}
	// match: (SETB (TESTW x x))
	// result: (ConstBool [false])
	for {
		if v_0.Op != ssaop.OpAMD64TESTW {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpConstBool)
		v.AuxInt = ssa.BoolToAuxInt(false)
		return true
	}
	// match: (SETB (TESTB x x))
	// result: (ConstBool [false])
	for {
		if v_0.Op != ssaop.OpAMD64TESTB {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpConstBool)
		v.AuxInt = ssa.BoolToAuxInt(false)
		return true
	}
	// match: (SETB (BTLconst [0] x))
	// result: (ANDLconst [1] x)
	for {
		if v_0.Op != ssaop.OpAMD64BTLconst || ssa.AuxIntToInt8(v_0.AuxInt) != 0 {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg(x)
		return true
	}
	// match: (SETB (BTQconst [0] x))
	// result: (ANDQconst [1] x)
	for {
		if v_0.Op != ssaop.OpAMD64BTQconst || ssa.AuxIntToInt8(v_0.AuxInt) != 0 {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg(x)
		return true
	}
	// match: (SETB c:(CMPQconst [128] x))
	// cond: c.Uses == 1
	// result: (SETBE (CMPQconst [127] x))
	for {
		c := v_0
		if c.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		x := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETB c:(CMPLconst [128] x))
	// cond: c.Uses == 1
	// result: (SETBE (CMPLconst [127] x))
	for {
		c := v_0
		if c.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		x := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETB (InvertFlags x))
	// result: (SETA x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETA)
		v.AddArg(x)
		return true
	}
	// match: (SETB (FlagEQ))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETB (FlagLT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETB (FlagLT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETB (FlagGT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETB (FlagGT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETBE(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SETBE (InvertFlags x))
	// result: (SETAE x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETAE)
		v.AddArg(x)
		return true
	}
	// match: (SETBE (FlagEQ))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETBE (FlagLT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETBE (FlagLT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETBE (FlagGT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETBE (FlagGT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETBEstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETBEstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETAEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETAEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETBEstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETBEstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETBEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETBEstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETBEstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETBEstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETBEstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETBEstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETBEstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETBstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETBstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETAstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETAstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETBstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETBstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETBstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETBstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETBstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETBstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETBstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETBstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETBstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETEQ(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (SETEQ (TESTL (SHLL (MOVLconst [1]) x) y))
	// result: (SETAE (BTL x y))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			if v_0_0.Op != ssaop.OpAMD64SHLL {
				continue
			}
			x := v_0_0.Args[1]
			v_0_0_0 := v_0_0.Args[0]
			if v_0_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0_0_0.AuxInt) != 1 {
				continue
			}
			y := v_0_1
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTL, types.TypeFlags)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (TESTQ (SHLQ (MOVQconst [1]) x) y))
	// result: (SETAE (BTQ x y))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			if v_0_0.Op != ssaop.OpAMD64SHLQ {
				continue
			}
			x := v_0_0.Args[1]
			v_0_0_0 := v_0_0.Args[0]
			if v_0_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_0_0_0.AuxInt) != 1 {
				continue
			}
			y := v_0_1
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQ, types.TypeFlags)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (TESTLconst [c] x))
	// cond: ssa.IsPowerOfTwo(uint32(c))
	// result: (SETAE (BTLconst [int8(ssa.Log32u(uint32(c)))] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.IsPowerOfTwo(uint32(c))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (TESTQconst [c] x))
	// cond: ssa.IsPowerOfTwo(uint64(c))
	// result: (SETAE (BTQconst [int8(ssa.Log32u(uint32(c)))] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.IsPowerOfTwo(uint64(c))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (TESTQ (MOVQconst [c]) x))
	// cond: ssa.IsPowerOfTwo(uint64(c))
	// result: (SETAE (BTQconst [int8(ssa.Log64u(uint64(c)))] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			if v_0_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_0_0.AuxInt)
			x := v_0_1
			if !(ssa.IsPowerOfTwo(uint64(c))) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(c))))
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (CMPLconst [1] s:(ANDLconst [1] _)))
	// result: (SETNE (CMPLconst [0] s))
	for {
		if v_0.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(v_0.AuxInt) != 1 {
			break
		}
		s := v_0.Args[0]
		if s.Op != ssaop.OpAMD64ANDLconst || ssa.AuxIntToInt32(s.AuxInt) != 1 {
			break
		}
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(s)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (CMPQconst [1] s:(ANDQconst [1] _)))
	// result: (SETNE (CMPQconst [0] s))
	for {
		if v_0.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(v_0.AuxInt) != 1 {
			break
		}
		s := v_0.Args[0]
		if s.Op != ssaop.OpAMD64ANDQconst || ssa.AuxIntToInt32(s.AuxInt) != 1 {
			break
		}
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(s)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2))
	// cond: z1==z2
	// result: (SETAE (BTQconst [63] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(63)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2))
	// cond: z1==z2
	// result: (SETAE (BTQconst [31] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(31)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2))
	// cond: z1==z2
	// result: (SETAE (BTQconst [0] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(0)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2))
	// cond: z1==z2
	// result: (SETAE (BTLconst [0] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(0)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (TESTQ z1:(SHRQconst [63] x) z2))
	// cond: z1==z2
	// result: (SETAE (BTQconst [63] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			x := z1.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(63)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (TESTL z1:(SHRLconst [31] x) z2))
	// cond: z1==z2
	// result: (SETAE (BTLconst [31] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			x := z1.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(31)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (InvertFlags x))
	// result: (SETEQ x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETEQ)
		v.AddArg(x)
		return true
	}
	// match: (SETEQ (FlagEQ))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETEQ (FlagLT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETEQ (FlagLT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETEQ (FlagGT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETEQ (FlagGT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETEQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s))
	// result: (SETEQ (Select1 <types.TypeFlags> blsr))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			s := v_0_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRQ || s != v_0_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64SETEQ)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (TESTL s:(Select0 blsr:(BLSRL _)) s))
	// result: (SETEQ (Select1 <types.TypeFlags> blsr))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			s := v_0_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRL || s != v_0_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64SETEQ)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETEQ (VPTEST x:(VPAND128 j k) y))
	// cond: x == y && x.Uses == 2
	// result: (SETEQ (VPTEST j k))
	for {
		if v_0.Op != ssaop.OpAMD64VPTEST {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		if x.Op != ssaop.OpAMD64VPAND128 {
			break
		}
		k := x.Args[1]
		j := x.Args[0]
		if !(x == y && x.Uses == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(j, k)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (VPTEST x:(VPAND256 j k) y))
	// cond: x == y && x.Uses == 2
	// result: (SETEQ (VPTEST j k))
	for {
		if v_0.Op != ssaop.OpAMD64VPTEST {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		if x.Op != ssaop.OpAMD64VPAND256 {
			break
		}
		k := x.Args[1]
		j := x.Args[0]
		if !(x == y && x.Uses == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(j, k)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (VPTEST x:(VPANDD512 j k) y))
	// cond: x == y && x.Uses == 2
	// result: (SETEQ (VPTEST j k))
	for {
		if v_0.Op != ssaop.OpAMD64VPTEST {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		if x.Op != ssaop.OpAMD64VPANDD512 {
			break
		}
		k := x.Args[1]
		j := x.Args[0]
		if !(x == y && x.Uses == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(j, k)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (VPTEST x:(VPANDQ512 j k) y))
	// cond: x == y && x.Uses == 2
	// result: (SETEQ (VPTEST j k))
	for {
		if v_0.Op != ssaop.OpAMD64VPTEST {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		if x.Op != ssaop.OpAMD64VPANDQ512 {
			break
		}
		k := x.Args[1]
		j := x.Args[0]
		if !(x == y && x.Uses == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(j, k)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (VPTEST x:(VPANDN128 j k) y))
	// cond: x == y && x.Uses == 2
	// result: (SETB (VPTEST k j))
	for {
		if v_0.Op != ssaop.OpAMD64VPTEST {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		if x.Op != ssaop.OpAMD64VPANDN128 {
			break
		}
		k := x.Args[1]
		j := x.Args[0]
		if !(x == y && x.Uses == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(k, j)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (VPTEST x:(VPANDN256 j k) y))
	// cond: x == y && x.Uses == 2
	// result: (SETB (VPTEST k j))
	for {
		if v_0.Op != ssaop.OpAMD64VPTEST {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		if x.Op != ssaop.OpAMD64VPANDN256 {
			break
		}
		k := x.Args[1]
		j := x.Args[0]
		if !(x == y && x.Uses == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(k, j)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (VPTEST x:(VPANDND512 j k) y))
	// cond: x == y && x.Uses == 2
	// result: (SETB (VPTEST k j))
	for {
		if v_0.Op != ssaop.OpAMD64VPTEST {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		if x.Op != ssaop.OpAMD64VPANDND512 {
			break
		}
		k := x.Args[1]
		j := x.Args[0]
		if !(x == y && x.Uses == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(k, j)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ (VPTEST x:(VPANDNQ512 j k) y))
	// cond: x == y && x.Uses == 2
	// result: (SETB (VPTEST k j))
	for {
		if v_0.Op != ssaop.OpAMD64VPTEST {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		if x.Op != ssaop.OpAMD64VPANDNQ512 {
			break
		}
		k := x.Args[1]
		j := x.Args[0]
		if !(x == y && x.Uses == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(k, j)
		v.AddArg(v0)
		return true
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (SETNE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETNE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETEQ flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETEQ)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (SETGE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETGE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (SETLE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETLE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETG flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETG)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETL flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETL)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (SETBE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (SETAE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETB flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETA flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETA)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (SETNE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETNE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETEQ flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETEQ)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (SETGE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETGE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (SETLE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETLE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETG flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETG)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETL flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETL)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (SETBE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (SETAE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETB flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTL x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETA flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETA)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: (SETNE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETNE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETEQ flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETEQ)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: (SETGE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETGE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: (SETLE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETLE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETG flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETG)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETL flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETL)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: (SETBE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: (SETAE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETB flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTW x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: (SETA flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETA)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETEQ flags) s))
	// cond: t.Block == s.Block
	// result: (SETNE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETNE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETNE flags) s))
	// cond: t.Block == s.Block
	// result: (SETEQ flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETEQ)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETL flags) s))
	// cond: t.Block == s.Block
	// result: (SETGE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETGE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETG flags) s))
	// cond: t.Block == s.Block
	// result: (SETLE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETLE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETLE flags) s))
	// cond: t.Block == s.Block
	// result: (SETG flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETG)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETGE flags) s))
	// cond: t.Block == s.Block
	// result: (SETL flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETL)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETA flags) s))
	// cond: t.Block == s.Block
	// result: (SETBE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETB flags) s))
	// cond: t.Block == s.Block
	// result: (SETAE flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAE)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETAE flags) s))
	// cond: t.Block == s.Block
	// result: (SETB flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v.AddArg(flags)
			return true
		}
		break
	}
	// match: (SETEQ t:(TESTB s:(SETBE flags) s))
	// cond: t.Block == s.Block
	// result: (SETA flags)
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			flags := s.Args[0]
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETA)
			v.AddArg(flags)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64SETEQstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETEQstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem)
	// result: (SETAEstore [off] {sym} ptr (BTL x y) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			if v_1_0.Op != ssaop.OpAMD64SHLL {
				continue
			}
			x := v_1_0.Args[1]
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_1_0_0.AuxInt) != 1 {
				continue
			}
			y := v_1_1
			mem := v_2
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTL, types.TypeFlags)
			v0.AddArg2(x, y)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem)
	// result: (SETAEstore [off] {sym} ptr (BTQ x y) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			if v_1_0.Op != ssaop.OpAMD64SHLQ {
				continue
			}
			x := v_1_0.Args[1]
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_1_0_0.AuxInt) != 1 {
				continue
			}
			y := v_1_1
			mem := v_2
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQ, types.TypeFlags)
			v0.AddArg2(x, y)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (TESTLconst [c] x) mem)
	// cond: ssa.IsPowerOfTwo(uint32(c))
	// result: (SETAEstore [off] {sym} ptr (BTLconst [int8(ssa.Log32u(uint32(c)))] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		x := v_1.Args[0]
		mem := v_2
		if !(ssa.IsPowerOfTwo(uint32(c))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
		v0.AddArg(x)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (TESTQconst [c] x) mem)
	// cond: ssa.IsPowerOfTwo(uint64(c))
	// result: (SETAEstore [off] {sym} ptr (BTQconst [int8(ssa.Log32u(uint32(c)))] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		x := v_1.Args[0]
		mem := v_2
		if !(ssa.IsPowerOfTwo(uint64(c))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETAEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
		v0.AddArg(x)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem)
	// cond: ssa.IsPowerOfTwo(uint64(c))
	// result: (SETAEstore [off] {sym} ptr (BTQconst [int8(ssa.Log64u(uint64(c)))] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			if v_1_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1_0.AuxInt)
			x := v_1_1
			mem := v_2
			if !(ssa.IsPowerOfTwo(uint64(c))) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(c))))
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem)
	// result: (SETNEstore [off] {sym} ptr (CMPLconst [0] s) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(v_1.AuxInt) != 1 {
			break
		}
		s := v_1.Args[0]
		if s.Op != ssaop.OpAMD64ANDLconst || ssa.AuxIntToInt32(s.AuxInt) != 1 {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64SETNEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(s)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem)
	// result: (SETNEstore [off] {sym} ptr (CMPQconst [0] s) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(v_1.AuxInt) != 1 {
			break
		}
		s := v_1.Args[0]
		if s.Op != ssaop.OpAMD64ANDQconst || ssa.AuxIntToInt32(s.AuxInt) != 1 {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64SETNEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(s)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem)
	// cond: z1==z2
	// result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(63)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem)
	// cond: z1==z2
	// result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(31)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem)
	// cond: z1==z2
	// result: (SETAEstore [off] {sym} ptr (BTQconst [0] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(0)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem)
	// cond: z1==z2
	// result: (SETAEstore [off] {sym} ptr (BTLconst [0] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(0)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem)
	// cond: z1==z2
	// result: (SETAEstore [off] {sym} ptr (BTQconst [63] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			x := z1.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(63)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem)
	// cond: z1==z2
	// result: (SETAEstore [off] {sym} ptr (BTLconst [31] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			x := z1.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETAEstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(31)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETEQstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETEQstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETEQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETEQstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETEQstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETEQstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETEQstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETEQstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETG(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SETG (InvertFlags x))
	// result: (SETL x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETL)
		v.AddArg(x)
		return true
	}
	// match: (SETG (FlagEQ))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETG (FlagLT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETG (FlagLT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETG (FlagGT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETG (FlagGT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETGE(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (SETGE c:(CMPQconst [128] x))
	// cond: c.Uses == 1
	// result: (SETG (CMPQconst [127] x))
	for {
		c := v_0
		if c.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		x := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETG)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETGE c:(CMPLconst [128] x))
	// cond: c.Uses == 1
	// result: (SETG (CMPLconst [127] x))
	for {
		c := v_0
		if c.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		x := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETG)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETGE (InvertFlags x))
	// result: (SETLE x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETLE)
		v.AddArg(x)
		return true
	}
	// match: (SETGE (FlagEQ))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETGE (FlagLT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETGE (FlagLT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETGE (FlagGT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETGE (FlagGT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETGEstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETGEstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETLEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETLEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETGEstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETGEstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETGEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETGEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETGEstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETGEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETGEstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETGEstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETGEstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETGEstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETGEstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETGstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETGstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETLstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETGstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETGstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETGstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETGstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETGstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETGstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETGstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETGstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETGstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETGstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETGstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETL(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (SETL c:(CMPQconst [128] x))
	// cond: c.Uses == 1
	// result: (SETLE (CMPQconst [127] x))
	for {
		c := v_0
		if c.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		x := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETL c:(CMPLconst [128] x))
	// cond: c.Uses == 1
	// result: (SETLE (CMPLconst [127] x))
	for {
		c := v_0
		if c.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(c.AuxInt) != 128 {
			break
		}
		x := c.Args[0]
		if !(c.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64SETLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(127)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETL (InvertFlags x))
	// result: (SETG x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETG)
		v.AddArg(x)
		return true
	}
	// match: (SETL (FlagEQ))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETL (FlagLT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETL (FlagLT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETL (FlagGT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETL (FlagGT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETLE(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SETLE (InvertFlags x))
	// result: (SETGE x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETGE)
		v.AddArg(x)
		return true
	}
	// match: (SETLE (FlagEQ))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETLE (FlagLT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETLE (FlagLT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETLE (FlagGT_ULT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETLE (FlagGT_UGT))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETLEstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETLEstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETGEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETGEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETLEstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETLEstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETLEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETLEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETLEstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETLEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETLEstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETLEstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETLEstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETLEstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETLEstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETLstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETLstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETGstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETGstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETLstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETLstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETLstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETLstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETLstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETLstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETLstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETLstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETLstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETLstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SETNE(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (SETNE (TESTBconst [1] x))
	// result: (ANDLconst [1] x)
	for {
		if v_0.Op != ssaop.OpAMD64TESTBconst || ssa.AuxIntToInt8(v_0.AuxInt) != 1 {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg(x)
		return true
	}
	// match: (SETNE (TESTWconst [1] x))
	// result: (ANDLconst [1] x)
	for {
		if v_0.Op != ssaop.OpAMD64TESTWconst || ssa.AuxIntToInt16(v_0.AuxInt) != 1 {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg(x)
		return true
	}
	// match: (SETNE (TESTL (SHLL (MOVLconst [1]) x) y))
	// result: (SETB (BTL x y))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			if v_0_0.Op != ssaop.OpAMD64SHLL {
				continue
			}
			x := v_0_0.Args[1]
			v_0_0_0 := v_0_0.Args[0]
			if v_0_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0_0_0.AuxInt) != 1 {
				continue
			}
			y := v_0_1
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTL, types.TypeFlags)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (TESTQ (SHLQ (MOVQconst [1]) x) y))
	// result: (SETB (BTQ x y))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			if v_0_0.Op != ssaop.OpAMD64SHLQ {
				continue
			}
			x := v_0_0.Args[1]
			v_0_0_0 := v_0_0.Args[0]
			if v_0_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_0_0_0.AuxInt) != 1 {
				continue
			}
			y := v_0_1
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQ, types.TypeFlags)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (TESTLconst [c] x))
	// cond: ssa.IsPowerOfTwo(uint32(c))
	// result: (SETB (BTLconst [int8(ssa.Log32u(uint32(c)))] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.IsPowerOfTwo(uint32(c))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETNE (TESTQconst [c] x))
	// cond: ssa.IsPowerOfTwo(uint64(c))
	// result: (SETB (BTQconst [int8(ssa.Log32u(uint32(c)))] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.IsPowerOfTwo(uint64(c))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SETNE (TESTQ (MOVQconst [c]) x))
	// cond: ssa.IsPowerOfTwo(uint64(c))
	// result: (SETB (BTQconst [int8(ssa.Log64u(uint64(c)))] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			if v_0_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_0_0.AuxInt)
			x := v_0_1
			if !(ssa.IsPowerOfTwo(uint64(c))) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(c))))
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (CMPLconst [1] s:(ANDLconst [1] _)))
	// result: (SETEQ (CMPLconst [0] s))
	for {
		if v_0.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(v_0.AuxInt) != 1 {
			break
		}
		s := v_0.Args[0]
		if s.Op != ssaop.OpAMD64ANDLconst || ssa.AuxIntToInt32(s.AuxInt) != 1 {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(s)
		v.AddArg(v0)
		return true
	}
	// match: (SETNE (CMPQconst [1] s:(ANDQconst [1] _)))
	// result: (SETEQ (CMPQconst [0] s))
	for {
		if v_0.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(v_0.AuxInt) != 1 {
			break
		}
		s := v_0.Args[0]
		if s.Op != ssaop.OpAMD64ANDQconst || ssa.AuxIntToInt32(s.AuxInt) != 1 {
			break
		}
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(s)
		v.AddArg(v0)
		return true
	}
	// match: (SETNE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2))
	// cond: z1==z2
	// result: (SETB (BTQconst [63] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(63)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2))
	// cond: z1==z2
	// result: (SETB (BTQconst [31] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(31)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2))
	// cond: z1==z2
	// result: (SETB (BTQconst [0] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(0)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2))
	// cond: z1==z2
	// result: (SETB (BTLconst [0] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(0)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (TESTQ z1:(SHRQconst [63] x) z2))
	// cond: z1==z2
	// result: (SETB (BTQconst [63] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			x := z1.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(63)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (TESTL z1:(SHRLconst [31] x) z2))
	// cond: z1==z2
	// result: (SETB (BTLconst [31] x))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			z1 := v_0_0
			if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			x := z1.Args[0]
			z2 := v_0_1
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETB)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(31)
			v0.AddArg(x)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (InvertFlags x))
	// result: (SETNE x)
	for {
		if v_0.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETNE)
		v.AddArg(x)
		return true
	}
	// match: (SETNE (FlagEQ))
	// result: (MOVLconst [0])
	for {
		if v_0.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SETNE (FlagLT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETNE (FlagLT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETNE (FlagGT_ULT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETNE (FlagGT_UGT))
	// result: (MOVLconst [1])
	for {
		if v_0.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		return true
	}
	// match: (SETNE (TESTQ s:(Select0 blsr:(BLSRQ _)) s))
	// result: (SETNE (Select1 <types.TypeFlags> blsr))
	for {
		if v_0.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			s := v_0_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRQ || s != v_0_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64SETNE)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE (TESTL s:(Select0 blsr:(BLSRL _)) s))
	// result: (SETNE (Select1 <types.TypeFlags> blsr))
	for {
		if v_0.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_0.Args[1]
		v_0_0 := v_0.Args[0]
		v_0_1 := v_0.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
			s := v_0_0
			if s.Op != ssaop.OpSelect0 {
				continue
			}
			blsr := s.Args[0]
			if blsr.Op != ssaop.OpAMD64BLSRL || s != v_0_1 {
				continue
			}
			v.Reset(ssaop.OpAMD64SETNE)
			v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
			v0.AddArg(blsr)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETNE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETL flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETG flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETLE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETGE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETA flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETB flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETAE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETBE flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETGF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTW {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			x := t_0
			if x.Op != ssaop.OpAMD64MOVBQZX {
				continue
			}
			s := x.Args[0]
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			if x != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETEQ flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQ {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETNE flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNE {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETL flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETL {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETG flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETG {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETLE flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETLE {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETGE flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGE {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETA flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETA {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETB flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETB {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETAE flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETAE {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETBE flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETBE {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETEQF flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETEQF {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETNEF flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETNEF {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETGF flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGF {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	// match: (SETNE t:(TESTB s:(SETGEF flags) s))
	// cond: t.Block == s.Block
	// result: s
	for {
		t := v_0
		if t.Op != ssaop.OpAMD64TESTB {
			break
		}
		_ = t.Args[1]
		t_0 := t.Args[0]
		t_1 := t.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
			s := t_0
			if s.Op != ssaop.OpAMD64SETGEF {
				continue
			}
			if s != t_1 || !(t.Block == s.Block) {
				continue
			}
			v.CopyOf(s)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64SETNEstore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SETNEstore [off] {sym} ptr (TESTL (SHLL (MOVLconst [1]) x) y) mem)
	// result: (SETBstore [off] {sym} ptr (BTL x y) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			if v_1_0.Op != ssaop.OpAMD64SHLL {
				continue
			}
			x := v_1_0.Args[1]
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_1_0_0.AuxInt) != 1 {
				continue
			}
			y := v_1_1
			mem := v_2
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTL, types.TypeFlags)
			v0.AddArg2(x, y)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (TESTQ (SHLQ (MOVQconst [1]) x) y) mem)
	// result: (SETBstore [off] {sym} ptr (BTQ x y) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			if v_1_0.Op != ssaop.OpAMD64SHLQ {
				continue
			}
			x := v_1_0.Args[1]
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_1_0_0.AuxInt) != 1 {
				continue
			}
			y := v_1_1
			mem := v_2
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQ, types.TypeFlags)
			v0.AddArg2(x, y)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (TESTLconst [c] x) mem)
	// cond: ssa.IsPowerOfTwo(uint32(c))
	// result: (SETBstore [off] {sym} ptr (BTLconst [int8(ssa.Log32u(uint32(c)))] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		x := v_1.Args[0]
		mem := v_2
		if !(ssa.IsPowerOfTwo(uint32(c))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
		v0.AddArg(x)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (TESTQconst [c] x) mem)
	// cond: ssa.IsPowerOfTwo(uint64(c))
	// result: (SETBstore [off] {sym} ptr (BTQconst [int8(ssa.Log32u(uint32(c)))] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		x := v_1.Args[0]
		mem := v_2
		if !(ssa.IsPowerOfTwo(uint64(c))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
		v0.AddArg(x)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (TESTQ (MOVQconst [c]) x) mem)
	// cond: ssa.IsPowerOfTwo(uint64(c))
	// result: (SETBstore [off] {sym} ptr (BTQconst [int8(ssa.Log64u(uint64(c)))] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			if v_1_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1_0.AuxInt)
			x := v_1_1
			mem := v_2
			if !(ssa.IsPowerOfTwo(uint64(c))) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(c))))
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (CMPLconst [1] s:(ANDLconst [1] _)) mem)
	// result: (SETEQstore [off] {sym} ptr (CMPLconst [0] s) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64CMPLconst || ssa.AuxIntToInt32(v_1.AuxInt) != 1 {
			break
		}
		s := v_1.Args[0]
		if s.Op != ssaop.OpAMD64ANDLconst || ssa.AuxIntToInt32(s.AuxInt) != 1 {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64SETEQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(s)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (CMPQconst [1] s:(ANDQconst [1] _)) mem)
	// result: (SETEQstore [off] {sym} ptr (CMPQconst [0] s) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64CMPQconst || ssa.AuxIntToInt32(v_1.AuxInt) != 1 {
			break
		}
		s := v_1.Args[0]
		if s.Op != ssaop.OpAMD64ANDQconst || ssa.AuxIntToInt32(s.AuxInt) != 1 {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64SETEQstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(s)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2) mem)
	// cond: z1==z2
	// result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(63)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHLLconst [31] (SHRLconst [31] x)) z2) mem)
	// cond: z1==z2
	// result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(31)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2) mem)
	// cond: z1==z2
	// result: (SETBstore [off] {sym} ptr (BTQconst [0] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(0)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2) mem)
	// cond: z1==z2
	// result: (SETBstore [off] {sym} ptr (BTLconst [0] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			z1_0 := z1.Args[0]
			if z1_0.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
				continue
			}
			x := z1_0.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(0)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (TESTQ z1:(SHRQconst [63] x) z2) mem)
	// cond: z1==z2
	// result: (SETBstore [off] {sym} ptr (BTQconst [63] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTQ {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
				continue
			}
			x := z1.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(63)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (TESTL z1:(SHRLconst [31] x) z2) mem)
	// cond: z1==z2
	// result: (SETBstore [off] {sym} ptr (BTLconst [31] x) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64TESTL {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			z1 := v_1_0
			if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
				continue
			}
			x := z1.Args[0]
			z2 := v_1_1
			mem := v_2
			if !(z1 == z2) {
				continue
			}
			v.Reset(ssaop.OpAMD64SETBstore)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(31)
			v0.AddArg(x)
			v.AddArg3(ptr, v0, mem)
			return true
		}
		break
	}
	// match: (SETNEstore [off] {sym} ptr (InvertFlags x) mem)
	// result: (SETNEstore [off] {sym} ptr x mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64InvertFlags {
			break
		}
		x := v_1.Args[0]
		mem := v_2
		v.Reset(ssaop.OpAMD64SETNEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	// match: (SETNEstore [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SETNEstore [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SETNEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETNEstore [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SETNEstore [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SETNEstore)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (FlagEQ) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [0]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagEQ {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (FlagLT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (FlagLT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagLT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (FlagGT_ULT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_ULT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	// match: (SETNEstore [off] {sym} ptr (FlagGT_UGT) mem)
	// result: (MOVBstore [off] {sym} ptr (MOVLconst <typ.UInt8> [1]) mem)
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64FlagGT_UGT {
			break
		}
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLconst, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHLL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (SHLL x (MOVQconst [c]))
	// result: (SHLLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SHLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SHLL x (MOVLconst [c]))
	// result: (SHLLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SHLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SHLL x (ADDQconst [c] y))
	// cond: c & 31 == 0
	// result: (SHLL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHLL x (NEGQ <t> (ADDQconst [c] y)))
	// cond: c & 31 == 0
	// result: (SHLL x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHLL x (ANDQconst [c] y))
	// cond: c & 31 == 31
	// result: (SHLL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHLL x (NEGQ <t> (ANDQconst [c] y)))
	// cond: c & 31 == 31
	// result: (SHLL x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHLL x (ADDLconst [c] y))
	// cond: c & 31 == 0
	// result: (SHLL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHLL x (NEGL <t> (ADDLconst [c] y)))
	// cond: c & 31 == 0
	// result: (SHLL x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHLL x (ANDLconst [c] y))
	// cond: c & 31 == 31
	// result: (SHLL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHLL x (NEGL <t> (ANDLconst [c] y)))
	// cond: c & 31 == 31
	// result: (SHLL x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHLL l:(MOVLload [off] {sym} ptr mem) x)
	// cond: buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (SHLXLload [off] {sym} ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLXLload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHLLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SHLLconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (SHLLconst [1] x)
	// result: (ADDL x x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 1 {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64ADDL)
		v.AddArg2(x, x)
		return true
	}
	// match: (SHLLconst [c] (ADDL x x))
	// cond: c < 31
	// result: (SHLLconst [c+1] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDL {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || !(c < 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(c + 1)
		v.AddArg(x)
		return true
	}
	// match: (SHLLconst [d] (MOVLconst [c]))
	// result: (MOVLconst [c << uint64(d)])
	for {
		d := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c << uint64(d))
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHLQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (SHLQ x (MOVQconst [c]))
	// result: (SHLQconst [int8(c&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SHLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v.AddArg(x)
		return true
	}
	// match: (SHLQ x (MOVLconst [c]))
	// result: (SHLQconst [int8(c&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SHLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v.AddArg(x)
		return true
	}
	// match: (SHLQ x (ADDQconst [c] y))
	// cond: c & 63 == 0
	// result: (SHLQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHLQ x (NEGQ <t> (ADDQconst [c] y)))
	// cond: c & 63 == 0
	// result: (SHLQ x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHLQ x (ANDQconst [c] y))
	// cond: c & 63 == 63
	// result: (SHLQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHLQ x (NEGQ <t> (ANDQconst [c] y)))
	// cond: c & 63 == 63
	// result: (SHLQ x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHLQ x (ADDLconst [c] y))
	// cond: c & 63 == 0
	// result: (SHLQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHLQ x (NEGL <t> (ADDLconst [c] y)))
	// cond: c & 63 == 0
	// result: (SHLQ x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHLQ x (ANDLconst [c] y))
	// cond: c & 63 == 63
	// result: (SHLQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHLQ x (NEGL <t> (ANDLconst [c] y)))
	// cond: c & 63 == 63
	// result: (SHLQ x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHLQ l:(MOVQload [off] {sym} ptr mem) x)
	// cond: buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (SHLXQload [off] {sym} ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLXQload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHLQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SHLQconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (SHLQconst [1] x)
	// result: (ADDQ x x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 1 {
			break
		}
		x := v_0
		v.Reset(ssaop.OpAMD64ADDQ)
		v.AddArg2(x, x)
		return true
	}
	// match: (SHLQconst [c] (ADDQ x x))
	// cond: c < 63
	// result: (SHLQconst [c+1] x)
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64ADDQ {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] || !(c < 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(c + 1)
		v.AddArg(x)
		return true
	}
	// match: (SHLQconst [d] (MOVQconst [c]))
	// result: (MOVQconst [c << uint64(d)])
	for {
		d := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(c << uint64(d))
		return true
	}
	// match: (SHLQconst [d] (MOVLconst [c]))
	// result: (MOVQconst [int64(c) << uint64(d)])
	for {
		d := ssa.AuxIntToInt8(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(c) << uint64(d))
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHLXLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SHLXLload [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (SHLLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SHLLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHLXQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SHLXQload [off] {sym} ptr (MOVQconst [c]) mem)
	// result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SHLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	// match: (SHLXQload [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (SHLQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SHLQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SHRB x (MOVQconst [c]))
	// cond: c&31 < 8
	// result: (SHRBconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(c&31 < 8) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SHRB x (MOVLconst [c]))
	// cond: c&31 < 8
	// result: (SHRBconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		if !(c&31 < 8) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRBconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SHRB _ (MOVQconst [c]))
	// cond: c&31 >= 8
	// result: (MOVLconst [0])
	for {
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(c&31 >= 8) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SHRB _ (MOVLconst [c]))
	// cond: c&31 >= 8
	// result: (MOVLconst [0])
	for {
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		if !(c&31 >= 8) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRBconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SHRBconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (SHRL x (MOVQconst [c]))
	// result: (SHRLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SHRLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SHRL x (MOVLconst [c]))
	// result: (SHRLconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SHRLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SHRL x (ADDQconst [c] y))
	// cond: c & 31 == 0
	// result: (SHRL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHRL x (NEGQ <t> (ADDQconst [c] y)))
	// cond: c & 31 == 0
	// result: (SHRL x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHRL x (ANDQconst [c] y))
	// cond: c & 31 == 31
	// result: (SHRL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHRL x (NEGQ <t> (ANDQconst [c] y)))
	// cond: c & 31 == 31
	// result: (SHRL x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHRL x (ADDLconst [c] y))
	// cond: c & 31 == 0
	// result: (SHRL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHRL x (NEGL <t> (ADDLconst [c] y)))
	// cond: c & 31 == 0
	// result: (SHRL x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHRL x (ANDLconst [c] y))
	// cond: c & 31 == 31
	// result: (SHRL x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHRL x (NEGL <t> (ANDLconst [c] y)))
	// cond: c & 31 == 31
	// result: (SHRL x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&31 == 31) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHRL l:(MOVLload [off] {sym} ptr mem) x)
	// cond: buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (SHRXLload [off] {sym} ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRXLload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SHRLconst [1] (ADDL x x))
	// result: (ANDLconst [0x7fffffff] x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64ADDL {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0x7fffffff)
		v.AddArg(x)
		return true
	}
	// match: (SHRLconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (SHRQ x (MOVQconst [c]))
	// result: (SHRQconst [int8(c&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SHRQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v.AddArg(x)
		return true
	}
	// match: (SHRQ x (MOVLconst [c]))
	// result: (SHRQconst [int8(c&63)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SHRQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v.AddArg(x)
		return true
	}
	// match: (SHRQ x (ADDQconst [c] y))
	// cond: c & 63 == 0
	// result: (SHRQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHRQ x (NEGQ <t> (ADDQconst [c] y)))
	// cond: c & 63 == 0
	// result: (SHRQ x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHRQ x (ANDQconst [c] y))
	// cond: c & 63 == 63
	// result: (SHRQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHRQ x (NEGQ <t> (ANDQconst [c] y)))
	// cond: c & 63 == 63
	// result: (SHRQ x (NEGQ <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGQ {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDQconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHRQ x (ADDLconst [c] y))
	// cond: c & 63 == 0
	// result: (SHRQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHRQ x (NEGL <t> (ADDLconst [c] y)))
	// cond: c & 63 == 0
	// result: (SHRQ x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ADDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHRQ x (ANDLconst [c] y))
	// cond: c & 63 == 63
	// result: (SHRQ x y)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		y := v_1.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (SHRQ x (NEGL <t> (ANDLconst [c] y)))
	// cond: c & 63 == 63
	// result: (SHRQ x (NEGL <t> y))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64NEGL {
			break
		}
		t := v_1.Type
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64ANDLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1_0.AuxInt)
		y := v_1_0.Args[0]
		if !(c&63 == 63) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGL, t)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	// match: (SHRQ l:(MOVQload [off] {sym} ptr mem) x)
	// cond: buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (SHRXQload [off] {sym} ptr x mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		x := v_1
		if !(buildcfg.GOAMD64 >= 3 && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRXQload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, x, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SHRQconst [1] (ADDQ x x))
	// result: (BTRQconst [63] x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64ADDQ {
			break
		}
		x := v_0.Args[1]
		if x != v_0.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64BTRQconst)
		v.AuxInt = ssa.Int8ToAuxInt(63)
		v.AddArg(x)
		return true
	}
	// match: (SHRQconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRW(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SHRW x (MOVQconst [c]))
	// cond: c&31 < 16
	// result: (SHRWconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(c&31 < 16) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRWconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SHRW x (MOVLconst [c]))
	// cond: c&31 < 16
	// result: (SHRWconst [int8(c&31)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		if !(c&31 < 16) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRWconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v.AddArg(x)
		return true
	}
	// match: (SHRW _ (MOVQconst [c]))
	// cond: c&31 >= 16
	// result: (MOVLconst [0])
	for {
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(c&31 >= 16) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SHRW _ (MOVLconst [c]))
	// cond: c&31 >= 16
	// result: (MOVLconst [0])
	for {
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		if !(c&31 >= 16) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRWconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SHRWconst x [0])
	// result: x
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRXLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SHRXLload [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (SHRLconst [int8(c&31)] (MOVLload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SHRLconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 31))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SHRXQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SHRXQload [off] {sym} ptr (MOVQconst [c]) mem)
	// result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SHRQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	// match: (SHRXQload [off] {sym} ptr (MOVLconst [c]) mem)
	// result: (SHRQconst [int8(c&63)] (MOVQload [off] {sym} ptr mem))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		ptr := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		mem := v_2
		v.Reset(ssaop.OpAMD64SHRQconst)
		v.AuxInt = ssa.Int8ToAuxInt(int8(c & 63))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (SUBL x (MOVLconst [c]))
	// result: (SUBLconst x [c])
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64SUBLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (SUBL (MOVLconst [c]) x)
	// result: (NEGL (SUBLconst <v.Type> x [c]))
	for {
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		c := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_1
		v.Reset(ssaop.OpAMD64NEGL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SUBLconst, v.Type)
		v0.AuxInt = ssa.Int32ToAuxInt(c)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SUBL x x)
	// result: (MOVLconst [0])
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SUBL x l:(MOVLload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (SUBLload x [off] {sym} ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBLload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SUBLconst [0] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (SUBLconst [c] x)
	// result: (ADDLconst [-c] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64ADDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(-c)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpAMD64SUBLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SUBLload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SUBLload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (SUBLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SUBLload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (SUBLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
	// result: (SUBL x (MOVLf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSSstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64SUBL)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVLf2i, typ.UInt32)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBLmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SUBLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SUBLmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SUBLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SUBLmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SUBQ x (MOVBQZX (SETB flags)))
	// result: (Select0 (SBBQconst [0] x flags))
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVBQZX {
			break
		}
		v_1_0 := v_1.Args[0]
		if v_1_0.Op != ssaop.OpAMD64SETB {
			break
		}
		flags := v_1_0.Args[0]
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQconst, types.NewTuple(typ.UInt64, types.TypeFlags))
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg2(x, flags)
		v.AddArg(v0)
		return true
	}
	// match: (SUBQ x (MOVQconst [c]))
	// cond: ssa.Is32Bit(c)
	// result: (SUBQconst x [int32(c)])
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(ssa.Is32Bit(c)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(c))
		v.AddArg(x)
		return true
	}
	// match: (SUBQ (MOVQconst [c]) x)
	// cond: ssa.Is32Bit(c)
	// result: (NEGQ (SUBQconst <v.Type> x [int32(c)]))
	for {
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_0.AuxInt)
		x := v_1
		if !(ssa.Is32Bit(c)) {
			break
		}
		v.Reset(ssaop.OpAMD64NEGQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SUBQconst, v.Type)
		v0.AuxInt = ssa.Int32ToAuxInt(int32(c))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	// match: (SUBQ x x)
	// result: (MOVLconst [0])
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (SUBQ x l:(MOVQload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (SUBQload x [off] {sym} ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBQborrow(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SUBQborrow x (MOVQconst [c]))
	// cond: ssa.Is32Bit(c)
	// result: (SUBQconstborrow x [int32(c)])
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		if !(ssa.Is32Bit(c)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQconstborrow)
		v.AuxInt = ssa.Int32ToAuxInt(int32(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (SUBQconst [0] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (SUBQconst [c] x)
	// cond: c != -(1<<31)
	// result: (ADDQconst [-c] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		x := v_0
		if !(c != -(1 << 31)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(-c)
		v.AddArg(x)
		return true
	}
	// match: (SUBQconst (MOVQconst [d]) [c])
	// result: (MOVQconst [d-int64(c)])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(d - int64(c))
		return true
	}
	// match: (SUBQconst (SUBQconst x [d]) [c])
	// cond: ssa.Is32Bit(int64(-c)-int64(d))
	// result: (ADDQconst [-c-d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64SUBQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		if !(ssa.Is32Bit(int64(-c) - int64(d))) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(-c - d)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SUBQload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SUBQload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (SUBQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SUBQload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (SUBQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
	// result: (SUBQ x (MOVQf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSDstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQ)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVQf2i, typ.UInt64)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBQmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SUBQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SUBQmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (SUBQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SUBQmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBSD(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SUBSD x l:(MOVSDload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (SUBSDload x [off] {sym} ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVSDload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	// match: (SUBSD (MULSD x y) z)
	// cond: buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)
	// result: (VFMSUB231SD z x y)
	for {
		if v_0.Op != ssaop.OpAMD64MULSD {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		z := v_1
		if !(buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUB231SD)
		v.AddArg3(z, x, y)
		return true
	}
	// match: (SUBSD x (MULSD y z))
	// cond: buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)
	// result: (VFNMADD231SD x y z)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MULSD {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			y := v_1_0
			z := v_1_1
			if !(buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VFNMADD231SD)
			v.AddArg3(x, y, z)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64SUBSDload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SUBSDload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SUBSDload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (SUBSDload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SUBSDload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBSDload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (SUBSDload x [off] {sym} ptr (MOVQstore [off] {sym} ptr y _))
	// result: (SUBSD x (MOVQi2f y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVQstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64SUBSD)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVQi2f, typ.Float64)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64SUBSS(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SUBSS x l:(MOVSSload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (SUBSSload x [off] {sym} ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64MOVSSload {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	// match: (SUBSS (MULSS x y) z)
	// cond: buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)
	// result: (VFMSUB231SS z x y)
	for {
		if v_0.Op != ssaop.OpAMD64MULSS {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		z := v_1
		if !(buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUB231SS)
		v.AddArg3(z, x, y)
		return true
	}
	// match: (SUBSS x (MULSS y z))
	// cond: buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)
	// result: (VFNMADD231SS x y z)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MULSS {
			break
		}
		_ = v_1.Args[1]
		v_1_0 := v_1.Args[0]
		v_1_1 := v_1.Args[1]
		for _i0 := 0; _i0 <= 1; _i0, v_1_0, v_1_1 = _i0+1, v_1_1, v_1_0 {
			y := v_1_0
			z := v_1_1
			if !(buildcfg.GOAMD64 >= 3 && z.Block.Func.UseFMA(v)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VFNMADD231SS)
			v.AddArg3(x, y, z)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64SUBSSload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SUBSSload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (SUBSSload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (SUBSSload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (SUBSSload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64SUBSSload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (SUBSSload x [off] {sym} ptr (MOVLstore [off] {sym} ptr y _))
	// result: (SUBSS x (MOVLi2f y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVLstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64SUBSS)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVLi2f, typ.Float32)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64TESTB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (TESTB (MOVLconst [c]) x)
	// result: (TESTBconst [int8(c)] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_1
			v.Reset(ssaop.OpAMD64TESTBconst)
			v.AuxInt = ssa.Int8ToAuxInt(int8(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (TESTB l:(MOVBload {sym} [off] ptr mem) l2)
	// cond: l == l2 && l.Uses == 2 && ssa.Clobber(l)
	// result: @l.Block (CMPBconstload {sym} [ssa.MakeValAndOff(0, off)] ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			l := v_0
			if l.Op != ssaop.OpAMD64MOVBload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			l2 := v_1
			if !(l == l2 && l.Uses == 2 && ssa.Clobber(l)) {
				continue
			}
			b = l.Block
			v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPBconstload, types.TypeFlags)
			v.CopyOf(v0)
			v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, off))
			v0.Aux = ssa.SymToAux(sym)
			v0.AddArg2(ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64TESTBconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TESTBconst [-1] x)
	// cond: x.Op != ssaop.OpAMD64MOVLconst
	// result: (TESTB x x)
	for {
		if ssa.AuxIntToInt8(v.AuxInt) != -1 {
			break
		}
		x := v_0
		if !(x.Op != ssaop.OpAMD64MOVLconst) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTB)
		v.AddArg2(x, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64TESTL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (TESTL (MOVLconst [c]) x)
	// result: (TESTLconst [c] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_1
			v.Reset(ssaop.OpAMD64TESTLconst)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (TESTL l:(MOVLload {sym} [off] ptr mem) l2)
	// cond: l == l2 && l.Uses == 2 && ssa.Clobber(l)
	// result: @l.Block (CMPLconstload {sym} [ssa.MakeValAndOff(0, off)] ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			l := v_0
			if l.Op != ssaop.OpAMD64MOVLload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			l2 := v_1
			if !(l == l2 && l.Uses == 2 && ssa.Clobber(l)) {
				continue
			}
			b = l.Block
			v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPLconstload, types.TypeFlags)
			v.CopyOf(v0)
			v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, off))
			v0.Aux = ssa.SymToAux(sym)
			v0.AddArg2(ptr, mem)
			return true
		}
		break
	}
	// match: (TESTL a:(ANDLload [off] {sym} x ptr mem) a)
	// cond: a.Uses == 2 && a.Block == v.Block && ssa.Clobber(a)
	// result: (TESTL (MOVLload <a.Type> [off] {sym} ptr mem) x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			a := v_0
			if a.Op != ssaop.OpAMD64ANDLload {
				continue
			}
			off := ssa.AuxIntToInt32(a.AuxInt)
			sym := ssa.AuxToSym(a.Aux)
			mem := a.Args[2]
			x := a.Args[0]
			ptr := a.Args[1]
			if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && ssa.Clobber(a)) {
				continue
			}
			v.Reset(ssaop.OpAMD64TESTL)
			v0 := b.NewValue0(a.Pos, ssaop.OpAMD64MOVLload, a.Type)
			v0.AuxInt = ssa.Int32ToAuxInt(off)
			v0.Aux = ssa.SymToAux(sym)
			v0.AddArg2(ptr, mem)
			v.AddArg2(v0, x)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64TESTLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TESTLconst [c] (MOVLconst [c]))
	// cond: c == 0
	// result: (FlagEQ)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0.AuxInt) != c || !(c == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagEQ)
		return true
	}
	// match: (TESTLconst [c] (MOVLconst [c]))
	// cond: c < 0
	// result: (FlagLT_UGT)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0.AuxInt) != c || !(c < 0) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_UGT)
		return true
	}
	// match: (TESTLconst [c] (MOVLconst [c]))
	// cond: c > 0
	// result: (FlagGT_UGT)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0.AuxInt) != c || !(c > 0) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_UGT)
		return true
	}
	// match: (TESTLconst [-1] x)
	// cond: x.Op != ssaop.OpAMD64MOVLconst
	// result: (TESTL x x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != -1 {
			break
		}
		x := v_0
		if !(x.Op != ssaop.OpAMD64MOVLconst) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTL)
		v.AddArg2(x, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64TESTQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (TESTQ (MOVQconst [c]) x)
	// cond: ssa.Is32Bit(c)
	// result: (TESTQconst [int32(c)] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_0.AuxInt)
			x := v_1
			if !(ssa.Is32Bit(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64TESTQconst)
			v.AuxInt = ssa.Int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (TESTQ l:(MOVQload {sym} [off] ptr mem) l2)
	// cond: l == l2 && l.Uses == 2 && ssa.Clobber(l)
	// result: @l.Block (CMPQconstload {sym} [ssa.MakeValAndOff(0, off)] ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			l := v_0
			if l.Op != ssaop.OpAMD64MOVQload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			l2 := v_1
			if !(l == l2 && l.Uses == 2 && ssa.Clobber(l)) {
				continue
			}
			b = l.Block
			v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPQconstload, types.TypeFlags)
			v.CopyOf(v0)
			v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, off))
			v0.Aux = ssa.SymToAux(sym)
			v0.AddArg2(ptr, mem)
			return true
		}
		break
	}
	// match: (TESTQ a:(ANDQload [off] {sym} x ptr mem) a)
	// cond: a.Uses == 2 && a.Block == v.Block && ssa.Clobber(a)
	// result: (TESTQ (MOVQload <a.Type> [off] {sym} ptr mem) x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			a := v_0
			if a.Op != ssaop.OpAMD64ANDQload {
				continue
			}
			off := ssa.AuxIntToInt32(a.AuxInt)
			sym := ssa.AuxToSym(a.Aux)
			mem := a.Args[2]
			x := a.Args[0]
			ptr := a.Args[1]
			if a != v_1 || !(a.Uses == 2 && a.Block == v.Block && ssa.Clobber(a)) {
				continue
			}
			v.Reset(ssaop.OpAMD64TESTQ)
			v0 := b.NewValue0(a.Pos, ssaop.OpAMD64MOVQload, a.Type)
			v0.AuxInt = ssa.Int32ToAuxInt(off)
			v0.Aux = ssa.SymToAux(sym)
			v0.AddArg2(ptr, mem)
			v.AddArg2(v0, x)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64TESTQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TESTQconst [c] (MOVQconst [d]))
	// cond: int64(c) == d && c == 0
	// result: (FlagEQ)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		if !(int64(c) == d && c == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagEQ)
		return true
	}
	// match: (TESTQconst [c] (MOVQconst [d]))
	// cond: int64(c) == d && c < 0
	// result: (FlagLT_UGT)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		if !(int64(c) == d && c < 0) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagLT_UGT)
		return true
	}
	// match: (TESTQconst [c] (MOVQconst [d]))
	// cond: int64(c) == d && c > 0
	// result: (FlagGT_UGT)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		if !(int64(c) == d && c > 0) {
			break
		}
		v.Reset(ssaop.OpAMD64FlagGT_UGT)
		return true
	}
	// match: (TESTQconst [-1] x)
	// cond: x.Op != ssaop.OpAMD64MOVQconst
	// result: (TESTQ x x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != -1 {
			break
		}
		x := v_0
		if !(x.Op != ssaop.OpAMD64MOVQconst) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTQ)
		v.AddArg2(x, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64TESTW(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (TESTW (MOVLconst [c]) x)
	// result: (TESTWconst [int16(c)] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_1
			v.Reset(ssaop.OpAMD64TESTWconst)
			v.AuxInt = ssa.Int16ToAuxInt(int16(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (TESTW l:(MOVWload {sym} [off] ptr mem) l2)
	// cond: l == l2 && l.Uses == 2 && ssa.Clobber(l)
	// result: @l.Block (CMPWconstload {sym} [ssa.MakeValAndOff(0, off)] ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			l := v_0
			if l.Op != ssaop.OpAMD64MOVWload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			l2 := v_1
			if !(l == l2 && l.Uses == 2 && ssa.Clobber(l)) {
				continue
			}
			b = l.Block
			v0 := b.NewValue0(l.Pos, ssaop.OpAMD64CMPWconstload, types.TypeFlags)
			v.CopyOf(v0)
			v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, off))
			v0.Aux = ssa.SymToAux(sym)
			v0.AddArg2(ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64TESTWconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TESTWconst [-1] x)
	// cond: x.Op != ssaop.OpAMD64MOVLconst
	// result: (TESTW x x)
	for {
		if ssa.AuxIntToInt16(v.AuxInt) != -1 {
			break
		}
		x := v_0
		if !(x.Op != ssaop.OpAMD64MOVLconst) {
			break
		}
		v.Reset(ssaop.OpAMD64TESTW)
		v.AddArg2(x, x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VADDPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPS128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPS128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPS256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPS256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPS512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPS512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPSMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPSMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPSMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPSMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPSMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDPSMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VADDPSMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VADDSUBPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDSUBPD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VADDSUBPD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VADDSUBPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDSUBPD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VADDSUBPD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VADDSUBPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDSUBPS128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VADDSUBPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VADDSUBPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VADDSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VADDSUBPS256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VADDSUBPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESDEC128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VAESDEC128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESDEC128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESDEC128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESDEC256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VAESDEC256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESDEC256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESDEC256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESDECLAST128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VAESDECLAST128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESDECLAST128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESDECLAST128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESDECLAST256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VAESDECLAST256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESDECLAST256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESDECLAST256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESENC128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VAESENC128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESENC128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESENC128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESENC256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VAESENC256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESENC256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESENC256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESENCLAST128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VAESENCLAST128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESENCLAST128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESENCLAST128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESENCLAST256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VAESENCLAST256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESENCLAST256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESENCLAST256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESIMC128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VAESIMC128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESIMC128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESIMC128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VAESKEYGENASSIST128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VAESKEYGENASSIST128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VAESKEYGENASSIST128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VAESKEYGENASSIST128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VBROADCASTSD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VBROADCASTSD512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VBROADCASTSDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VBROADCASTSDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VBROADCASTSS128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSS128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VBROADCASTSS256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx) && ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSS512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VBROADCASTSS512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSS512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VBROADCASTSSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSSMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VBROADCASTSSMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VBROADCASTSSMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VBROADCASTSSMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VBROADCASTSSMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPS128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPS128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPS128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPS256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPS256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPS256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPS512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPS512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPS512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPSMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPSMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPSMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPSMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPSMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPSMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPSMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCMPPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCMPPSMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCMPPSMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCMPPSMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PS128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PS512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PS512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PSMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTDQ2PSMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTDQ2PSMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPD2PS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTPD2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPD2PS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPD2PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPD2PSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTPD2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPD2PSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPD2PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPD2PSX128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTPD2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPD2PSX128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPD2PSX128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPD2PSXMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTPD2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPD2PSXMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPD2PSXMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPD2PSY128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTPD2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPD2PSY128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPD2PSY128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPD2PSYMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTPD2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPD2PSYMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPD2PSYMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPS2PD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTPS2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPS2PD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPS2PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPS2PD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTPS2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPS2PD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPS2PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPS2PDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTPS2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPS2PDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPS2PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTPS2PDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTPS2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTPS2PDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPS2PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PSX128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PSX128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PSX128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PSXMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PSXMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PSXMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PSY128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PSY128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PSY128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTQQ2PSYMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTQQ2PSYMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PSYMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2DQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2DQ256 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2DQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2DQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2DQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2DQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2DQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2DQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2DQX128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2DQX128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2DQX128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2DQX128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2DQXMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2DQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2DQXMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2DQXMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2DQY128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2DQY128 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2DQY128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2DQY128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2DQYMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2DQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2DQYMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2DQYMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2QQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2QQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2QQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2QQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2QQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2QQ256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2QQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2QQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2QQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2QQ512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2QQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2QQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2QQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2QQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2QQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2QQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2QQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2QQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2QQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2QQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2QQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UDQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2UDQ256 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UDQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UDQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2UDQMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UDQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UDQX128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2UDQX128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UDQX128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQX128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UDQXMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2UDQXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UDQXMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQXMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UDQY128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2UDQY128 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UDQY128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQY128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UDQYMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2UDQYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UDQYMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQYMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UQQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2UQQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UQQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UQQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2UQQ256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UQQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UQQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPD2UQQ512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UQQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UQQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2UQQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UQQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UQQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2UQQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UQQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPD2UQQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPD2UQQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPD2UQQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2DQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2DQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2DQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2DQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2DQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2DQ256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2DQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2DQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2DQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2DQ512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2DQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2DQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2DQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2DQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2DQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2DQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2DQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2DQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2DQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2DQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2DQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2QQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2QQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2QQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2QQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2QQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2QQ512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2QQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2QQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2QQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2QQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2QQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2QQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2QQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2QQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2QQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2QQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UDQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2UDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UDQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UDQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2UDQ256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UDQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UDQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2UDQ512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UDQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UDQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2UDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UDQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UDQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2UDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UDQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UDQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2UDQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UDQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UQQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2UQQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UQQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UQQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UQQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTTPS2UQQ512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UQQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UQQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UQQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2UQQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UQQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UQQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTTPS2UQQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTTPS2UQQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTTPS2UQQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UQQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PD512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PS128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PS128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PS256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PS512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PS512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PS512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PSMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUDQ2PSMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUDQ2PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUDQ2PSMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PS256 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PSMasked256 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PSX128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PSX128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PSX128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSX128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PSXMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PSXMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PSXMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSXMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PSY128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PSY128 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PSY128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSY128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VCVTUQQ2PSYMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VCVTUQQ2PSYMasked128 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VCVTUQQ2PSYMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSYMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPS128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPS256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPS512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPSMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPSMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPSMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VDIVPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VDIVPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VDIVPSMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VEXPANDPDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VEXPANDPDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VEXPANDPDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VEXPANDPDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VEXPANDPDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VEXPANDPDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VEXPANDPDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VEXPANDPDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VEXPANDPSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VEXPANDPSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VEXPANDPSMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VEXPANDPSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VEXPANDPSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VEXPANDPSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VEXPANDPSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VEXPANDPSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PD128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PD128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PD256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PD256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PD512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PD512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PDMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PDMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PDMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PDMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PDMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PDMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PS128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PS128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PS256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PS256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PS512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PS512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PSMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PSMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PSMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PSMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADD213PSMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADD213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADD213PSMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADD213PSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PD128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PD128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PD256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PD256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PD512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PD512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PDMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PDMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PDMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PDMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PDMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PDMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PS128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PS128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PS256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PS256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PS512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PS512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PSMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PSMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PSMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PSMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMADDSUB213PSMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMADDSUB213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMADDSUB213PSMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMADDSUB213PSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PD128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PD128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PD256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PD256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PD512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PD512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PDMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PDMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PDMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PDMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PDMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PDMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PS128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PS128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PS256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PS256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PS512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PS512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PSMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PSMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PSMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PSMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VFMSUBADD213PSMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VFMSUBADD213PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VFMSUBADD213PSMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VFMSUBADD213PSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEINVQB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEINVQB128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEINVQB128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQB128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEINVQB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEINVQB256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEINVQB256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQB256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEINVQB512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEINVQB512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEINVQB512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQB512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEINVQBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEINVQBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEINVQBMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQBMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEINVQBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEINVQBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEINVQBMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQBMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEINVQBMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEINVQBMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEINVQBMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQBMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEQB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEQB128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEQB128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQB128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEQB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEQB256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEQB256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQB256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEQB512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEQB512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEQB512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQB512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEQBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEQBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEQBMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQBMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEQBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEQBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEQBMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQBMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8AFFINEQBMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8AFFINEQBMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8AFFINEQBMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQBMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8MULB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8MULB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8MULB128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8MULB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8MULB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8MULB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8MULB256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8MULB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8MULBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8MULBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8MULBMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8MULBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VGF2P8MULBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VGF2P8MULBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VGF2P8MULBMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8MULBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VHADDPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VHADDPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VHADDPD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VHADDPD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VHADDPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VHADDPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VHADDPD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VHADDPD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VHADDPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VHADDPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VHADDPS128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VHADDPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VHADDPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VHADDPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VHADDPS256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VHADDPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VHSUBPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VHSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VHSUBPD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VHSUBPD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VHSUBPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VHSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VHSUBPD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VHSUBPD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VHSUBPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VHSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VHSUBPS128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VHSUBPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VHSUBPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VHSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VHSUBPS256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VHSUBPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VINSERTF128256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VINSERTF128256 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VINSERTF128256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VINSERTF128256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VINSERTF64X4512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VINSERTF64X4512 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VINSERTF64X4512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VINSERTF64X4512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VINSERTI128256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VINSERTI128256 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VINSERTI128256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VINSERTI128256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VINSERTI64X4512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VINSERTI64X4512 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VINSERTI64X4512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VINSERTI64X4512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMAXPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPS128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPS128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPS256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPS256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPS512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPS512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPSMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPSMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPSMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPSMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPSMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMAXPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMAXPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMAXPSMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMAXPSMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPS128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPS128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPS256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPS256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPS512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPS512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPSMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPSMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPSMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPSMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPSMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMINPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMINPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMINPSMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMINPSMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMOVD(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VMOVD x:(MOVLload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (VMOVDload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVLload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64VMOVDload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU16Masked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU16Masked128 (VPABSW128 x) mask)
	// result: (VPABSWMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSW128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSWMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPADDW128 x y) mask)
	// result: (VPADDWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPADDSW128 x y) mask)
	// result: (VPADDSWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDSW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDSWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPADDUSW128 x y) mask)
	// result: (VPADDUSWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDUSW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDUSWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPAVGW128 x y) mask)
	// result: (VPAVGWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPAVGW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPAVGWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPERMI2W128 x y z) mask)
	// result: (VPERMI2WMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2W128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2WMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMADDWD128 x y) mask)
	// result: (VPMADDWDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMADDWD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMADDWDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMADDUBSW128 x y) mask)
	// result: (VPMADDUBSWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMADDUBSW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMADDUBSWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMOVSXWQ128 x) mask)
	// result: (VPMOVSXWQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXWQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMOVZXWQ128 x) mask)
	// result: (VPMOVZXWQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXWQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMOVSXWD128 x) mask)
	// result: (VPMOVSXWDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXWD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMOVZXWD128 x) mask)
	// result: (VPMOVZXWDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXWD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMAXSW128 x y) mask)
	// result: (VPMAXSWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMAXUW128 x y) mask)
	// result: (VPMAXUWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMINSW128 x y) mask)
	// result: (VPMINSWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMINUW128 x y) mask)
	// result: (VPMINUWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMULHW128 x y) mask)
	// result: (VPMULHWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULHW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULHWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMULHUW128 x y) mask)
	// result: (VPMULHUWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULHUW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULHUWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMULLW128 x y) mask)
	// result: (VPMULLWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPOPCNTW128 x) mask)
	// result: (VPOPCNTWMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTW128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTWMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPERMW128 x y) mask)
	// result: (VPERMWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMOVSWB128_128 x) mask)
	// result: (VPMOVSWBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSWB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSWBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMOVUSWB128_128 x) mask)
	// result: (VPMOVUSWBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSWB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSWBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSHLDW128 [a] x y) mask)
	// result: (VPSHLDWMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDW128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDWMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSLLW128 x y) mask)
	// result: (VPSLLWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSHRDW128 [a] x y) mask)
	// result: (VPSHRDWMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDW128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDWMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSRAW128 x y) mask)
	// result: (VPSRAWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSRLW128 x y) mask)
	// result: (VPSRLWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSHLDVW128 x y z) mask)
	// result: (VPSHLDVWMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVW128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVWMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSLLVW128 x y) mask)
	// result: (VPSLLVWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSHRDVW128 x y z) mask)
	// result: (VPSHRDVWMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVW128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVWMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSRAVW128 x y) mask)
	// result: (VPSRAVWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSRLVW128 x y) mask)
	// result: (VPSRLVWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSUBW128 x y) mask)
	// result: (VPSUBWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSUBSW128 x y) mask)
	// result: (VPSUBSWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBSW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBSWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSUBUSW128 x y) mask)
	// result: (VPSUBUSWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBUSW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBUSWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPMOVWB128_128 x) mask)
	// result: (VPMOVWBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVWB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVWBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSHUFHW128 [a] x) mask)
	// result: (VPSHUFHWMasked128 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFHW128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFHWMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSHUFLW128 [a] x) mask)
	// result: (VPSHUFLWMasked128 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFLW128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFLWMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSLLW128const [a] x) mask)
	// result: (VPSLLWMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLW128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLWMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSRAW128const [a] x) mask)
	// result: (VPSRAWMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAW128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAWMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked128 (VPSRLW128const [a] x) mask)
	// result: (VPSRLWMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLW128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLWMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU16Masked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU16Masked256 (VPABSW256 x) mask)
	// result: (VPABSWMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSW256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSWMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPADDW256 x y) mask)
	// result: (VPADDWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPADDSW256 x y) mask)
	// result: (VPADDSWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDSW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDSWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPADDUSW256 x y) mask)
	// result: (VPADDUSWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDUSW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDUSWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPAVGW256 x y) mask)
	// result: (VPAVGWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPAVGW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPAVGWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPERMI2W256 x y z) mask)
	// result: (VPERMI2WMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2W256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2WMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMADDWD256 x y) mask)
	// result: (VPMADDWDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMADDWD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMADDWDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMADDUBSW256 x y) mask)
	// result: (VPMADDUBSWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMADDUBSW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMADDUBSWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVSXWQ256 x) mask)
	// result: (VPMOVSXWQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXWQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVZXWQ256 x) mask)
	// result: (VPMOVZXWQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXWQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVSXWD256 x) mask)
	// result: (VPMOVSXWDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXWD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVZXWD256 x) mask)
	// result: (VPMOVZXWDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXWD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMAXSW256 x y) mask)
	// result: (VPMAXSWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMAXUW256 x y) mask)
	// result: (VPMAXUWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMINSW256 x y) mask)
	// result: (VPMINSWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMINUW256 x y) mask)
	// result: (VPMINUWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMULHW256 x y) mask)
	// result: (VPMULHWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULHW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULHWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMULHUW256 x y) mask)
	// result: (VPMULHUWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULHUW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULHUWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMULLW256 x y) mask)
	// result: (VPMULLWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPOPCNTW256 x) mask)
	// result: (VPOPCNTWMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTW256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTWMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPERMW256 x y) mask)
	// result: (VPERMWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVSWB128_256 x) mask)
	// result: (VPMOVSWBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSWB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSWBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVSWB256 x) mask)
	// result: (VPMOVSWBMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSWB256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSWBMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVUSWB128_256 x) mask)
	// result: (VPMOVUSWBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSWB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSWBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVUSWB256 x) mask)
	// result: (VPMOVUSWBMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSWB256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSWBMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSHLDW256 [a] x y) mask)
	// result: (VPSHLDWMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDW256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDWMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSLLW256 x y) mask)
	// result: (VPSLLWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSHRDW256 [a] x y) mask)
	// result: (VPSHRDWMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDW256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDWMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSRAW256 x y) mask)
	// result: (VPSRAWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSRLW256 x y) mask)
	// result: (VPSRLWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSHLDVW256 x y z) mask)
	// result: (VPSHLDVWMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVW256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVWMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSLLVW256 x y) mask)
	// result: (VPSLLVWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSHRDVW256 x y z) mask)
	// result: (VPSHRDVWMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVW256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVWMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSRAVW256 x y) mask)
	// result: (VPSRAVWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSRLVW256 x y) mask)
	// result: (VPSRLVWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSUBW256 x y) mask)
	// result: (VPSUBWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSUBSW256 x y) mask)
	// result: (VPSUBSWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBSW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBSWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSUBUSW256 x y) mask)
	// result: (VPSUBUSWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBUSW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBUSWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVWB128_256 x) mask)
	// result: (VPMOVWBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVWB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVWBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPMOVWB256 x) mask)
	// result: (VPMOVWBMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVWB256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVWBMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSHUFHW256 [a] x) mask)
	// result: (VPSHUFHWMasked256 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFHW256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFHWMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSHUFLW256 [a] x) mask)
	// result: (VPSHUFLWMasked256 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFLW256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFLWMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSLLW256const [a] x) mask)
	// result: (VPSLLWMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLW256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLWMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSRAW256const [a] x) mask)
	// result: (VPSRAWMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAW256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAWMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked256 (VPSRLW256const [a] x) mask)
	// result: (VPSRLWMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLW256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLWMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU16Masked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU16Masked512 (VPABSW512 x) mask)
	// result: (VPABSWMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSW512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSWMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPADDW512 x y) mask)
	// result: (VPADDWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPADDSW512 x y) mask)
	// result: (VPADDSWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDSW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDSWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPADDUSW512 x y) mask)
	// result: (VPADDUSWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDUSW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDUSWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPAVGW512 x y) mask)
	// result: (VPAVGWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPAVGW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPAVGWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPERMI2W512 x y z) mask)
	// result: (VPERMI2WMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2W512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2WMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMADDWD512 x y) mask)
	// result: (VPMADDWDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMADDWD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMADDWDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMADDUBSW512 x y) mask)
	// result: (VPMADDUBSWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMADDUBSW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMADDUBSWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMOVSXWD512 x) mask)
	// result: (VPMOVSXWDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXWD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMOVSXWQ512 x) mask)
	// result: (VPMOVSXWQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXWQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMOVZXWD512 x) mask)
	// result: (VPMOVZXWDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXWD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMOVZXWQ512 x) mask)
	// result: (VPMOVZXWQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXWQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMAXSW512 x y) mask)
	// result: (VPMAXSWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMAXUW512 x y) mask)
	// result: (VPMAXUWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMINSW512 x y) mask)
	// result: (VPMINSWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMINUW512 x y) mask)
	// result: (VPMINUWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMULHW512 x y) mask)
	// result: (VPMULHWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULHW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULHWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMULHUW512 x y) mask)
	// result: (VPMULHUWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULHUW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULHUWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPMULLW512 x y) mask)
	// result: (VPMULLWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPOPCNTW512 x) mask)
	// result: (VPOPCNTWMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTW512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTWMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPERMW512 x y) mask)
	// result: (VPERMWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSHLDW512 [a] x y) mask)
	// result: (VPSHLDWMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDW512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDWMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSLLW512 x y) mask)
	// result: (VPSLLWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSHRDW512 [a] x y) mask)
	// result: (VPSHRDWMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDW512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDWMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSRAW512 x y) mask)
	// result: (VPSRAWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSRLW512 x y) mask)
	// result: (VPSRLWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSHLDVW512 x y z) mask)
	// result: (VPSHLDVWMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVW512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVWMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSLLVW512 x y) mask)
	// result: (VPSLLVWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSHRDVW512 x y z) mask)
	// result: (VPSHRDVWMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVW512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVWMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSRAVW512 x y) mask)
	// result: (VPSRAVWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSRLVW512 x y) mask)
	// result: (VPSRLVWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSUBW512 x y) mask)
	// result: (VPSUBWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSUBSW512 x y) mask)
	// result: (VPSUBSWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBSW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBSWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSUBUSW512 x y) mask)
	// result: (VPSUBUSWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBUSW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBUSWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSHUFHW512 [a] x) mask)
	// result: (VPSHUFHWMasked512 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFHW512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFHWMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSHUFLW512 [a] x) mask)
	// result: (VPSHUFLWMasked512 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFLW512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFLWMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSLLW512const [a] x) mask)
	// result: (VPSLLWMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLW512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLWMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSRAW512const [a] x) mask)
	// result: (VPSRAWMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAW512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAWMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU16Masked512 (VPSRLW512const [a] x) mask)
	// result: (VPSRLWMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLW512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLWMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU32Masked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU32Masked128 (VPABSD128 x) mask)
	// result: (VPABSDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VADDPS128 x y) mask)
	// result: (VADDPSMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VADDPS128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VADDPSMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPADDD128 x y) mask)
	// result: (VPADDDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VRNDSCALEPS128 [a] x) mask)
	// result: (VRNDSCALEPSMasked128 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRNDSCALEPS128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VREDUCEPS128 [a] x) mask)
	// result: (VREDUCEPSMasked128 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VREDUCEPS128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPERMI2PS128 x y z) mask)
	// result: (VPERMI2PSMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2PS128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2PSMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPERMI2D128 x y z) mask)
	// result: (VPERMI2DMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2D128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2DMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VCVTDQ2PS128 x) mask)
	// result: (VCVTDQ2PSMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTDQ2PS128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VCVTUDQ2PS128 x) mask)
	// result: (VCVTUDQ2PSMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUDQ2PS128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VCVTTPS2DQ128 x) mask)
	// result: (VCVTTPS2DQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2DQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VCVTTPS2UDQ128 x) mask)
	// result: (VCVTTPS2UDQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2UDQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VDIVPS128 x y) mask)
	// result: (VDIVPSMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VDIVPS128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VDIVPSMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMOVSXDQ128 x) mask)
	// result: (VPMOVSXDQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXDQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMOVZXDQ128 x) mask)
	// result: (VPMOVZXDQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXDQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPLZCNTD128 x) mask)
	// result: (VPLZCNTDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPLZCNTD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VMAXPS128 x y) mask)
	// result: (VMAXPSMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMAXPS128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMAXPSMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMAXSD128 x y) mask)
	// result: (VPMAXSDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMAXUD128 x y) mask)
	// result: (VPMAXUDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VMINPS128 x y) mask)
	// result: (VMINPSMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMINPS128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMINPSMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMINSD128 x y) mask)
	// result: (VPMINSDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMINUD128 x y) mask)
	// result: (VPMINUDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VFMADDSUB213PS128 x y z) mask)
	// result: (VFMADDSUB213PSMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADDSUB213PS128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADDSUB213PSMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VFMADD213PS128 x y z) mask)
	// result: (VFMADD213PSMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADD213PS128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADD213PSMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VFMSUBADD213PS128 x y z) mask)
	// result: (VFMSUBADD213PSMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMSUBADD213PS128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMSUBADD213PSMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VMULPS128 x y) mask)
	// result: (VMULPSMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMULPS128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMULPSMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMULLD128 x y) mask)
	// result: (VPMULLDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPOPCNTD128 x) mask)
	// result: (VPOPCNTDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPROLVD128 x y) mask)
	// result: (VPROLVDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPROLVD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPROLVDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPRORVD128 x y) mask)
	// result: (VPRORVDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPRORVD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPRORVDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMOVSDB128_128 x) mask)
	// result: (VPMOVSDBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSDB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSDBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPACKSSDW128 x y) mask)
	// result: (VPACKSSDWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPACKSSDW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMOVSDW128_128 x) mask)
	// result: (VPMOVSDWMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSDW128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSDWMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMOVUSDB128_128 x) mask)
	// result: (VPMOVUSDBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSDB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSDBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPACKUSDW128 x y) mask)
	// result: (VPACKUSDWMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPACKUSDW128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMOVUSDW128_128 x) mask)
	// result: (VPMOVUSDWMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSDW128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSDWMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VSCALEFPS128 x y) mask)
	// result: (VSCALEFPSMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSCALEFPS128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSHLDD128 [a] x y) mask)
	// result: (VPSHLDDMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDD128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDDMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSLLD128 x y) mask)
	// result: (VPSLLDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSHRDD128 [a] x y) mask)
	// result: (VPSHRDDMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDD128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDDMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSRAD128 x y) mask)
	// result: (VPSRADMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRADMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSRLD128 x y) mask)
	// result: (VPSRLDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSHLDVD128 x y z) mask)
	// result: (VPSHLDVDMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVD128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVDMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSLLVD128 x y) mask)
	// result: (VPSLLVDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSHRDVD128 x y z) mask)
	// result: (VPSHRDVDMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVD128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVDMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSRAVD128 x y) mask)
	// result: (VPSRAVDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSRLVD128 x y) mask)
	// result: (VPSRLVDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VSQRTPS128 x) mask)
	// result: (VSQRTPSMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSQRTPS128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSQRTPSMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VSUBPS128 x y) mask)
	// result: (VSUBPSMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSUBPS128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSUBPSMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSUBD128 x y) mask)
	// result: (VPSUBDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMOVDB128_128 x) mask)
	// result: (VPMOVDBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVDB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVDBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPMOVDW128_128 x) mask)
	// result: (VPMOVDWMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVDW128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVDWMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSHUFD128 [a] x) mask)
	// result: (VPSHUFDMasked128 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFD128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFDMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSLLD128const [a] x) mask)
	// result: (VPSLLDMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLD128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLDMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSRAD128const [a] x) mask)
	// result: (VPSRADMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAD128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRADMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked128 (VPSRLD128const [a] x) mask)
	// result: (VPSRLDMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLD128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLDMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU32Masked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU32Masked256 (VPABSD256 x) mask)
	// result: (VPABSDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VADDPS256 x y) mask)
	// result: (VADDPSMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VADDPS256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VADDPSMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPADDD256 x y) mask)
	// result: (VPADDDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VRNDSCALEPS256 [a] x) mask)
	// result: (VRNDSCALEPSMasked256 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRNDSCALEPS256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VREDUCEPS256 [a] x) mask)
	// result: (VREDUCEPSMasked256 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VREDUCEPS256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPERMI2PS256 x y z) mask)
	// result: (VPERMI2PSMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2PS256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2PSMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPERMI2D256 x y z) mask)
	// result: (VPERMI2DMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2D256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2DMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTDQ2PS256 x) mask)
	// result: (VCVTDQ2PSMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTDQ2PS256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTUDQ2PS256 x) mask)
	// result: (VCVTUDQ2PSMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUDQ2PS256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTPS2PD256 x) mask)
	// result: (VCVTPS2PDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTPS2PD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTPS2PDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTDQ2PD256 x) mask)
	// result: (VCVTDQ2PDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTDQ2PD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTDQ2PDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTUDQ2PD256 x) mask)
	// result: (VCVTUDQ2PDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUDQ2PD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUDQ2PDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTTPS2DQ256 x) mask)
	// result: (VCVTTPS2DQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2DQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTTPS2QQ256 x) mask)
	// result: (VCVTTPS2QQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2QQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2QQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTTPS2UDQ256 x) mask)
	// result: (VCVTTPS2UDQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2UDQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VCVTTPS2UQQ256 x) mask)
	// result: (VCVTTPS2UQQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2UQQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2UQQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VDIVPS256 x y) mask)
	// result: (VDIVPSMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VDIVPS256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VDIVPSMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVSXDQ256 x) mask)
	// result: (VPMOVSXDQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXDQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVZXDQ256 x) mask)
	// result: (VPMOVZXDQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXDQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPLZCNTD256 x) mask)
	// result: (VPLZCNTDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPLZCNTD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VMAXPS256 x y) mask)
	// result: (VMAXPSMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMAXPS256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMAXPSMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMAXSD256 x y) mask)
	// result: (VPMAXSDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMAXUD256 x y) mask)
	// result: (VPMAXUDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VMINPS256 x y) mask)
	// result: (VMINPSMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMINPS256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMINPSMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMINSD256 x y) mask)
	// result: (VPMINSDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMINUD256 x y) mask)
	// result: (VPMINUDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VFMADDSUB213PS256 x y z) mask)
	// result: (VFMADDSUB213PSMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADDSUB213PS256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADDSUB213PSMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VFMADD213PS256 x y z) mask)
	// result: (VFMADD213PSMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADD213PS256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADD213PSMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VFMSUBADD213PS256 x y z) mask)
	// result: (VFMSUBADD213PSMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMSUBADD213PS256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMSUBADD213PSMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VMULPS256 x y) mask)
	// result: (VMULPSMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMULPS256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMULPSMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMULLD256 x y) mask)
	// result: (VPMULLDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPOPCNTD256 x) mask)
	// result: (VPOPCNTDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPERMPS256 x y) mask)
	// result: (VPERMPSMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMPS256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMPSMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPERMD256 x y) mask)
	// result: (VPERMDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPROLVD256 x y) mask)
	// result: (VPROLVDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPROLVD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPROLVDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPRORVD256 x y) mask)
	// result: (VPRORVDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPRORVD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPRORVDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVSDB128_256 x) mask)
	// result: (VPMOVSDBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSDB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSDBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPACKSSDW256 x y) mask)
	// result: (VPACKSSDWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPACKSSDW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVSDW128_256 x) mask)
	// result: (VPMOVSDWMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSDW128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSDWMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVSDW256 x) mask)
	// result: (VPMOVSDWMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSDW256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSDWMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVUSDB128_256 x) mask)
	// result: (VPMOVUSDBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSDB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSDBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPACKUSDW256 x y) mask)
	// result: (VPACKUSDWMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPACKUSDW256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVUSDW128_256 x) mask)
	// result: (VPMOVUSDWMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSDW128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSDWMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVUSDW256 x) mask)
	// result: (VPMOVUSDWMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSDW256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSDWMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VSCALEFPS256 x y) mask)
	// result: (VSCALEFPSMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSCALEFPS256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSHLDD256 [a] x y) mask)
	// result: (VPSHLDDMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDD256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDDMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSLLD256 x y) mask)
	// result: (VPSLLDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSHRDD256 [a] x y) mask)
	// result: (VPSHRDDMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDD256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDDMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSRAD256 x y) mask)
	// result: (VPSRADMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRADMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSRLD256 x y) mask)
	// result: (VPSRLDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSHLDVD256 x y z) mask)
	// result: (VPSHLDVDMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVD256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVDMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSLLVD256 x y) mask)
	// result: (VPSLLVDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSHRDVD256 x y z) mask)
	// result: (VPSHRDVDMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVD256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVDMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSRAVD256 x y) mask)
	// result: (VPSRAVDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSRLVD256 x y) mask)
	// result: (VPSRLVDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VSQRTPS256 x) mask)
	// result: (VSQRTPSMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSQRTPS256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSQRTPSMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VSUBPS256 x y) mask)
	// result: (VSUBPSMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSUBPS256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSUBPSMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSUBD256 x y) mask)
	// result: (VPSUBDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVDB128_256 x) mask)
	// result: (VPMOVDBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVDB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVDBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVDW128_256 x) mask)
	// result: (VPMOVDWMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVDW128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVDWMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPMOVDW256 x) mask)
	// result: (VPMOVDWMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVDW256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVDWMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSHUFD256 [a] x) mask)
	// result: (VPSHUFDMasked256 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFD256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFDMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSLLD256const [a] x) mask)
	// result: (VPSLLDMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLD256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLDMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSRAD256const [a] x) mask)
	// result: (VPSRADMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAD256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRADMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked256 (VPSRLD256const [a] x) mask)
	// result: (VPSRLDMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLD256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLDMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU32Masked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU32Masked512 (VPABSD512 x) mask)
	// result: (VPABSDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VADDPS512 x y) mask)
	// result: (VADDPSMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VADDPS512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VADDPSMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPADDD512 x y) mask)
	// result: (VPADDDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPANDD512 x y) mask)
	// result: (VPANDDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPANDD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPANDDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPANDND512 x y) mask)
	// result: (VPANDNDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPANDND512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPANDNDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VRNDSCALEPS512 [a] x) mask)
	// result: (VRNDSCALEPSMasked512 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRNDSCALEPS512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VREDUCEPS512 [a] x) mask)
	// result: (VREDUCEPSMasked512 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VREDUCEPS512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPERMI2PS512 x y z) mask)
	// result: (VPERMI2PSMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2PS512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2PSMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPERMI2D512 x y z) mask)
	// result: (VPERMI2DMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2D512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2DMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTDQ2PS512 x) mask)
	// result: (VCVTDQ2PSMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTDQ2PS512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTUDQ2PS512 x) mask)
	// result: (VCVTUDQ2PSMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUDQ2PS512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTPS2PD512 x) mask)
	// result: (VCVTPS2PDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTPS2PD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTPS2PDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTDQ2PD512 x) mask)
	// result: (VCVTDQ2PDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTDQ2PD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTDQ2PDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTUDQ2PD512 x) mask)
	// result: (VCVTUDQ2PDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUDQ2PD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUDQ2PDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTTPS2DQ512 x) mask)
	// result: (VCVTTPS2DQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2DQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTTPS2QQ512 x) mask)
	// result: (VCVTTPS2QQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2QQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2QQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTTPS2UDQ512 x) mask)
	// result: (VCVTTPS2UDQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2UDQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VCVTTPS2UQQ512 x) mask)
	// result: (VCVTTPS2UQQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPS2UQQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPS2UQQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VDIVPS512 x y) mask)
	// result: (VDIVPSMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VDIVPS512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VDIVPSMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMOVSXDQ512 x) mask)
	// result: (VPMOVSXDQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXDQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMOVZXDQ512 x) mask)
	// result: (VPMOVZXDQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXDQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPLZCNTD512 x) mask)
	// result: (VPLZCNTDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPLZCNTD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VMAXPS512 x y) mask)
	// result: (VMAXPSMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMAXPS512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMAXPSMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMAXSD512 x y) mask)
	// result: (VPMAXSDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMAXUD512 x y) mask)
	// result: (VPMAXUDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VMINPS512 x y) mask)
	// result: (VMINPSMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMINPS512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMINPSMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMINSD512 x y) mask)
	// result: (VPMINSDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMINUD512 x y) mask)
	// result: (VPMINUDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VFMADDSUB213PS512 x y z) mask)
	// result: (VFMADDSUB213PSMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADDSUB213PS512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADDSUB213PSMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VFMADD213PS512 x y z) mask)
	// result: (VFMADD213PSMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADD213PS512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADD213PSMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VFMSUBADD213PS512 x y z) mask)
	// result: (VFMSUBADD213PSMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMSUBADD213PS512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMSUBADD213PSMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VMULPS512 x y) mask)
	// result: (VMULPSMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMULPS512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMULPSMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMULLD512 x y) mask)
	// result: (VPMULLDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPOPCNTD512 x) mask)
	// result: (VPOPCNTDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPORD512 x y) mask)
	// result: (VPORDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPORD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPORDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPERMPS512 x y) mask)
	// result: (VPERMPSMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMPS512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMPSMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPERMD512 x y) mask)
	// result: (VPERMDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VRCP14PS512 x) mask)
	// result: (VRCP14PSMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRCP14PS512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRCP14PSMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VRSQRT14PS512 x) mask)
	// result: (VRSQRT14PSMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRSQRT14PS512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRSQRT14PSMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPROLVD512 x y) mask)
	// result: (VPROLVDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPROLVD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPROLVDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPRORVD512 x y) mask)
	// result: (VPRORVDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPRORVD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPRORVDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMOVSDB128_512 x) mask)
	// result: (VPMOVSDBMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSDB128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSDBMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPACKSSDW512 x y) mask)
	// result: (VPACKSSDWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPACKSSDW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMOVUSDB128_512 x) mask)
	// result: (VPMOVUSDBMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSDB128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSDBMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPACKUSDW512 x y) mask)
	// result: (VPACKUSDWMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPACKUSDW512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VSCALEFPS512 x y) mask)
	// result: (VSCALEFPSMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSCALEFPS512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSHLDD512 [a] x y) mask)
	// result: (VPSHLDDMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDD512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDDMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSLLD512 x y) mask)
	// result: (VPSLLDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSHRDD512 [a] x y) mask)
	// result: (VPSHRDDMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDD512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDDMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSRAD512 x y) mask)
	// result: (VPSRADMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRADMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSRLD512 x y) mask)
	// result: (VPSRLDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSHLDVD512 x y z) mask)
	// result: (VPSHLDVDMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVD512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVDMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSLLVD512 x y) mask)
	// result: (VPSLLVDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSHRDVD512 x y z) mask)
	// result: (VPSHRDVDMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVD512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVDMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSRAVD512 x y) mask)
	// result: (VPSRAVDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSRLVD512 x y) mask)
	// result: (VPSRLVDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VSQRTPS512 x) mask)
	// result: (VSQRTPSMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSQRTPS512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSQRTPSMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VSUBPS512 x y) mask)
	// result: (VSUBPSMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSUBPS512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSUBPSMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSUBD512 x y) mask)
	// result: (VPSUBDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPMOVDB128_512 x) mask)
	// result: (VPMOVDBMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVDB128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVDBMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPXORD512 x y) mask)
	// result: (VPXORDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPXORD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPXORDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSHUFD512 [a] x) mask)
	// result: (VPSHUFDMasked512 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFD512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFDMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSLLD512const [a] x) mask)
	// result: (VPSLLDMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLD512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLDMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSRAD512const [a] x) mask)
	// result: (VPSRADMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAD512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRADMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU32Masked512 (VPSRLD512const [a] x) mask)
	// result: (VPSRLDMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLD512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLDMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU64Masked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU64Masked128 (VPABSQ128 x) mask)
	// result: (VPABSQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VADDPD128 x y) mask)
	// result: (VADDPDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VADDPD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VADDPDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPADDQ128 x y) mask)
	// result: (VPADDQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VRNDSCALEPD128 [a] x) mask)
	// result: (VRNDSCALEPDMasked128 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRNDSCALEPD128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VREDUCEPD128 [a] x) mask)
	// result: (VREDUCEPDMasked128 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VREDUCEPD128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPERMI2PD128 x y z) mask)
	// result: (VPERMI2PDMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2PD128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2PDMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPERMI2Q128 x y z) mask)
	// result: (VPERMI2QMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2Q128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2QMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTPD2PSX128 x) mask)
	// result: (VCVTPD2PSXMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTPD2PSX128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTPD2PSXMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTPD2PSY128 x) mask)
	// result: (VCVTPD2PSYMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTPD2PSY128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTPD2PSYMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTQQ2PSX128 x) mask)
	// result: (VCVTQQ2PSXMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTQQ2PSX128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTQQ2PSXMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTQQ2PSY128 x) mask)
	// result: (VCVTQQ2PSYMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTQQ2PSY128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTQQ2PSYMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTUQQ2PSX128 x) mask)
	// result: (VCVTUQQ2PSXMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUQQ2PSX128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSXMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTUQQ2PSY128 x) mask)
	// result: (VCVTUQQ2PSYMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUQQ2PSY128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSYMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTQQ2PD128 x) mask)
	// result: (VCVTQQ2PDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTQQ2PD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTUQQ2PD128 x) mask)
	// result: (VCVTUQQ2PDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUQQ2PD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTTPD2DQX128 x) mask)
	// result: (VCVTTPD2DQXMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2DQX128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2DQXMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTTPD2DQY128 x) mask)
	// result: (VCVTTPD2DQYMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2DQY128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2DQYMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTTPD2QQ128 x) mask)
	// result: (VCVTTPD2QQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2QQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTTPD2UDQX128 x) mask)
	// result: (VCVTTPD2UDQXMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2UDQX128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQXMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTTPD2UDQY128 x) mask)
	// result: (VCVTTPD2UDQYMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2UDQY128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQYMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VCVTTPD2UQQ128 x) mask)
	// result: (VCVTTPD2UQQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2UQQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VDIVPD128 x y) mask)
	// result: (VDIVPDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VDIVPD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VDIVPDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPLZCNTQ128 x) mask)
	// result: (VPLZCNTQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPLZCNTQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VMAXPD128 x y) mask)
	// result: (VMAXPDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMAXPD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMAXPDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMAXSQ128 x y) mask)
	// result: (VPMAXSQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMAXUQ128 x y) mask)
	// result: (VPMAXUQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VMINPD128 x y) mask)
	// result: (VMINPDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMINPD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMINPDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMINSQ128 x y) mask)
	// result: (VPMINSQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMINUQ128 x y) mask)
	// result: (VPMINUQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VFMADDSUB213PD128 x y z) mask)
	// result: (VFMADDSUB213PDMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADDSUB213PD128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADDSUB213PDMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VFMADD213PD128 x y z) mask)
	// result: (VFMADD213PDMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADD213PD128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADD213PDMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VFMSUBADD213PD128 x y z) mask)
	// result: (VFMSUBADD213PDMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMSUBADD213PD128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMSUBADD213PDMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VMULPD128 x y) mask)
	// result: (VMULPDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMULPD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMULPDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMULLQ128 x y) mask)
	// result: (VPMULLQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPOPCNTQ128 x) mask)
	// result: (VPOPCNTQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VRCP14PD128 x) mask)
	// result: (VRCP14PDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRCP14PD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRCP14PDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VRSQRT14PD128 x) mask)
	// result: (VRSQRT14PDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRSQRT14PD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPROLVQ128 x y) mask)
	// result: (VPROLVQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPROLVQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPROLVQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPRORVQ128 x y) mask)
	// result: (VPRORVQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPRORVQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPRORVQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVSQB128_128 x) mask)
	// result: (VPMOVSQBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVSQW128_128 x) mask)
	// result: (VPMOVSQWMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQW128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQWMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVSQD128_128 x) mask)
	// result: (VPMOVSQDMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQD128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQDMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVUSQB128_128 x) mask)
	// result: (VPMOVUSQBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVUSQW128_128 x) mask)
	// result: (VPMOVUSQWMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQW128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQWMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVUSQD128_128 x) mask)
	// result: (VPMOVUSQDMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQD128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQDMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VSCALEFPD128 x y) mask)
	// result: (VSCALEFPDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSCALEFPD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSHLDQ128 [a] x y) mask)
	// result: (VPSHLDQMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDQ128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDQMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSLLQ128 x y) mask)
	// result: (VPSLLQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSHRDQ128 [a] x y) mask)
	// result: (VPSHRDQMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDQ128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDQMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSRAQ128 x y) mask)
	// result: (VPSRAQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSRLQ128 x y) mask)
	// result: (VPSRLQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSHLDVQ128 x y z) mask)
	// result: (VPSHLDVQMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVQ128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVQMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSLLVQ128 x y) mask)
	// result: (VPSLLVQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSHRDVQ128 x y z) mask)
	// result: (VPSHRDVQMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVQ128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVQMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSRAVQ128 x y) mask)
	// result: (VPSRAVQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSRLVQ128 x y) mask)
	// result: (VPSRLVQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VSQRTPD128 x) mask)
	// result: (VSQRTPDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSQRTPD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSQRTPDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VSUBPD128 x y) mask)
	// result: (VSUBPDMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSUBPD128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSUBPDMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSUBQ128 x y) mask)
	// result: (VPSUBQMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBQ128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBQMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVQB128_128 x) mask)
	// result: (VPMOVQBMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQB128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQBMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVQW128_128 x) mask)
	// result: (VPMOVQWMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQW128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQWMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPMOVQD128_128 x) mask)
	// result: (VPMOVQDMasked128_128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQD128_128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQDMasked128_128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSLLQ128const [a] x) mask)
	// result: (VPSLLQMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLQ128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLQMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSRAQ128const [a] x) mask)
	// result: (VPSRAQMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAQ128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAQMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked128 (VPSRLQ128const [a] x) mask)
	// result: (VPSRLQMasked128const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLQ128const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLQMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU64Masked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU64Masked256 (VPABSQ256 x) mask)
	// result: (VPABSQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VADDPD256 x y) mask)
	// result: (VADDPDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VADDPD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VADDPDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPADDQ256 x y) mask)
	// result: (VPADDQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VRNDSCALEPD256 [a] x) mask)
	// result: (VRNDSCALEPDMasked256 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRNDSCALEPD256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VREDUCEPD256 [a] x) mask)
	// result: (VREDUCEPDMasked256 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VREDUCEPD256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPERMI2PD256 x y z) mask)
	// result: (VPERMI2PDMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2PD256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2PDMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPERMI2Q256 x y z) mask)
	// result: (VPERMI2QMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2Q256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2QMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTPD2PS256 x) mask)
	// result: (VCVTPD2PSMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTPD2PS256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTPD2PSMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTQQ2PS256 x) mask)
	// result: (VCVTQQ2PSMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTQQ2PS256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTQQ2PSMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTUQQ2PS256 x) mask)
	// result: (VCVTUQQ2PSMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUQQ2PS256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTQQ2PD256 x) mask)
	// result: (VCVTQQ2PDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTQQ2PD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTUQQ2PD256 x) mask)
	// result: (VCVTUQQ2PDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUQQ2PD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTTPD2DQ256 x) mask)
	// result: (VCVTTPD2DQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2DQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2DQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTTPD2QQ256 x) mask)
	// result: (VCVTTPD2QQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2QQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTTPD2UDQ256 x) mask)
	// result: (VCVTTPD2UDQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2UDQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VCVTTPD2UQQ256 x) mask)
	// result: (VCVTTPD2UQQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2UQQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VDIVPD256 x y) mask)
	// result: (VDIVPDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VDIVPD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VDIVPDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPLZCNTQ256 x) mask)
	// result: (VPLZCNTQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPLZCNTQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VMAXPD256 x y) mask)
	// result: (VMAXPDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMAXPD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMAXPDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMAXSQ256 x y) mask)
	// result: (VPMAXSQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMAXUQ256 x y) mask)
	// result: (VPMAXUQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VMINPD256 x y) mask)
	// result: (VMINPDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMINPD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMINPDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMINSQ256 x y) mask)
	// result: (VPMINSQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMINUQ256 x y) mask)
	// result: (VPMINUQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VFMADDSUB213PD256 x y z) mask)
	// result: (VFMADDSUB213PDMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADDSUB213PD256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADDSUB213PDMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VFMADD213PD256 x y z) mask)
	// result: (VFMADD213PDMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADD213PD256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADD213PDMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VFMSUBADD213PD256 x y z) mask)
	// result: (VFMSUBADD213PDMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMSUBADD213PD256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMSUBADD213PDMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VMULPD256 x y) mask)
	// result: (VMULPDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMULPD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMULPDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMULLQ256 x y) mask)
	// result: (VPMULLQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPOPCNTQ256 x) mask)
	// result: (VPOPCNTQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPERMPD256 x y) mask)
	// result: (VPERMPDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMPD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMPDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPERMQ256 x y) mask)
	// result: (VPERMQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VRCP14PD256 x) mask)
	// result: (VRCP14PDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRCP14PD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRCP14PDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VRSQRT14PD256 x) mask)
	// result: (VRSQRT14PDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRSQRT14PD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPROLVQ256 x y) mask)
	// result: (VPROLVQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPROLVQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPROLVQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPRORVQ256 x y) mask)
	// result: (VPRORVQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPRORVQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPRORVQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVSQB128_256 x) mask)
	// result: (VPMOVSQBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVSQW128_256 x) mask)
	// result: (VPMOVSQWMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQW128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQWMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVSQD128_256 x) mask)
	// result: (VPMOVSQDMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQD128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQDMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVSQD256 x) mask)
	// result: (VPMOVSQDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVUSQB128_256 x) mask)
	// result: (VPMOVUSQBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVUSQW128_256 x) mask)
	// result: (VPMOVUSQWMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQW128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQWMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVUSQD128_256 x) mask)
	// result: (VPMOVUSQDMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQD128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQDMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVUSQD256 x) mask)
	// result: (VPMOVUSQDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VSCALEFPD256 x y) mask)
	// result: (VSCALEFPDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSCALEFPD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSHLDQ256 [a] x y) mask)
	// result: (VPSHLDQMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDQ256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDQMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSLLQ256 x y) mask)
	// result: (VPSLLQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSHRDQ256 [a] x y) mask)
	// result: (VPSHRDQMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDQ256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDQMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSRAQ256 x y) mask)
	// result: (VPSRAQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSRLQ256 x y) mask)
	// result: (VPSRLQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSHLDVQ256 x y z) mask)
	// result: (VPSHLDVQMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVQ256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVQMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSLLVQ256 x y) mask)
	// result: (VPSLLVQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSHRDVQ256 x y z) mask)
	// result: (VPSHRDVQMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVQ256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVQMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSRAVQ256 x y) mask)
	// result: (VPSRAVQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSRLVQ256 x y) mask)
	// result: (VPSRLVQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VSQRTPD256 x) mask)
	// result: (VSQRTPDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSQRTPD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSQRTPDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VSUBPD256 x y) mask)
	// result: (VSUBPDMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSUBPD256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSUBPDMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSUBQ256 x y) mask)
	// result: (VPSUBQMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBQ256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBQMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVQB128_256 x) mask)
	// result: (VPMOVQBMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQB128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQBMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVQW128_256 x) mask)
	// result: (VPMOVQWMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQW128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQWMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVQD128_256 x) mask)
	// result: (VPMOVQDMasked128_256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQD128_256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQDMasked128_256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPMOVQD256 x) mask)
	// result: (VPMOVQDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSLLQ256const [a] x) mask)
	// result: (VPSLLQMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLQ256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLQMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSRAQ256const [a] x) mask)
	// result: (VPSRAQMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAQ256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAQMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked256 (VPSRLQ256const [a] x) mask)
	// result: (VPSRLQMasked256const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLQ256const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLQMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU64Masked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU64Masked512 (VPABSQ512 x) mask)
	// result: (VPABSQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VADDPD512 x y) mask)
	// result: (VADDPDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VADDPD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VADDPDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPADDQ512 x y) mask)
	// result: (VPADDQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPANDQ512 x y) mask)
	// result: (VPANDQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPANDQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPANDQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPANDNQ512 x y) mask)
	// result: (VPANDNQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPANDNQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPANDNQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VRNDSCALEPD512 [a] x) mask)
	// result: (VRNDSCALEPDMasked512 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRNDSCALEPD512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VREDUCEPD512 [a] x) mask)
	// result: (VREDUCEPDMasked512 [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VREDUCEPD512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPERMI2PD512 x y z) mask)
	// result: (VPERMI2PDMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2PD512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2PDMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPERMI2Q512 x y z) mask)
	// result: (VPERMI2QMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2Q512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2QMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VCVTQQ2PD512 x) mask)
	// result: (VCVTQQ2PDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTQQ2PD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VCVTUQQ2PD512 x) mask)
	// result: (VCVTUQQ2PDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTUQQ2PD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VCVTTPD2QQ512 x) mask)
	// result: (VCVTTPD2QQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2QQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VCVTTPD2UQQ512 x) mask)
	// result: (VCVTTPD2UQQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VCVTTPD2UQQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VDIVPD512 x y) mask)
	// result: (VDIVPDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VDIVPD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VDIVPDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPLZCNTQ512 x) mask)
	// result: (VPLZCNTQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPLZCNTQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VMAXPD512 x y) mask)
	// result: (VMAXPDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMAXPD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMAXPDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMAXSQ512 x y) mask)
	// result: (VPMAXSQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMAXUQ512 x y) mask)
	// result: (VPMAXUQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VMINPD512 x y) mask)
	// result: (VMINPDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMINPD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMINPDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMINSQ512 x y) mask)
	// result: (VPMINSQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMINUQ512 x y) mask)
	// result: (VPMINUQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VFMADDSUB213PD512 x y z) mask)
	// result: (VFMADDSUB213PDMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADDSUB213PD512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADDSUB213PDMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VFMADD213PD512 x y z) mask)
	// result: (VFMADD213PDMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMADD213PD512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMADD213PDMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VFMSUBADD213PD512 x y z) mask)
	// result: (VFMSUBADD213PDMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VFMSUBADD213PD512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VFMSUBADD213PDMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VMULPD512 x y) mask)
	// result: (VMULPDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VMULPD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VMULPDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMULLQ512 x y) mask)
	// result: (VPMULLQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMULLQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMULLQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPOPCNTQ512 x) mask)
	// result: (VPOPCNTQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPORQ512 x y) mask)
	// result: (VPORQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPORQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPORQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPERMPD512 x y) mask)
	// result: (VPERMPDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMPD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMPDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPERMQ512 x y) mask)
	// result: (VPERMQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VRCP14PD512 x) mask)
	// result: (VRCP14PDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRCP14PD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRCP14PDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VRSQRT14PD512 x) mask)
	// result: (VRSQRT14PDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VRSQRT14PD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPROLVQ512 x y) mask)
	// result: (VPROLVQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPROLVQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPROLVQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPRORVQ512 x y) mask)
	// result: (VPRORVQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPRORVQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPRORVQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMOVSQB128_512 x) mask)
	// result: (VPMOVSQBMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQB128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQBMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMOVSQW128_512 x) mask)
	// result: (VPMOVSQWMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSQW128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSQWMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMOVUSQB128_512 x) mask)
	// result: (VPMOVUSQBMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQB128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQBMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMOVUSQW128_512 x) mask)
	// result: (VPMOVUSQWMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVUSQW128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVUSQWMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VSCALEFPD512 x y) mask)
	// result: (VSCALEFPDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSCALEFPD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSHLDQ512 [a] x y) mask)
	// result: (VPSHLDQMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDQ512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDQMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSLLQ512 x y) mask)
	// result: (VPSLLQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSHRDQ512 [a] x y) mask)
	// result: (VPSHRDQMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDQ512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDQMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSRAQ512 x y) mask)
	// result: (VPSRAQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSRLQ512 x y) mask)
	// result: (VPSRLQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSHLDVQ512 x y z) mask)
	// result: (VPSHLDVQMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHLDVQ512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHLDVQMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSLLVQ512 x y) mask)
	// result: (VPSLLVQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLVQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLVQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSHRDVQ512 x y z) mask)
	// result: (VPSHRDVQMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHRDVQ512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHRDVQMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSRAVQ512 x y) mask)
	// result: (VPSRAVQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAVQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAVQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSRLVQ512 x y) mask)
	// result: (VPSRLVQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLVQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLVQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VSQRTPD512 x) mask)
	// result: (VSQRTPDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSQRTPD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSQRTPDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VSUBPD512 x y) mask)
	// result: (VSUBPDMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VSUBPD512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VSUBPDMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSUBQ512 x y) mask)
	// result: (VPSUBQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMOVQB128_512 x) mask)
	// result: (VPMOVQBMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQB128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQBMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPMOVQW128_512 x) mask)
	// result: (VPMOVQWMasked128_512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVQW128_512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVQWMasked128_512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPXORQ512 x y) mask)
	// result: (VPXORQMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPXORQ512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPXORQMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSLLQ512const [a] x) mask)
	// result: (VPSLLQMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSLLQ512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSLLQMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSRAQ512const [a] x) mask)
	// result: (VPSRAQMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRAQ512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRAQMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU64Masked512 (VPSRLQ512const [a] x) mask)
	// result: (VPSRLQMasked512const [a] x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSRLQ512const {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSRLQMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU8Masked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU8Masked128 (VPABSB128 x) mask)
	// result: (VPABSBMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSB128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSBMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPADDB128 x y) mask)
	// result: (VPADDBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPADDSB128 x y) mask)
	// result: (VPADDSBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDSB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDSBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPADDUSB128 x y) mask)
	// result: (VPADDUSBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDUSB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDUSBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPAVGB128 x y) mask)
	// result: (VPAVGBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPAVGB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPAVGBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPERMI2B128 x y z) mask)
	// result: (VPERMI2BMasked128 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2B128 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2BMasked128)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPALIGNR128 [a] x y) mask)
	// result: (VPALIGNRMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPALIGNR128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPALIGNRMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMOVSXBQ128 x) mask)
	// result: (VPMOVSXBQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMOVZXBQ128 x) mask)
	// result: (VPMOVZXBQMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBQ128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBQMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMOVSXBD128 x) mask)
	// result: (VPMOVSXBDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMOVZXBD128 x) mask)
	// result: (VPMOVZXBDMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBD128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMOVSXBW128 x) mask)
	// result: (VPMOVSXBWMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBW128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMOVZXBW128 x) mask)
	// result: (VPMOVZXBWMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBW128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VGF2P8AFFINEINVQB128 [a] x y) mask)
	// result: (VGF2P8AFFINEINVQBMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8AFFINEINVQB128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQBMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VGF2P8AFFINEQB128 [a] x y) mask)
	// result: (VGF2P8AFFINEQBMasked128 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8AFFINEQB128 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQBMasked128)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VGF2P8MULB128 x y) mask)
	// result: (VGF2P8MULBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8MULB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8MULBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMAXSB128 x y) mask)
	// result: (VPMAXSBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMAXUB128 x y) mask)
	// result: (VPMAXUBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMINSB128 x y) mask)
	// result: (VPMINSBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPMINUB128 x y) mask)
	// result: (VPMINUBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPOPCNTB128 x) mask)
	// result: (VPOPCNTBMasked128 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTB128 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTBMasked128)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPERMB128 x y) mask)
	// result: (VPERMBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPSHUFB128 x y) mask)
	// result: (VPSHUFBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPSUBB128 x y) mask)
	// result: (VPSUBBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPSUBSB128 x y) mask)
	// result: (VPSUBSBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBSB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBSBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked128 (VPSUBUSB128 x y) mask)
	// result: (VPSUBUSBMasked128 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBUSB128 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBUSBMasked128)
		v.AddArg3(x, y, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU8Masked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU8Masked256 (VPABSB256 x) mask)
	// result: (VPABSBMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSB256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSBMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPADDB256 x y) mask)
	// result: (VPADDBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPADDSB256 x y) mask)
	// result: (VPADDSBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDSB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDSBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPADDUSB256 x y) mask)
	// result: (VPADDUSBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDUSB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDUSBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPAVGB256 x y) mask)
	// result: (VPAVGBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPAVGB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPAVGBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPERMI2B256 x y z) mask)
	// result: (VPERMI2BMasked256 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2B256 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2BMasked256)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPALIGNR256 [a] x y) mask)
	// result: (VPALIGNRMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPALIGNR256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPALIGNRMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMOVSXBQ256 x) mask)
	// result: (VPMOVSXBQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMOVZXBQ256 x) mask)
	// result: (VPMOVZXBQMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBQ256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBQMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMOVSXBD256 x) mask)
	// result: (VPMOVSXBDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMOVZXBD256 x) mask)
	// result: (VPMOVZXBDMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBD256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMOVSXBW256 x) mask)
	// result: (VPMOVSXBWMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBW256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMOVZXBW256 x) mask)
	// result: (VPMOVZXBWMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBW256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VGF2P8AFFINEINVQB256 [a] x y) mask)
	// result: (VGF2P8AFFINEINVQBMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8AFFINEINVQB256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQBMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VGF2P8AFFINEQB256 [a] x y) mask)
	// result: (VGF2P8AFFINEQBMasked256 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8AFFINEQB256 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQBMasked256)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VGF2P8MULB256 x y) mask)
	// result: (VGF2P8MULBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8MULB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8MULBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMAXSB256 x y) mask)
	// result: (VPMAXSBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMAXUB256 x y) mask)
	// result: (VPMAXUBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMINSB256 x y) mask)
	// result: (VPMINSBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPMINUB256 x y) mask)
	// result: (VPMINUBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPOPCNTB256 x) mask)
	// result: (VPOPCNTBMasked256 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTB256 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTBMasked256)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPERMB256 x y) mask)
	// result: (VPERMBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPSHUFB256 x y) mask)
	// result: (VPSHUFBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPSUBB256 x y) mask)
	// result: (VPSUBBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPSUBSB256 x y) mask)
	// result: (VPSUBSBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBSB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBSBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked256 (VPSUBUSB256 x y) mask)
	// result: (VPSUBUSBMasked256 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBUSB256 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBUSBMasked256)
		v.AddArg3(x, y, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQU8Masked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQU8Masked512 (VPABSB512 x) mask)
	// result: (VPABSBMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPABSB512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPABSBMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPADDB512 x y) mask)
	// result: (VPADDBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPADDSB512 x y) mask)
	// result: (VPADDSBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDSB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDSBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPADDUSB512 x y) mask)
	// result: (VPADDUSBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPADDUSB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPADDUSBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPAVGB512 x y) mask)
	// result: (VPAVGBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPAVGB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPAVGBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPERMI2B512 x y z) mask)
	// result: (VPERMI2BMasked512 x y z mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMI2B512 {
			break
		}
		z := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMI2BMasked512)
		v.AddArg4(x, y, z, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPALIGNR512 [a] x y) mask)
	// result: (VPALIGNRMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPALIGNR512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPALIGNRMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMOVSXBQ512 x) mask)
	// result: (VPMOVSXBQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMOVZXBQ512 x) mask)
	// result: (VPMOVZXBQMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBQ512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBQMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMOVSXBW512 x) mask)
	// result: (VPMOVSXBWMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBW512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMOVSXBD512 x) mask)
	// result: (VPMOVSXBDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVSXBD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMOVZXBW512 x) mask)
	// result: (VPMOVZXBWMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBW512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMOVZXBD512 x) mask)
	// result: (VPMOVZXBDMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVZXBD512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VGF2P8AFFINEINVQB512 [a] x y) mask)
	// result: (VGF2P8AFFINEINVQBMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8AFFINEINVQB512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEINVQBMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VGF2P8AFFINEQB512 [a] x y) mask)
	// result: (VGF2P8AFFINEQBMasked512 [a] x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8AFFINEQB512 {
			break
		}
		a := ssa.AuxIntToUint8(v_0.AuxInt)
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8AFFINEQBMasked512)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VGF2P8MULB512 x y) mask)
	// result: (VGF2P8MULBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VGF2P8MULB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VGF2P8MULBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMAXSB512 x y) mask)
	// result: (VPMAXSBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXSB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXSBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMAXUB512 x y) mask)
	// result: (VPMAXUBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMAXUB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMAXUBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMINSB512 x y) mask)
	// result: (VPMINSBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINSB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINSBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPMINUB512 x y) mask)
	// result: (VPMINUBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPMINUB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPMINUBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPOPCNTB512 x) mask)
	// result: (VPOPCNTBMasked512 x mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPOPCNTB512 {
			break
		}
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPOPCNTBMasked512)
		v.AddArg2(x, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPERMB512 x y) mask)
	// result: (VPERMBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPERMB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPERMBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPSHUFB512 x y) mask)
	// result: (VPSHUFBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSHUFB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSHUFBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPSUBB512 x y) mask)
	// result: (VPSUBBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPSUBSB512 x y) mask)
	// result: (VPSUBSBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBSB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBSBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	// match: (VMOVDQU8Masked512 (VPSUBUSB512 x y) mask)
	// result: (VPSUBUSBMasked512 x y mask)
	for {
		if v_0.Op != ssaop.OpAMD64VPSUBUSB512 {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		mask := v_1
		v.Reset(ssaop.OpAMD64VPSUBUSBMasked512)
		v.AddArg3(x, y, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQUload128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQUload128 [off1] {sym} x:(ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (VMOVDQUload128 [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		ptr := x.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload128)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (VMOVDQUload128 [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (VMOVDQUload128 [off1+off2] {ssa.MergeSym(sym1, sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		sym2 := ssa.AuxToSym(x.Aux)
		base := x.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload128)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQUload256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQUload256 [off1] {sym} x:(ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (VMOVDQUload256 [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		ptr := x.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload256)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (VMOVDQUload256 [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (VMOVDQUload256 [off1+off2] {ssa.MergeSym(sym1, sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		sym2 := ssa.AuxToSym(x.Aux)
		base := x.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload256)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQUload512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQUload512 [off1] {sym} x:(ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (VMOVDQUload512 [off1+off2] {sym} ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		ptr := x.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload512)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (VMOVDQUload512 [off1] {sym1} x:(LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (VMOVDQUload512 [off1+off2] {ssa.MergeSym(sym1, sym2)} base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		sym2 := ssa.AuxToSym(x.Aux)
		base := x.Args[0]
		mem := v_1
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload512)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQUstore128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQUstore128 [off1] {sym} x:(ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (VMOVDQUstore128 [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		ptr := x.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore128)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (VMOVDQUstore128 [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (VMOVDQUstore128 [off1+off2] {ssa.MergeSym(sym1, sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		sym2 := ssa.AuxToSym(x.Aux)
		base := x.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore128)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQUstore256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQUstore256 [off1] {sym} x:(ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (VMOVDQUstore256 [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		ptr := x.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore256)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (VMOVDQUstore256 [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (VMOVDQUstore256 [off1+off2] {ssa.MergeSym(sym1, sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		sym2 := ssa.AuxToSym(x.Aux)
		base := x.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore256)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVDQUstore512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMOVDQUstore512 [off1] {sym} x:(ADDQconst [off2] ptr) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (VMOVDQUstore512 [off1+off2] {sym} ptr val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		ptr := x.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore512)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (VMOVDQUstore512 [off1] {sym1} x:(LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (VMOVDQUstore512 [off1+off2] {ssa.MergeSym(sym1, sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		x := v_0
		if x.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(x.AuxInt)
		sym2 := ssa.AuxToSym(x.Aux)
		base := x.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore512)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVQ(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VMOVQ x:(MOVQload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (VMOVQload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVQload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64VMOVQload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVSDf2v(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VMOVSDf2v x:(MOVSDload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (VMOVSDload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVSDload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64VMOVSDload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (VMOVSDf2v x:(MOVSDconst [c] ))
	// result: (VMOVSDconst [c] )
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVSDconst {
			break
		}
		c := ssa.AuxIntToFloat64(x.AuxInt)
		v.Reset(ssaop.OpAMD64VMOVSDconst)
		v.AuxInt = ssa.Float64ToAuxInt(c)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMOVSSf2v(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VMOVSSf2v x:(MOVSSload [off] {sym} ptr mem))
	// cond: x.Uses == 1 && ssa.Clobber(x)
	// result: @x.Block (VMOVSSload <v.Type> [off] {sym} ptr mem)
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVSSload {
			break
		}
		off := ssa.AuxIntToInt32(x.AuxInt)
		sym := ssa.AuxToSym(x.Aux)
		mem := x.Args[1]
		ptr := x.Args[0]
		if !(x.Uses == 1 && ssa.Clobber(x)) {
			break
		}
		b = x.Block
		v0 := b.NewValue0(x.Pos, ssaop.OpAMD64VMOVSSload, v.Type)
		v.CopyOf(v0)
		v0.AuxInt = ssa.Int32ToAuxInt(off)
		v0.Aux = ssa.SymToAux(sym)
		v0.AddArg2(ptr, mem)
		return true
	}
	// match: (VMOVSSf2v x:(MOVSSconst [c] ))
	// result: (VMOVSSconst [c] )
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64MOVSSconst {
			break
		}
		c := ssa.AuxIntToFloat32(x.AuxInt)
		v.Reset(ssaop.OpAMD64VMOVSSconst)
		v.AuxInt = ssa.Float32ToAuxInt(c)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VMULPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPS128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPS128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPS256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPS256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPS512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPS512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPSMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPSMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPSMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPSMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPSMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VMULPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VMULPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VMULPSMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMULPSMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPABSB128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSB128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSB128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSB256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSB256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSB256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSBMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSBMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSBMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSBMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSQ256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSQ512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSW128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSW128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSW128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSW256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPABSW256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSW256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSWMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSWMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPABSWMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPABSWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPABSWMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKSSDW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKSSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKSSDW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKSSDW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKSSDW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKSSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKSSDW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKSSDW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKSSDW512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKSSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKSSDW512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKSSDW512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKSSDWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKSSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKSSDWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKSSDWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKSSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKSSDWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKSSDWMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKSSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKSSDWMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKUSDW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKUSDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKUSDW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKUSDW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKUSDW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKUSDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKUSDW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKUSDW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKUSDW512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKUSDW512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKUSDW512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKUSDW512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKUSDWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKUSDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKUSDWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKUSDWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKUSDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKUSDWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPACKUSDWMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPACKUSDWMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPACKUSDWMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPADDB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDBMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDBMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDBMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDBMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDSB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDSB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDSB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDSB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDSB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDSB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDSBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDSBMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDSBMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDSBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDSBMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDSBMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDSW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDSW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDSW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDSW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDSWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDSWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDSWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDSWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDSWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDSWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDUSB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDUSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDUSB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDUSB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDUSB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDUSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDUSB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDUSB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDUSBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDUSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDUSBMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDUSBMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDUSBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDUSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDUSBMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDUSBMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDUSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDUSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDUSW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDUSW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDUSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDUSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDUSW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDUSW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDUSWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDUSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDUSWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDUSWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDUSWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDUSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDUSWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDUSWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPADDWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPADDWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPADDWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPADDWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPALIGNR128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPALIGNR128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPALIGNR128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPALIGNR128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPALIGNR256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPALIGNR256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPALIGNR256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPALIGNR256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPALIGNRMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPALIGNRMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPALIGNRMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPALIGNRMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPALIGNRMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPALIGNRMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPALIGNRMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPALIGNRMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPAND128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPAND128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x16 (KANDW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPAND128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x8 (KANDB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPAND128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x4 (KANDB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x4 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x4 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x4)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPAND128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x2 (KANDB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x2 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x2 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x2)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPAND128 x (VPMOVMToVec8x16 k))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMOVDQU8Masked128 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x16 {
				continue
			}
			k := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMOVDQU8Masked128)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPAND128 x (VPMOVMToVec16x8 k))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMOVDQU16Masked128 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x8 {
				continue
			}
			k := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMOVDQU16Masked128)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPAND128 x (VPMOVMToVec32x4 k))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMOVDQU32Masked128 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x4 {
				continue
			}
			k := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMOVDQU32Masked128)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPAND128 x (VPMOVMToVec64x2 k))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMOVDQU64Masked128 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x2 {
				continue
			}
			k := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMOVDQU64Masked128)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPAND128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAND128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAND128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAND256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPAND256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x32 (KANDD x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x32 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x32 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x32)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDD, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPAND256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x16 (KANDW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPAND256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x8 (KANDB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPAND256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x4 (KANDB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x4 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x4 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x4)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPAND256 x (VPMOVMToVec8x32 k))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMOVDQU8Masked256 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x32 {
				continue
			}
			k := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMOVDQU8Masked256)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPAND256 x (VPMOVMToVec16x16 k))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMOVDQU16Masked256 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x16 {
				continue
			}
			k := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMOVDQU16Masked256)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPAND256 x (VPMOVMToVec32x8 k))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMOVDQU32Masked256 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x8 {
				continue
			}
			k := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMOVDQU32Masked256)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPAND256 x (VPMOVMToVec64x4 k))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMOVDQU64Masked256 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x4 {
				continue
			}
			k := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VMOVDQU64Masked256)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPAND256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAND256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAND256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPANDD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPANDD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x64 (KANDQ x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDQ, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPANDD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x32 (KANDD x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDD, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPANDD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x16 (KANDW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPANDD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x8 (KANDB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KANDB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPANDD512 x (VPMOVMToVec64x8 k))
	// result: (VMOVDQU64Masked512 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			k := v_1.Args[0]
			v.Reset(ssaop.OpAMD64VMOVDQU64Masked512)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPANDD512 x (VPMOVMToVec32x16 k))
	// result: (VMOVDQU32Masked512 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			k := v_1.Args[0]
			v.Reset(ssaop.OpAMD64VMOVDQU32Masked512)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPANDD512 x (VPMOVMToVec16x32 k))
	// result: (VMOVDQU16Masked512 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
				continue
			}
			k := v_1.Args[0]
			v.Reset(ssaop.OpAMD64VMOVDQU16Masked512)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPANDD512 x (VPMOVMToVec8x64 k))
	// result: (VMOVDQU8Masked512 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
				continue
			}
			k := v_1.Args[0]
			v.Reset(ssaop.OpAMD64VMOVDQU8Masked512)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPANDD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPANDD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPANDDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPANDDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPANDDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPANDDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPANDDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPANDDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPANDN128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDN128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDN128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDN128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDN256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDN256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDN256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDN256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDND512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDND512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDND512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDND512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDNDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDNDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDNDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDNDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDNDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDNDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDNDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDNDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDNDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDNDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDNDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDNDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDNQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDNQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDNQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDNQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDNQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDNQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDNQMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDNQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDNQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDNQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDNQMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDNQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDNQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDNQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDNQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPANDNQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPANDQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDQ512 x (VPMOVMToVec64x8 k))
	// result: (VMOVDQU64Masked512 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			k := v_1.Args[0]
			v.Reset(ssaop.OpAMD64VMOVDQU64Masked512)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPANDQ512 x (VPMOVMToVec32x16 k))
	// result: (VMOVDQU32Masked512 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			k := v_1.Args[0]
			v.Reset(ssaop.OpAMD64VMOVDQU32Masked512)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPANDQ512 x (VPMOVMToVec16x32 k))
	// result: (VMOVDQU16Masked512 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
				continue
			}
			k := v_1.Args[0]
			v.Reset(ssaop.OpAMD64VMOVDQU16Masked512)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPANDQ512 x (VPMOVMToVec8x64 k))
	// result: (VMOVDQU8Masked512 x k)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
				continue
			}
			k := v_1.Args[0]
			v.Reset(ssaop.OpAMD64VMOVDQU8Masked512)
			v.AddArg2(x, k)
			return true
		}
		break
	}
	// match: (VPANDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPANDQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPANDQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPANDQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPANDQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPANDQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPANDQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPANDQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPANDQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPANDQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAVGB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPAVGB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAVGB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAVGB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAVGB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPAVGB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAVGB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAVGB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAVGBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPAVGBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAVGBMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAVGBMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAVGBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPAVGBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAVGBMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAVGBMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAVGW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPAVGW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAVGW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAVGW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAVGW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPAVGW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAVGW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAVGW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAVGWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPAVGWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAVGWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAVGWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPAVGWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPAVGWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPAVGWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPAVGWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPBLENDMBMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBLENDMBMasked512 dst (VGF2P8MULB512 x y) mask)
	// result: (VGF2P8MULBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VGF2P8MULB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VGF2P8MULBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPABSB512 x) mask)
	// result: (VPABSBMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSB512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPABSBMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPADDB512 x y) mask)
	// result: (VPADDBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPADDBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPADDSB512 x y) mask)
	// result: (VPADDSBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDSB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPADDSBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPADDUSB512 x y) mask)
	// result: (VPADDUSBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDUSB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPADDUSBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPAVGB512 x y) mask)
	// result: (VPAVGBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPAVGB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPAVGBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPMAXSB512 x y) mask)
	// result: (VPMAXSBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMAXSBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPMAXUB512 x y) mask)
	// result: (VPMAXUBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMAXUBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPMINSB512 x y) mask)
	// result: (VPMINSBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMINSBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPMINUB512 x y) mask)
	// result: (VPMINUBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMINUBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPOPCNTB512 x) mask)
	// result: (VPOPCNTBMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTB512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPOPCNTBMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPSHUFB512 x y) mask)
	// result: (VPSHUFBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSHUFBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPSUBB512 x y) mask)
	// result: (VPSUBBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSUBBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPSUBSB512 x y) mask)
	// result: (VPSUBSBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBSB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSUBSBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMBMasked512 dst (VPSUBUSB512 x y) mask)
	// result: (VPSUBUSBMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBUSB512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSUBUSBMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBLENDMDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBLENDMDMasked512 dst (VADDPS512 x y) mask)
	// result: (VADDPSMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VADDPS512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VADDPSMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VCVTDQ2PS512 x) mask)
	// result: (VCVTDQ2PSMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTDQ2PS512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VCVTTPS2DQ512 x) mask)
	// result: (VCVTTPS2DQMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2DQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VCVTTPS2UDQ512 x) mask)
	// result: (VCVTTPS2UDQMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2UDQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VCVTUDQ2PS512 x) mask)
	// result: (VCVTUDQ2PSMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUDQ2PS512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VDIVPS512 x y) mask)
	// result: (VDIVPSMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VDIVPS512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VDIVPSMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VMAXPS512 x y) mask)
	// result: (VMAXPSMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMAXPS512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VMAXPSMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VMINPS512 x y) mask)
	// result: (VMINPSMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMINPS512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VMINPSMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VMULPS512 x y) mask)
	// result: (VMULPSMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMULPS512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VMULPSMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPABSD512 x) mask)
	// result: (VPABSDMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPABSDMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPACKSSDW512 x y) mask)
	// result: (VPACKSSDWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPACKSSDW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPACKUSDW512 x y) mask)
	// result: (VPACKUSDWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPACKUSDW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPADDD512 x y) mask)
	// result: (VPADDDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPADDDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPANDD512 x y) mask)
	// result: (VPANDDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPANDD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPANDDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPLZCNTD512 x) mask)
	// result: (VPLZCNTDMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPLZCNTD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMAXSD512 x y) mask)
	// result: (VPMAXSDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMAXSDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMAXUD512 x y) mask)
	// result: (VPMAXUDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMAXUDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMINSD512 x y) mask)
	// result: (VPMINSDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMINSDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMINUD512 x y) mask)
	// result: (VPMINUDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMINUDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMOVDB128_512 x) mask)
	// result: (VPMOVDBMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVDB128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVDBMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMOVDW256 x) mask)
	// result: (VPMOVDWMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVDW256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVDWMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMOVSDB128_512 x) mask)
	// result: (VPMOVSDBMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSDB128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVSDBMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMOVSDW256 x) mask)
	// result: (VPMOVSDWMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSDW256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVSDWMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMOVUSDB128_512 x) mask)
	// result: (VPMOVUSDBMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSDB128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVUSDBMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMOVUSDW256 x) mask)
	// result: (VPMOVUSDWMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSDW256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVUSDWMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPMULLD512 x y) mask)
	// result: (VPMULLDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMULLDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPOPCNTD512 x) mask)
	// result: (VPOPCNTDMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPORD512 x y) mask)
	// result: (VPORDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPORD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPORDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPROLVD512 x y) mask)
	// result: (VPROLVDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPROLVD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPROLVDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPRORVD512 x y) mask)
	// result: (VPRORVDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPRORVD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPRORVDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPSHUFD512 [a] x) mask)
	// result: (VPSHUFDMasked512Merging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFD512 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSHUFDMasked512Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPSLLD512const [a] x) mask)
	// result: (VPSLLDMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLD512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLDMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPSLLVD512 x y) mask)
	// result: (VPSLLVDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLVDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPSRAD512const [a] x) mask)
	// result: (VPSRADMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAD512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRADMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPSRAVD512 x y) mask)
	// result: (VPSRAVDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAVDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPSRLD512const [a] x) mask)
	// result: (VPSRLDMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLD512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLDMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPSRLVD512 x y) mask)
	// result: (VPSRLVDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLVDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPSUBD512 x y) mask)
	// result: (VPSUBDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSUBDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VPXORD512 x y) mask)
	// result: (VPXORDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPXORD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPXORDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VRCP14PS512 x) mask)
	// result: (VRCP14PSMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRCP14PS512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VRCP14PSMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VREDUCEPS512 [a] x) mask)
	// result: (VREDUCEPSMasked512Merging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VREDUCEPS512 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked512Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VRNDSCALEPS512 [a] x) mask)
	// result: (VRNDSCALEPSMasked512Merging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRNDSCALEPS512 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked512Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VRSQRT14PS512 x) mask)
	// result: (VRSQRT14PSMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRSQRT14PS512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VRSQRT14PSMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VSCALEFPS512 x y) mask)
	// result: (VSCALEFPSMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSCALEFPS512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VSQRTPS512 x) mask)
	// result: (VSQRTPSMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSQRTPS512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VSQRTPSMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 dst (VSUBPS512 x y) mask)
	// result: (VSUBPSMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSUBPS512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VSUBPSMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBLENDMDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBLENDMDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBLENDMQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBLENDMQMasked512 dst (VADDPD512 x y) mask)
	// result: (VADDPDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VADDPD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VADDPDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTPD2PS256 x) mask)
	// result: (VCVTPD2PSMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTPD2PS256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTPD2PSMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTQQ2PD512 x) mask)
	// result: (VCVTQQ2PDMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTQQ2PD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTQQ2PS256 x) mask)
	// result: (VCVTQQ2PSMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTQQ2PS256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTQQ2PSMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTTPD2DQ256 x) mask)
	// result: (VCVTTPD2DQMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2DQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTTPD2DQMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTTPD2QQ512 x) mask)
	// result: (VCVTTPD2QQMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2QQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTTPD2UDQ256 x) mask)
	// result: (VCVTTPD2UDQMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2UDQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTTPD2UQQ512 x) mask)
	// result: (VCVTTPD2UQQMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2UQQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTUQQ2PD512 x) mask)
	// result: (VCVTUQQ2PDMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUQQ2PD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VCVTUQQ2PS256 x) mask)
	// result: (VCVTUQQ2PSMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUQQ2PS256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VDIVPD512 x y) mask)
	// result: (VDIVPDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VDIVPD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VDIVPDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VMAXPD512 x y) mask)
	// result: (VMAXPDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMAXPD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VMAXPDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VMINPD512 x y) mask)
	// result: (VMINPDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMINPD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VMINPDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VMULPD512 x y) mask)
	// result: (VMULPDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMULPD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VMULPDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPABSQ512 x) mask)
	// result: (VPABSQMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPABSQMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPADDQ512 x y) mask)
	// result: (VPADDQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPADDQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPANDQ512 x y) mask)
	// result: (VPANDQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPANDQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPANDQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPLZCNTQ512 x) mask)
	// result: (VPLZCNTQMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPLZCNTQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMAXSQ512 x y) mask)
	// result: (VPMAXSQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMAXSQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMAXUQ512 x y) mask)
	// result: (VPMAXUQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMAXUQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMINSQ512 x y) mask)
	// result: (VPMINSQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMINSQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMINUQ512 x y) mask)
	// result: (VPMINUQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMINUQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVQB128_512 x) mask)
	// result: (VPMOVQBMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQB128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVQBMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVQD256 x) mask)
	// result: (VPMOVQDMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVQDMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVQW128_512 x) mask)
	// result: (VPMOVQWMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQW128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVQWMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVSQB128_512 x) mask)
	// result: (VPMOVSQBMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQB128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVSQBMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVSQD256 x) mask)
	// result: (VPMOVSQDMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVSQDMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVSQW128_512 x) mask)
	// result: (VPMOVSQWMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQW128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVSQWMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVUSQB128_512 x) mask)
	// result: (VPMOVUSQBMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQB128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVUSQBMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVUSQD256 x) mask)
	// result: (VPMOVUSQDMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVUSQDMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMOVUSQW128_512 x) mask)
	// result: (VPMOVUSQWMasked128_512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQW128_512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVUSQWMasked128_512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPMULLQ512 x y) mask)
	// result: (VPMULLQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMULLQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPOPCNTQ512 x) mask)
	// result: (VPOPCNTQMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPORQ512 x y) mask)
	// result: (VPORQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPORQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPORQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPROLVQ512 x y) mask)
	// result: (VPROLVQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPROLVQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPROLVQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPRORVQ512 x y) mask)
	// result: (VPRORVQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPRORVQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPRORVQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPSLLQ512const [a] x) mask)
	// result: (VPSLLQMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLQ512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLQMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPSLLVQ512 x y) mask)
	// result: (VPSLLVQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLVQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPSRAQ512const [a] x) mask)
	// result: (VPSRAQMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAQ512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAQMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPSRAVQ512 x y) mask)
	// result: (VPSRAVQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAVQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPSRLQ512const [a] x) mask)
	// result: (VPSRLQMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLQ512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLQMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPSRLVQ512 x y) mask)
	// result: (VPSRLVQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLVQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPSUBQ512 x y) mask)
	// result: (VPSUBQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSUBQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VPXORQ512 x y) mask)
	// result: (VPXORQMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPXORQ512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPXORQMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VRCP14PD512 x) mask)
	// result: (VRCP14PDMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRCP14PD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VRCP14PDMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VREDUCEPD512 [a] x) mask)
	// result: (VREDUCEPDMasked512Merging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VREDUCEPD512 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked512Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VRNDSCALEPD512 [a] x) mask)
	// result: (VRNDSCALEPDMasked512Merging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRNDSCALEPD512 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked512Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VRSQRT14PD512 x) mask)
	// result: (VRSQRT14PDMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRSQRT14PD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VSCALEFPD512 x y) mask)
	// result: (VSCALEFPDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSCALEFPD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VSQRTPD512 x) mask)
	// result: (VSQRTPDMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSQRTPD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VSQRTPDMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 dst (VSUBPD512 x y) mask)
	// result: (VSUBPDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSUBPD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VSUBPDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBLENDMQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBLENDMQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBLENDMWMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBLENDMWMasked512 dst (VPABSW512 x) mask)
	// result: (VPABSWMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSW512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPABSWMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPADDSW512 x y) mask)
	// result: (VPADDSWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDSW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPADDSWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPADDUSW512 x y) mask)
	// result: (VPADDUSWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDUSW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPADDUSWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPADDW512 x y) mask)
	// result: (VPADDWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPADDWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPAVGW512 x y) mask)
	// result: (VPAVGWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPAVGW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPAVGWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMADDUBSW512 x y) mask)
	// result: (VPMADDUBSWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMADDUBSW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMADDUBSWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMADDWD512 x y) mask)
	// result: (VPMADDWDMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMADDWD512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMADDWDMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMAXSW512 x y) mask)
	// result: (VPMAXSWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMAXSWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMAXUW512 x y) mask)
	// result: (VPMAXUWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMAXUWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMINSW512 x y) mask)
	// result: (VPMINSWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMINSWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMINUW512 x y) mask)
	// result: (VPMINUWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMINUWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMOVSWB256 x) mask)
	// result: (VPMOVSWBMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSWB256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVSWBMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMOVUSWB256 x) mask)
	// result: (VPMOVUSWBMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSWB256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVUSWBMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMOVWB256 x) mask)
	// result: (VPMOVWBMasked256Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVWB256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMOVWBMasked256Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMULHUW512 x y) mask)
	// result: (VPMULHUWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULHUW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMULHUWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMULHW512 x y) mask)
	// result: (VPMULHWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULHW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMULHWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPMULLW512 x y) mask)
	// result: (VPMULLWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPMULLWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPOPCNTW512 x) mask)
	// result: (VPOPCNTWMasked512Merging dst x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTW512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPOPCNTWMasked512Merging)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSHUFHW512 [a] x) mask)
	// result: (VPSHUFHWMasked512Merging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFHW512 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSHUFHWMasked512Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSHUFLW512 [a] x) mask)
	// result: (VPSHUFLWMasked512Merging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFLW512 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSHUFLWMasked512Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSLLVW512 x y) mask)
	// result: (VPSLLVWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLVWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSLLW512const [a] x) mask)
	// result: (VPSLLWMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLW512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLWMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSRAVW512 x y) mask)
	// result: (VPSRAVWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAVWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSRAW512const [a] x) mask)
	// result: (VPSRAWMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAW512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAWMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSRLVW512 x y) mask)
	// result: (VPSRLVWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLVWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSRLW512const [a] x) mask)
	// result: (VPSRLWMasked512constMerging dst [a] x mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLW512const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLWMasked512constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v.AddArg3(dst, x, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSUBSW512 x y) mask)
	// result: (VPSUBSWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBSW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSUBSWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSUBUSW512 x y) mask)
	// result: (VPSUBUSWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBUSW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSUBUSWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	// match: (VPBLENDMWMasked512 dst (VPSUBW512 x y) mask)
	// result: (VPSUBWMasked512Merging dst x y mask)
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBW512 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSUBWMasked512Merging)
		v.AddArg4(dst, x, y, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBLENDVB128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (VPBLENDVB128 dst (VADDPD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VADDPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VADDPD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VADDPDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VADDPS128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VADDPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VADDPS128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VADDPSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VBROADCASTSD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VBROADCASTSDMasked256Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VBROADCASTSD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VBROADCASTSD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VBROADCASTSDMasked512Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VBROADCASTSD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VBROADCASTSS128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VBROADCASTSSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VBROADCASTSS128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VBROADCASTSS256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VBROADCASTSSMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VBROADCASTSS256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VBROADCASTSS512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VBROADCASTSSMasked512Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VBROADCASTSS512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTDQ2PD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTDQ2PD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTDQ2PS128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTDQ2PS128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTPD2PSX128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTPD2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTPD2PSX128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPD2PSXMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTPS2PD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTPS2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTPS2PD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPS2PDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTQQ2PD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTQQ2PD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTQQ2PSX128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTQQ2PSX128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PSXMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTTPD2DQX128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPD2DQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2DQX128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2DQXMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTTPD2QQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPD2QQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2QQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTTPD2UDQX128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPD2UDQXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2UDQX128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQXMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTTPD2UQQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPD2UQQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2UQQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTTPS2DQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPS2DQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2DQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTTPS2QQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPS2QQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2QQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2QQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTTPS2UDQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPS2UDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2UDQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTTPS2UQQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPS2UQQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2UQQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UQQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTUDQ2PD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTUDQ2PDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUDQ2PD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTUDQ2PS128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTUDQ2PSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUDQ2PS128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTUQQ2PD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTUQQ2PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUQQ2PD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VCVTUQQ2PSX128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTUQQ2PSXMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUQQ2PSX128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSXMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VDIVPD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VDIVPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VDIVPD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VDIVPS128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VDIVPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VDIVPS128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VGF2P8MULB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VGF2P8MULBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VGF2P8MULB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8MULBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VMAXPD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMAXPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMAXPD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMAXPDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VMAXPS128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMAXPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMAXPS128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMAXPSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VMINPD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMINPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMINPD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMINPDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VMINPS128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMINPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMINPS128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMINPSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VMULPD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMULPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMULPD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMULPDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VMULPS128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMULPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMULPS128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMULPSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPABSB128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPABSBMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSB128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPABSD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPABSDMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPABSQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPABSQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPABSW128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPABSWMasked128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSW128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPACKSSDW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPACKSSDWMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPACKSSDW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPACKUSDW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPACKUSDWMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPACKUSDW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPADDB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPADDD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPADDQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPADDSB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDSBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDSB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDSBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPADDSW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDSWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDSW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDSWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPADDUSB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDUSBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDUSB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDUSBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPADDUSW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDUSWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDUSW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDUSWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPADDW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPAVGB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPAVGBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPAVGB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPAVGBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPAVGW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPAVGWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPAVGW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPAVGWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTB128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTBMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTB128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTB256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTBMasked256Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTB256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTB512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTBMasked512Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTB512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTDMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTDMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTDMasked512Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTQMasked256Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTQMasked512Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTW128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTWMasked128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTW128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTW256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTWMasked256Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTW256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPBROADCASTW512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPBROADCASTWMasked512Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPBROADCASTW512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPLZCNTD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPLZCNTDMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPLZCNTD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPLZCNTQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPLZCNTQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPLZCNTQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMADDUBSW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMADDUBSWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMADDUBSW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDUBSWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMADDWD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMADDWDMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMADDWD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDWDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMAXSB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXSBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXSBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMAXSD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXSDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXSDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMAXSQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXSQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXSQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMAXSW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXSWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXSWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMAXUB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXUBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXUBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMAXUD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXUDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXUDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMAXUQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXUQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXUQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMAXUW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXUWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXUWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMINSB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINSBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINSBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMINSD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINSDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINSDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMINSQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINSQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINSQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMINSW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINSWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINSWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMINUB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINUBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINUBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMINUD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINUDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINUDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMINUQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINUQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINUQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMINUW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINUWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINUWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVDB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVDBMasked128_128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVDB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVDBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVDW128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVDWMasked128_128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVDW128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVDWMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVQB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVQBMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVQBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVQD128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVQDMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQD128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVQDMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVQW128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVQWMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQW128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVQWMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSDB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSDBMasked128_128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSDB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSDBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSDW128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSDWMasked128_128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSDW128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSDWMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSQB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSQBMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSQBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSQD128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSQDMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQD128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSQDMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSQW128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSQWMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQW128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSQWMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSWB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSWBMasked128_128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSWB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSWBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXBD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBDMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXBD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBDMasked256Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXBD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBDMasked512Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXBQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBQMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXBQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBQMasked256Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXBQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBQMasked512Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXBW128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBWMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBW128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXBW256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBWMasked256Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBW256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXDQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXDQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXDQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXDQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXDQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXWD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXWDMasked128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXWD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXWD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXWDMasked256Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXWD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXWQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXWQMasked128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXWQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXWQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXWQMasked256Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXWQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVSXWQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXWQMasked512Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXWQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVUSDB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSDBMasked128_128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSDB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSDBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVUSDW128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSDWMasked128_128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSDW128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSDWMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVUSQB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSQBMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSQBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVUSQD128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSQDMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQD128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSQDMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVUSQW128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSQWMasked128_128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQW128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSQWMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVUSWB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSWBMasked128_128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSWB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSWBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVWB128_128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVWBMasked128_128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVWB128_128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVWBMasked128_128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXBD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBDMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXBD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBDMasked256Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXBD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBDMasked512Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXBQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBQMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXBQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBQMasked256Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXBQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBQMasked512Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXBW128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBWMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBW128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXBW256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBWMasked256Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBW256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXDQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXDQMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXDQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXDQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXDQMasked256Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXDQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXWD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXWDMasked128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXWD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXWD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXWDMasked256Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXWD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXWQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXWQMasked128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXWQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXWQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXWQMasked256Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXWQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMOVZXWQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXWQMasked512Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXWQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMULHUW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULHUWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULHUW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULHUWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMULHW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULHWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULHW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULHWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMULLD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULLDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULLDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMULLQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULLQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULLQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPMULLW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULLWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULLWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPOPCNTB128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPOPCNTBMasked128Merging dst x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTB128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPOPCNTD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPOPCNTDMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPOPCNTQ128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPOPCNTQMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTQ128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPOPCNTW128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPOPCNTWMasked128Merging dst x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTW128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPROLVD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPROLVDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPROLVD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPROLVQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPROLVQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPROLVQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPRORVD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPRORVDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPRORVD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPRORVQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPRORVQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPRORVQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSHUFB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSHUFBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSHUFD128 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSHUFDMasked128Merging dst [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFD128 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFDMasked128Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSHUFHW128 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSHUFHWMasked128Merging dst [a] x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFHW128 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFHWMasked128Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSHUFLW128 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSHUFLWMasked128Merging dst [a] x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFLW128 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFLWMasked128Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSLLD128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLDMasked128constMerging dst [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLD128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLDMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSLLQ128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLQMasked128constMerging dst [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLQ128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLQMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSLLVD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLVDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSLLVQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLVQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSLLVW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLVWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSLLW128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLWMasked128constMerging dst [a] x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLW128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLWMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRAD128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRADMasked128constMerging dst [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAD128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRADMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRAQ128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAQMasked128constMerging dst [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAQ128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAQMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRAVD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAVDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRAVQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAVQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRAVW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAVWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRAW128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAWMasked128constMerging dst [a] x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAW128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAWMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRLD128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLDMasked128constMerging dst [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLD128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLDMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRLQ128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLQMasked128constMerging dst [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLQ128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLQMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRLVD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLVDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRLVQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLVQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRLVW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLVWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSRLW128const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLWMasked128constMerging dst [a] x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLW128const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLWMasked128constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSUBB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSUBD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBDMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSUBQ128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBQMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBQ128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBQMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSUBSB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBSBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBSB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSUBSW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBSWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBSW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSUBUSB128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBUSBMasked128Merging dst x y (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBUSB128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSBMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSUBUSW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBUSWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBUSW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VPSUBW128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBWMasked128Merging dst x y (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBW128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBWMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VRCP14PD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VRCP14PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRCP14PD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VREDUCEPD128 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VREDUCEPDMasked128Merging dst [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VREDUCEPD128 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked128Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VREDUCEPS128 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VREDUCEPSMasked128Merging dst [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VREDUCEPS128 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked128Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VRNDSCALEPD128 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VRNDSCALEPDMasked128Merging dst [a] x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRNDSCALEPD128 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked128Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VRNDSCALEPS128 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VRNDSCALEPSMasked128Merging dst [a] x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRNDSCALEPS128 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked128Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VRSQRT14PD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VRSQRT14PDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRSQRT14PD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VSCALEFPD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSCALEFPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSCALEFPD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VSCALEFPS128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSCALEFPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSCALEFPS128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VSQRTPD128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSQRTPDMasked128Merging dst x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSQRTPD128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VSQRTPS128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSQRTPSMasked128Merging dst x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSQRTPS128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VSUBPD128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSUBPDMasked128Merging dst x y (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSUBPD128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPDMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB128 dst (VSUBPS128 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSUBPSMasked128Merging dst x y (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSUBPS128 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPSMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBLENDVB256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (VPBLENDVB256 dst (VADDPD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VADDPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VADDPD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VADDPDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VADDPS256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VADDPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VADDPS256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VADDPSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTDQ2PD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTDQ2PD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTDQ2PS256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTDQ2PS256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTDQ2PSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTPD2PSY128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTPD2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTPD2PSY128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPD2PSYMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTPS2PD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTPS2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTPS2PD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTPS2PDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTQQ2PD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTQQ2PD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTQQ2PSY128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTQQ2PSY128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTQQ2PSYMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTTPD2DQY128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPD2DQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2DQY128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2DQYMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTTPD2QQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPD2QQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2QQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2QQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTTPD2UDQY128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPD2UDQYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2UDQY128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UDQYMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTTPD2UQQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPD2UQQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPD2UQQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPD2UQQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTTPS2DQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPS2DQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2DQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2DQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTTPS2QQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPS2QQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2QQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2QQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTTPS2UDQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPS2UDQMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2UDQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UDQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTTPS2UQQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTTPS2UQQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTTPS2UQQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTTPS2UQQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTUDQ2PD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTUDQ2PDMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUDQ2PD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTUDQ2PS256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTUDQ2PSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUDQ2PS256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUDQ2PSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTUQQ2PD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTUQQ2PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUQQ2PD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VCVTUQQ2PSY128 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VCVTUQQ2PSYMasked128Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VCVTUQQ2PSY128 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VCVTUQQ2PSYMasked128Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VDIVPD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VDIVPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VDIVPD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VDIVPS256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VDIVPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VDIVPS256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VDIVPSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VGF2P8MULB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VGF2P8MULBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VGF2P8MULB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VGF2P8MULBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VMAXPD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMAXPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMAXPD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMAXPDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VMAXPS256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMAXPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMAXPS256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMAXPSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VMINPD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMINPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMINPD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMINPDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VMINPS256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMINPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMINPS256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMINPSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VMULPD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMULPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMULPD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMULPDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VMULPS256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VMULPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VMULPS256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VMULPSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPABSB256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPABSBMasked256Merging dst x (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSB256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPABSD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPABSDMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPABSQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPABSQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPABSW256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPABSWMasked256Merging dst x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPABSW256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPABSWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPACKSSDW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPACKSSDWMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPACKSSDW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKSSDWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPACKUSDW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPACKUSDWMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPACKUSDW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPACKUSDWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPADDB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPADDD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPADDQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPADDSB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDSBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDSB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDSBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPADDSW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDSWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDSW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDSWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPADDUSB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDUSBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDUSB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDUSBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPADDUSW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDUSWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDUSW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDUSWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPADDW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPADDWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPADDW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPADDWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPAVGB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPAVGBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPAVGB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPAVGBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPAVGW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPAVGWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPAVGW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPAVGWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPLZCNTD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPLZCNTDMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPLZCNTD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPLZCNTQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPLZCNTQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPLZCNTQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMADDUBSW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMADDUBSWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMADDUBSW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDUBSWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMADDWD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMADDWDMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMADDWD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDWDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMAXSB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXSBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXSBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMAXSD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXSDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXSDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMAXSQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXSQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXSQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMAXSW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXSWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXSW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXSWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMAXUB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXUBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXUBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMAXUD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXUDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXUDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMAXUQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXUQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXUQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMAXUW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMAXUWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMAXUW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMAXUWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMINSB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINSBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINSBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMINSD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINSDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINSDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMINSQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINSQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINSQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMINSW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINSWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINSW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINSWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMINUB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINUBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINUBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMINUD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINUDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINUDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMINUQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINUQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINUQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMINUW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMINUWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMINUW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMINUWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVDB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVDBMasked128_256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVDB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVDBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVDW128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVDWMasked128_256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVDW128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVDWMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVQB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVQBMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVQBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVQD128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVQDMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQD128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVQDMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVQW128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVQWMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVQW128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVQWMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSDB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSDBMasked128_256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSDB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSDBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSDW128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSDWMasked128_256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSDW128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSDWMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSQB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSQBMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSQBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSQD128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSQDMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQD128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSQDMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSQW128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSQWMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSQW128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSQWMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSWB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSWBMasked128_256Merging dst x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSWB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSWBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSXBW512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXBWMasked512Merging dst x (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXBW512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSXDQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXDQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXDQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVSXWD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVSXWDMasked512Merging dst x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVSXWD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVUSDB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSDBMasked128_256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSDB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSDBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVUSDW128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSDWMasked128_256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSDW128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSDWMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVUSQB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSQBMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSQBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVUSQD128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSQDMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQD128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSQDMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVUSQW128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSQWMasked128_256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSQW128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSQWMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVUSWB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVUSWBMasked128_256Merging dst x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVUSWB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVUSWBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVWB128_256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVWBMasked128_256Merging dst x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVWB128_256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVWBMasked128_256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVZXBW512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXBWMasked512Merging dst x (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXBW512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVZXDQ512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXDQMasked512Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXDQ512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMOVZXWD512 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVZXWDMasked512Merging dst x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMOVZXWD512 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked512Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMULHUW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULHUWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULHUW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULHUWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMULHW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULHWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULHW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULHWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMULLD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULLDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULLDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMULLQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULLQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULLQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPMULLW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMULLWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPMULLW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMULLWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPOPCNTB256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPOPCNTBMasked256Merging dst x (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTB256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPOPCNTD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPOPCNTDMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPOPCNTQ256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPOPCNTQMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTQ256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPOPCNTW256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPOPCNTWMasked256Merging dst x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPOPCNTW256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPROLVD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPROLVDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPROLVD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPROLVQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPROLVQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPROLVQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPRORVD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPRORVDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPRORVD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPRORVQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPRORVQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPRORVQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSHUFB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSHUFBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSHUFD256 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSHUFDMasked256Merging dst [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFD256 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFDMasked256Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSHUFHW256 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSHUFHWMasked256Merging dst [a] x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFHW256 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFHWMasked256Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSHUFLW256 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSHUFLWMasked256Merging dst [a] x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSHUFLW256 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFLWMasked256Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSLLD256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLDMasked256constMerging dst [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLD256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLDMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSLLQ256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLQMasked256constMerging dst [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLQ256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLQMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSLLVD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLVDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSLLVQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLVQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSLLVW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLVWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLVW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSLLW256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSLLWMasked256constMerging dst [a] x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSLLW256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLWMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRAD256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRADMasked256constMerging dst [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAD256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRADMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRAQ256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAQMasked256constMerging dst [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAQ256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAQMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRAVD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAVDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRAVQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAVQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRAVW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAVWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAVW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRAW256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRAWMasked256constMerging dst [a] x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRAW256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAWMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRLD256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLDMasked256constMerging dst [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLD256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLDMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRLQ256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLQMasked256constMerging dst [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLQ256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLQMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRLVD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLVDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRLVQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLVQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRLVW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLVWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLVW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSRLW256const [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSRLWMasked256constMerging dst [a] x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSRLW256const {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLWMasked256constMerging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSUBB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSUBD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBDMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSUBQ256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBQMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBQ256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBQMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSUBSB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBSBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBSB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSUBSW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBSWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBSW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSUBUSB256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBUSBMasked256Merging dst x y (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBUSB256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSBMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSUBUSW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBUSWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBUSW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VPSUBW256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPSUBWMasked256Merging dst x y (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VPSUBW256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBWMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VRCP14PD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VRCP14PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRCP14PD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VREDUCEPD256 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VREDUCEPDMasked256Merging dst [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VREDUCEPD256 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked256Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VREDUCEPS256 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VREDUCEPSMasked256Merging dst [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VREDUCEPS256 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked256Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VRNDSCALEPD256 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VRNDSCALEPDMasked256Merging dst [a] x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRNDSCALEPD256 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked256Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VRNDSCALEPS256 [a] x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VRNDSCALEPSMasked256Merging dst [a] x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRNDSCALEPS256 {
			break
		}
		a := ssa.AuxIntToUint8(v_1.AuxInt)
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked256Merging)
		v.AuxInt = ssa.Uint8ToAuxInt(a)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VRSQRT14PD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VRSQRT14PDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VRSQRT14PD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VSCALEFPD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSCALEFPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSCALEFPD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VSCALEFPS256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSCALEFPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSCALEFPS256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VSQRTPD256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSQRTPDMasked256Merging dst x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSQRTPD256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VSQRTPS256 x) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSQRTPSMasked256Merging dst x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSQRTPS256 {
			break
		}
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(dst, x, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VSUBPD256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSUBPDMasked256Merging dst x y (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSUBPD256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPDMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	// match: (VPBLENDVB256 dst (VSUBPS256 x y) mask)
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VSUBPSMasked256Merging dst x y (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		dst := v_0
		if v_1.Op != ssaop.OpAMD64VSUBPS256 {
			break
		}
		y := v_1.Args[1]
		x := v_1.Args[0]
		mask := v_2
		if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPSMasked256Merging)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(dst, x, y, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTB128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VPBROADCASTB128 x:(VPINSRB128 [0] (Zero128 <t>) y))
	// cond: x.Uses == 1
	// result: (VPBROADCASTB128 (VMOVQ <types.TypeVec128> y))
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64VPINSRB128 || ssa.AuxIntToUint8(x.AuxInt) != 0 {
			break
		}
		y := x.Args[1]
		x_0 := x.Args[0]
		if x_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTB128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VMOVQ, types.TypeVec128)
		v0.AddArg(y)
		v.AddArg(v0)
		return true
	}
	// match: (VPBROADCASTB128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTB128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTB256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VPBROADCASTB256 x:(VPINSRB128 [0] (Zero128 <t>) y))
	// cond: x.Uses == 1
	// result: (VPBROADCASTB256 (VMOVQ <types.TypeVec128> y))
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64VPINSRB128 || ssa.AuxIntToUint8(x.AuxInt) != 0 {
			break
		}
		y := x.Args[1]
		x_0 := x.Args[0]
		if x_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTB256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VMOVQ, types.TypeVec128)
		v0.AddArg(y)
		v.AddArg(v0)
		return true
	}
	// match: (VPBROADCASTB256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTB256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTB512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VPBROADCASTB512 x:(VPINSRB128 [0] (Zero128 <t>) y))
	// cond: x.Uses == 1
	// result: (VPBROADCASTB512 (VMOVQ <types.TypeVec128> y))
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64VPINSRB128 || ssa.AuxIntToUint8(x.AuxInt) != 0 {
			break
		}
		y := x.Args[1]
		x_0 := x.Args[0]
		if x_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTB512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VMOVQ, types.TypeVec128)
		v0.AddArg(y)
		v.AddArg(v0)
		return true
	}
	// match: (VPBROADCASTB512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTB512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTB512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTBMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTBMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTBMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTBMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTBMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTBMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTBMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTBMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPBROADCASTD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPBROADCASTD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPBROADCASTD512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPBROADCASTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPBROADCASTQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPBROADCASTQ512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPBROADCASTQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTW128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VPBROADCASTW128 x:(VPINSRW128 [0] (Zero128 <t>) y))
	// cond: x.Uses == 1
	// result: (VPBROADCASTW128 (VMOVQ <types.TypeVec128> y))
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64VPINSRW128 || ssa.AuxIntToUint8(x.AuxInt) != 0 {
			break
		}
		y := x.Args[1]
		x_0 := x.Args[0]
		if x_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTW128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VMOVQ, types.TypeVec128)
		v0.AddArg(y)
		v.AddArg(v0)
		return true
	}
	// match: (VPBROADCASTW128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTW128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTW256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VPBROADCASTW256 x:(VPINSRW128 [0] (Zero128 <t>) y))
	// cond: x.Uses == 1
	// result: (VPBROADCASTW256 (VMOVQ <types.TypeVec128> y))
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64VPINSRW128 || ssa.AuxIntToUint8(x.AuxInt) != 0 {
			break
		}
		y := x.Args[1]
		x_0 := x.Args[0]
		if x_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTW256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VMOVQ, types.TypeVec128)
		v0.AddArg(y)
		v.AddArg(v0)
		return true
	}
	// match: (VPBROADCASTW256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPBROADCASTW256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPBROADCASTW512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (VPBROADCASTW512 x:(VPINSRW128 [0] (Zero128 <t>) y))
	// cond: x.Uses == 1
	// result: (VPBROADCASTW512 (VMOVQ <types.TypeVec128> y))
	for {
		x := v_0
		if x.Op != ssaop.OpAMD64VPINSRW128 || ssa.AuxIntToUint8(x.AuxInt) != 0 {
			break
		}
		y := x.Args[1]
		x_0 := x.Args[0]
		if x_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		if !(x.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64VPBROADCASTW512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VMOVQ, types.TypeVec128)
		v0.AddArg(y)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCLMULQDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCLMULQDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCLMULQDQ128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCLMULQDQ128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCLMULQDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCLMULQDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCLMULQDQ256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCLMULQDQ256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPBMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPBMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPBMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPBMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPEQW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPEQW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPEQW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPCMPEQW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTB128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTB256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPGTW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPGTW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPGTW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPGTW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPQ512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPQ512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPQMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPQMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPQMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPQMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPQMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPQMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUBMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUBMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUBMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUBMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUBMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUBMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUQ512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUQ512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUQMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUQMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUQMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUQMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUQMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUQMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUWMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUWMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPUWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPUWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPUWMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPUWMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPWMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPWMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPCMPWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPCMPWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPCMPWMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPCMPWMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPDPWSSD128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPDPWSSD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPDPWSSD128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPDPWSSD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPDPWSSD256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPDPWSSD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPDPWSSD256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPDPWSSD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPDPWSSD512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPDPWSSD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPDPWSSD512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPDPWSSD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPDPWSSDMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPDPWSSDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPDPWSSDMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPDPWSSDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPDPWSSDMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPDPWSSDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPDPWSSDMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPDPWSSDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPDPWSSDMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPDPWSSDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPDPWSSDMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPDPWSSDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERM2F128256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERM2F128256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERM2F128256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERM2F128256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERM2I128256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERM2I128256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERM2I128256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERM2I128256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMB128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMB256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMBMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMBMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2B128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2B128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2B128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2B128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2B256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2B256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2B256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2B256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2BMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2BMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2BMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2BMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2BMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2BMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2BMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2BMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2D128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2D128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2D128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2D128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2D256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2D256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2D256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2D256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2D512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2D512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2D512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2D512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2DMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2DMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2DMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2DMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2DMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2DMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2DMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2DMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2DMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2DMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2DMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2DMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PD128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PD128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PD256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PD256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PD512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PD512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PDMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PDMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PDMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PDMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PDMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PDMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PS128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PS128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PS128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PS256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PS256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PS256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PS512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PS512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PS512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PSMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PSMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PSMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PSMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PSMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PSMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2PSMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2PSMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2PSMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2PSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2Q128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2Q128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2Q128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2Q128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2Q256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2Q256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2Q256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2Q256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2Q512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2Q512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2Q512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2Q512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2QMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2QMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2QMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2QMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2QMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2QMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2QMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2QMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2QMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2QMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2QMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2QMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2W128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2W128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2W128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2W128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2W256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2W256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2W256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2W256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2WMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2WMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2WMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2WMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMI2WMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMI2WMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMI2WMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMI2WMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMPD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMPD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMPD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMPD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMPDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMPDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMPDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMPDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMPS256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMPS512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMPS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMPSMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMPSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMPSMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMPSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMQMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPERMWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPERMWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPERMWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPERMWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPEXPANDBMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPEXPANDBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPEXPANDBMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPEXPANDBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPEXPANDBMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPEXPANDBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPEXPANDBMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPEXPANDBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPEXPANDDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPEXPANDDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPEXPANDDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPEXPANDDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPEXPANDDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPEXPANDDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPEXPANDDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPEXPANDDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPEXPANDQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPEXPANDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPEXPANDQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPEXPANDQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPEXPANDQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPEXPANDQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPEXPANDQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPEXPANDQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPEXPANDWMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPEXPANDWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPEXPANDWMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPEXPANDWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPEXPANDWMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPEXPANDWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPEXPANDWMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPEXPANDWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHADDD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHADDD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHADDD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHADDD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHADDD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHADDD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHADDD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHADDD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHADDSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHADDSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHADDSW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHADDSW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHADDSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHADDSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHADDSW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHADDSW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHADDW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHADDW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHADDW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHADDW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHADDW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHADDW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHADDW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHADDW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHSUBD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHSUBD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHSUBD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHSUBD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHSUBD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHSUBD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHSUBSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHSUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHSUBSW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHSUBSW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHSUBSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHSUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHSUBSW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHSUBSW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHSUBW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHSUBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHSUBW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHSUBW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPHSUBW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPHSUBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPHSUBW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPHSUBW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPINSRD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPINSRD128 [0] (Zero128 <t>) y)
	// cond: y.Type.IsFloat()
	// result: (VMOVSSf2v <types.TypeVec128> y)
	for {
		if ssa.AuxIntToUint8(v.AuxInt) != 0 || v_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		y := v_1
		if !(y.Type.IsFloat()) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVSSf2v)
		v.Type = types.TypeVec128
		v.AddArg(y)
		return true
	}
	// match: (VPINSRD128 [0] (Zero128 <t>) y)
	// cond: !y.Type.IsFloat()
	// result: (VMOVD <types.TypeVec128> y)
	for {
		if ssa.AuxIntToUint8(v.AuxInt) != 0 || v_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		y := v_1
		if !(!y.Type.IsFloat()) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVD)
		v.Type = types.TypeVec128
		v.AddArg(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPINSRQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPINSRQ128 [0] (Zero128 <t>) y)
	// cond: y.Type.IsFloat()
	// result: (VMOVSDf2v <types.TypeVec128> y)
	for {
		if ssa.AuxIntToUint8(v.AuxInt) != 0 || v_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		y := v_1
		if !(y.Type.IsFloat()) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVSDf2v)
		v.Type = types.TypeVec128
		v.AddArg(y)
		return true
	}
	// match: (VPINSRQ128 [0] (Zero128 <t>) y)
	// cond: !y.Type.IsFloat()
	// result: (VMOVQ <types.TypeVec128> y)
	for {
		if ssa.AuxIntToUint8(v.AuxInt) != 0 || v_0.Op != ssaop.OpAMD64Zero128 {
			break
		}
		y := v_1
		if !(!y.Type.IsFloat()) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVQ)
		v.Type = types.TypeVec128
		v.AddArg(y)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPLZCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPLZCNTD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPLZCNTD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPLZCNTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPLZCNTDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPLZCNTDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPLZCNTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPLZCNTQ256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPLZCNTQ512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPLZCNTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPLZCNTQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPLZCNTQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPLZCNTQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPLZCNTQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPLZCNTQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMADDUBSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMADDUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMADDUBSW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDUBSW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMADDUBSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMADDUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMADDUBSW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDUBSW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMADDUBSWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMADDUBSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMADDUBSWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDUBSWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMADDUBSWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMADDUBSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMADDUBSWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDUBSWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMADDWD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMADDWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMADDWD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDWD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMADDWD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMADDWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMADDWD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDWD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMADDWDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMADDWDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMADDWDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDWDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMADDWDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMADDWDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMADDWDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMADDWDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSBMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSBMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSBMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSBMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXSWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXSWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXSWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUBMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUBMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUBMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUBMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMAXUWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMAXUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMAXUWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMAXUWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSBMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSBMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSBMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSBMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINSWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINSWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINSWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUB128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUB128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUB256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUB256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUBMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUBMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUBMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUBMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMINUWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMINUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMINUWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMINUWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBD512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXBDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXBDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXBDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBQ512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXBQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXBQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBW128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBW128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBW128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBW256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBW256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBW256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBW512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXBW512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBW512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBW512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBWMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXBWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBWMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBWMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXBWMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBWMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXBWMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXBWMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXBWMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXBWMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXDQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXDQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXDQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXDQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXDQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXDQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXDQ512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXDQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXDQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXDQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXDQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXDQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXDQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXDQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXDQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXDQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXDQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXWD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXWD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXWD512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXWDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXWDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXWDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXWQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXWQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVSXWQ512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXWQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXWQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVSXWQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVSXWQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVSXWQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVSXWQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec16x16ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec16x16ToM (VPMOVMToVec16x16 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x16 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec16x32ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec16x32ToM (VPMOVMToVec16x32 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec16x8ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec16x8ToM (VPMOVMToVec16x8 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x8 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec32x16ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec32x16ToM (VPMOVMToVec32x16 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec32x4ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec32x4ToM (VPMOVMToVec32x4 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x4 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec32x8ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec32x8ToM (VPMOVMToVec32x8 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x8 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec64x2ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec64x2ToM (VPMOVMToVec64x2 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x2 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec64x4ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec64x4ToM (VPMOVMToVec64x4 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x4 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec64x8ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec64x8ToM (VPMOVMToVec64x8 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec8x16ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec8x16ToM (VPMOVMToVec8x16 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x16 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec8x32ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec8x32ToM (VPMOVMToVec8x32 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x32 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVVec8x64ToM(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVVec8x64ToM (VPMOVMToVec8x64 x))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
			break
		}
		x := v_0.Args[0]
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBD512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXBDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXBDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXBDMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBQ512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXBQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXBQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBW128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBW128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBW128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBW256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBW256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBW256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBW512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXBW512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBW512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBW512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBWMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXBWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBWMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBWMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXBWMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBWMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXBWMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXBWMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXBWMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXBWMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXDQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXDQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXDQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXDQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXDQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXDQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXDQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXDQ512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXDQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXDQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXDQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXDQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXDQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXDQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXDQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXDQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXDQMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXDQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXDQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXWD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXWD256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXWD512 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXWDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXWDMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXWDMasked512 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXWQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXWQ256 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPMOVZXWQ512 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXWQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXWQMasked256 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMOVZXWQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMOVZXWQMasked512 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMOVZXWQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMOVZXWQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPMULDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULDQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULDQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULDQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULDQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULHUW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULHUW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULHUW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULHUW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULHUW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULHUW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULHUW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULHUW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULHUWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULHUWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULHUWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULHUWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULHUWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULHUWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULHUWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULHUWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULHW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULHW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULHW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULHW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULHW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULHW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULHW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULHW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULHWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULHWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULHWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULHWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULHWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULHWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULHWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULHWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLD128 x (VPBROADCASTD128 (VMOVD (MOVLconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLD128const [uint8(ssa.Log32(int32(c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTD128 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVD {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLD128const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log32(int32(c))))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (VPMULLD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLD128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLD128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLD256 x (VPBROADCASTD256 (VMOVD (MOVLconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLD256const [uint8(ssa.Log32(int32(c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTD256 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVD {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLD256const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log32(int32(c))))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (VPMULLD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLD256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLD256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLD512 x (VPBROADCASTD512 (VMOVD (MOVLconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLD512const [uint8(ssa.Log32(int32(c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTD512 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVD {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLD512const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log32(int32(c))))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (VPMULLD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLQ128 x (VPBROADCASTQ128 (VMOVQ (MOVQconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLQ128const [uint8(ssa.Log64(c))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTQ128 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVQ {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLQ128const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log64(c)))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (VPMULLQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLQ256 x (VPBROADCASTQ256 (VMOVQ (MOVQconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLQ256const [uint8(ssa.Log64(c))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTQ256 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVQ {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLQ256const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log64(c)))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (VPMULLQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLQ512 x (VPBROADCASTQ512 (VMOVQ (MOVQconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLQ512const [uint8(ssa.Log64(c))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTQ512 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVQ {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLQ512const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log64(c)))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (VPMULLQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLW128 x (VPBROADCASTW128 (VMOVQ (MOVLconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLW128const [uint8(ssa.Log16(int16(c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTW128 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVQ {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLW128const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log16(int16(c))))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (VPMULLW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLW128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLW128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLW256 x (VPBROADCASTW256 (VMOVQ (MOVLconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLW256const [uint8(ssa.Log16(int16(c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTW256 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVQ {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLW256const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log16(int16(c))))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (VPMULLW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLW256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLW256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLW512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLW512 x (VPBROADCASTW512 (VMOVQ (MOVLconst [c]))))
	// cond: ssa.IsPowerOfTwo(c)
	// result: (VPSLLW512const [uint8(ssa.Log16(int16(c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64VPBROADCASTW512 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VMOVQ {
				continue
			}
			v_1_0_0 := v_1_0.Args[0]
			if v_1_0_0.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1_0_0.AuxInt)
			if !(ssa.IsPowerOfTwo(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPSLLW512const)
			v.AuxInt = ssa.Uint8ToAuxInt(uint8(ssa.Log16(int16(c))))
			v.AddArg(x)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLWMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLWMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULLWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULLWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULLWMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULLWMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULUDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULUDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULUDQ128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULUDQ128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPMULUDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPMULUDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPMULUDQ256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMULUDQ256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTB128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTB128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTB128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTB256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTB256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTB256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTBMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTBMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTBMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTBMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTBMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTBMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTQ128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTQ128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTQ256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTQ256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTQ512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTQ512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTQMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTQMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTQMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTQMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTQMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTQMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTW128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTW128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTW128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTW256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPOPCNTW256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTW256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTWMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTWMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTWMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOPCNTWMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPOPCNTWMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOPCNTWMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPOPCNTWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPOR128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPOR128 (VCMPPS128 [3] x x) (VCMPPS128 [3] y y))
	// result: (VCMPPS128 [3] x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VCMPPS128 || ssa.AuxIntToUint8(v_0.AuxInt) != 3 {
				continue
			}
			x := v_0.Args[1]
			if x != v_0.Args[0] || v_1.Op != ssaop.OpAMD64VCMPPS128 || ssa.AuxIntToUint8(v_1.AuxInt) != 3 {
				continue
			}
			y := v_1.Args[1]
			if y != v_1.Args[0] {
				continue
			}
			v.Reset(ssaop.OpAMD64VCMPPS128)
			v.AuxInt = ssa.Uint8ToAuxInt(3)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (VPOR128 (VCMPPD128 [3] x x) (VCMPPD128 [3] y y))
	// result: (VCMPPD128 [3] x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VCMPPD128 || ssa.AuxIntToUint8(v_0.AuxInt) != 3 {
				continue
			}
			x := v_0.Args[1]
			if x != v_0.Args[0] || v_1.Op != ssaop.OpAMD64VCMPPD128 || ssa.AuxIntToUint8(v_1.AuxInt) != 3 {
				continue
			}
			y := v_1.Args[1]
			if y != v_1.Args[0] {
				continue
			}
			v.Reset(ssaop.OpAMD64VCMPPD128)
			v.AuxInt = ssa.Uint8ToAuxInt(3)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (VPOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x16 (KORW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x8 (KORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x4 (KORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x4 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x4 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x4)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x2 (KORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x2 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x2 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x2)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPOR128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOR128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPOR128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPOR256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPOR256 (VCMPPS256 [3] x x) (VCMPPS256 [3] y y))
	// result: (VCMPPS256 [3] x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VCMPPS256 || ssa.AuxIntToUint8(v_0.AuxInt) != 3 {
				continue
			}
			x := v_0.Args[1]
			if x != v_0.Args[0] || v_1.Op != ssaop.OpAMD64VCMPPS256 || ssa.AuxIntToUint8(v_1.AuxInt) != 3 {
				continue
			}
			y := v_1.Args[1]
			if y != v_1.Args[0] {
				continue
			}
			v.Reset(ssaop.OpAMD64VCMPPS256)
			v.AuxInt = ssa.Uint8ToAuxInt(3)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (VPOR256 (VCMPPD256 [3] x x) (VCMPPD256 [3] y y))
	// result: (VCMPPD256 [3] x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VCMPPD256 || ssa.AuxIntToUint8(v_0.AuxInt) != 3 {
				continue
			}
			x := v_0.Args[1]
			if x != v_0.Args[0] || v_1.Op != ssaop.OpAMD64VCMPPD256 || ssa.AuxIntToUint8(v_1.AuxInt) != 3 {
				continue
			}
			y := v_1.Args[1]
			if y != v_1.Args[0] {
				continue
			}
			v.Reset(ssaop.OpAMD64VCMPPD256)
			v.AuxInt = ssa.Uint8ToAuxInt(3)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (VPOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x32 (KORD x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x32 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x32 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x32)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORD, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x16 (KORW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x8 (KORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x4 (KORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x4 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x4 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x4)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPOR256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPOR256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPOR256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPORD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPORD512 (VPMOVMToVec32x16 (VCMPPS512 [3] x x)) (VPMOVMToVec32x16 (VCMPPS512 [3] y y)))
	// result: (VPMOVMToVec32x16 (VCMPPS512 [3] x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64VCMPPS512 || ssa.AuxIntToUint8(v_0_0.AuxInt) != 3 {
				continue
			}
			x := v_0_0.Args[1]
			if x != v_0_0.Args[0] || v_1.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VCMPPS512 || ssa.AuxIntToUint8(v_1_0.AuxInt) != 3 {
				continue
			}
			y := v_1_0.Args[1]
			if y != v_1_0.Args[0] {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPS512, typ.Mask)
			v0.AuxInt = ssa.Uint8ToAuxInt(3)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPORD512 (VPMOVMToVec64x8 (VCMPPD512 [3] x x)) (VPMOVMToVec64x8 (VCMPPD512 [3] y y)))
	// result: (VPMOVMToVec64x8 (VCMPPD512 [3] x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64VCMPPD512 || ssa.AuxIntToUint8(v_0_0.AuxInt) != 3 {
				continue
			}
			x := v_0_0.Args[1]
			if x != v_0_0.Args[0] || v_1.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			v_1_0 := v_1.Args[0]
			if v_1_0.Op != ssaop.OpAMD64VCMPPD512 || ssa.AuxIntToUint8(v_1_0.AuxInt) != 3 {
				continue
			}
			y := v_1_0.Args[1]
			if y != v_1_0.Args[0] {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPD512, typ.Mask)
			v0.AuxInt = ssa.Uint8ToAuxInt(3)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x64 (KORQ x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORQ, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x32 (KORD x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORD, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x16 (KORW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x8 (KORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPORD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPORD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPORD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPORDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPORDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPORDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPORDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPORDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPORDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPORDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPORDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPORDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPORDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPORDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPORDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPORQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPORQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPORQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPORQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPORQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPORQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPORQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPORQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPORQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPORQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPORQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPORQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPORQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPROLD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPROLD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPROLD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPROLD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPROLQ128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLQ128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLQ128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPROLQ256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLQ256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLQ256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPROLQ512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLQ512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLQ512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLQMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLQMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLQMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLQMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLQMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLQMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLQMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLQMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLQMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVQMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVQMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPROLVQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPROLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPROLVQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPROLVQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPRORD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPRORD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPRORD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORQ128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPRORQ128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORQ128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORQ128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORQ256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPRORQ256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORQ256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORQ256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORQ512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPRORQ512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORQ512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORQ512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORQMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORQMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORQMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORQMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORQMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORQMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORQMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORQMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORQMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORQMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORQMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORQMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVQMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVQMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPRORVQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPRORVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPRORVQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPRORVQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSADBW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSADBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSADBW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSADBW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSADBW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSADBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSADBW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSADBW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDQ128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDQ128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDQ256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDQ256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDQ512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDQ512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDQMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDQMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDQMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDQMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDQMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDQMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVD128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVD128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVD256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVD256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVD512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVD512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVDMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVDMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVDMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVDMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVDMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVDMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVQ128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVQ128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVQ128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVQ256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVQ256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVQ256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVQ512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVQ512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVQ512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVQMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVQMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVQMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVQMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVQMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVQMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVQMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVQMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVQMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVW128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVW128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVW128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVW256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVW256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVW256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVWMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVWMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVWMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDVWMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDVWMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDVWMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDVWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDW128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDW128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDW128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDW256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDW256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDW256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDWMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDWMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHLDWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHLDWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHLDWMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHLDWMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDDMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDDMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDDMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDQ128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDQ128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDQ128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDQ256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDQ256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDQ256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDQ512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDQ512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDQ512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDQMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDQMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDQMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDQMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDQMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDQMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDQMasked512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDQMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDQMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVD128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVD128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVD128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVD256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVD256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVD256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVD512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVD512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVD512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVDMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVDMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVDMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVDMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVDMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVDMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVDMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVDMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVDMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVQ128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVQ128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVQ128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVQ256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVQ256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVQ256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVQ512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVQ512 x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVQ512load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVQMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVQMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVQMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVQMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVQMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVQMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVQMasked512(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVQMasked512 x y l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVQMasked512load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVW128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVW128 x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVW128load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVW256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVW256 x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVW256load {sym} [off] x y ptr mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVWMasked128(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVWMasked128 x y l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVWMasked128load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDVWMasked256(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDVWMasked256 x y l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDVWMasked256load {sym} [off] x y ptr mask mem)
	for {
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_3
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDVWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg5(x, y, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDW128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDW128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDW128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDW256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDW256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDW256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDWMasked128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDWMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDWMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHRDWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHRDWMasked256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHRDWMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHRDWMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFB128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFB256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFBMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFBMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSHUFD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSHUFD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSHUFD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFHW128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSHUFHW128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFHW128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFHW128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFHW256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSHUFHW256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFHW256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFHW256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFHWMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFHWMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFHWMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFHWMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFHWMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFHWMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFHWMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFHWMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFLW128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSHUFLW128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFLW128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFLW128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFLW256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSHUFLW256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFLW256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFLW256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFLWMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFLWMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFLWMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFLWMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSHUFLWMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSHUFLWMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSHUFLWMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSHUFLWMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSIGNB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSIGNB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSIGNB128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSIGNB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSIGNB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSIGNB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSIGNB256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSIGNB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSIGND128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSIGND128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSIGND128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSIGND128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSIGND256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSIGND256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSIGND256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSIGND256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSIGNW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSIGNW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSIGNW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSIGNW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSIGNW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSIGNW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSIGNW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSIGNW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLD128 x (MOVQconst [c]))
	// result: (VPSLLD128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLD128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLD128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLD128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLD256 x (MOVQconst [c]))
	// result: (VPSLLD256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLD256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLD256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLD256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLD512 x (MOVQconst [c]))
	// result: (VPSLLD512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLD512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLD512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLD512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLD512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLD512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLDMasked128 x (MOVQconst [c]) mask)
	// result: (VPSLLDMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLDMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLDMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLDMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLDMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLDMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLDMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLDMasked256 x (MOVQconst [c]) mask)
	// result: (VPSLLDMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLDMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLDMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLDMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLDMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLDMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLDMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLDMasked512 x (MOVQconst [c]) mask)
	// result: (VPSLLDMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLDMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLDMasked512const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLDMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLDMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLDMasked512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLDMasked512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQ128 x (MOVQconst [c]))
	// result: (VPSLLQ128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLQ128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQ128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLQ128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQ256 x (MOVQconst [c]))
	// result: (VPSLLQ256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLQ256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQ256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLQ256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQ512 x (MOVQconst [c]))
	// result: (VPSLLQ512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLQ512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQ512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLQ512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLQ512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLQ512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQMasked128 x (MOVQconst [c]) mask)
	// result: (VPSLLQMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLQMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLQMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLQMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQMasked256 x (MOVQconst [c]) mask)
	// result: (VPSLLQMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLQMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLQMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLQMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQMasked512 x (MOVQconst [c]) mask)
	// result: (VPSLLQMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLQMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLQMasked512const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLQMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLQMasked512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLQMasked512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVQMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVQMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLVWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLVWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLVWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLW128 x (MOVQconst [c]))
	// result: (VPSLLW128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLW128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLW128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLW128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLW256 x (MOVQconst [c]))
	// result: (VPSLLW256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLW256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLW256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLW256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLW512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLW512 x (MOVQconst [c]))
	// result: (VPSLLW512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSLLW512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLW512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLW512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLWMasked128 x (MOVQconst [c]) mask)
	// result: (VPSLLWMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLWMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLWMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLWMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLWMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLWMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLWMasked256 x (MOVQconst [c]) mask)
	// result: (VPSLLWMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLWMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLWMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLWMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSLLWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSLLWMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSLLWMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLWMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSLLWMasked512 x (MOVQconst [c]) mask)
	// result: (VPSLLWMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSLLWMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSLLWMasked512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSLLWMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAD128 x (MOVQconst [c]))
	// result: (VPSRAD128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAD128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAD128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAD128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAD256 x (MOVQconst [c]))
	// result: (VPSRAD256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAD256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAD256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAD256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAD512 x (MOVQconst [c]))
	// result: (VPSRAD512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAD512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAD512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAD512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAD512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAD512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRADMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRADMasked128 x (MOVQconst [c]) mask)
	// result: (VPSRADMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRADMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRADMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRADMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRADMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRADMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRADMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRADMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRADMasked256 x (MOVQconst [c]) mask)
	// result: (VPSRADMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRADMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRADMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRADMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRADMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRADMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRADMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRADMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRADMasked512 x (MOVQconst [c]) mask)
	// result: (VPSRADMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRADMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRADMasked512const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRADMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRADMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRADMasked512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRADMasked512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQ128 x (MOVQconst [c]))
	// result: (VPSRAQ128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAQ128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQ128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAQ128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAQ128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAQ128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAQ128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQ256 x (MOVQconst [c]))
	// result: (VPSRAQ256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAQ256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQ256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAQ256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAQ256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAQ256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAQ256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQ512 x (MOVQconst [c]))
	// result: (VPSRAQ512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAQ512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQ512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAQ512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAQ512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAQ512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQMasked128 x (MOVQconst [c]) mask)
	// result: (VPSRAQMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAQMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAQMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAQMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQMasked256 x (MOVQconst [c]) mask)
	// result: (VPSRAQMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAQMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAQMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAQMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQMasked512 x (MOVQconst [c]) mask)
	// result: (VPSRAQMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAQMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAQMasked512const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAQMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAQMasked512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAQMasked512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVQMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVQMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAVWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAVWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAVWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAW128 x (MOVQconst [c]))
	// result: (VPSRAW128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAW128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAW128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAW128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAW256 x (MOVQconst [c]))
	// result: (VPSRAW256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAW256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAW256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAW256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAW512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAW512 x (MOVQconst [c]))
	// result: (VPSRAW512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRAW512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAW512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAW512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAWMasked128 x (MOVQconst [c]) mask)
	// result: (VPSRAWMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAWMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAWMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAWMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAWMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAWMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAWMasked256 x (MOVQconst [c]) mask)
	// result: (VPSRAWMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAWMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAWMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAWMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRAWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRAWMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRAWMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAWMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRAWMasked512 x (MOVQconst [c]) mask)
	// result: (VPSRAWMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRAWMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRAWMasked512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRAWMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLD128 x (MOVQconst [c]))
	// result: (VPSRLD128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLD128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLD128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLD128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLD256 x (MOVQconst [c]))
	// result: (VPSRLD256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLD256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLD256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLD256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLD512 x (MOVQconst [c]))
	// result: (VPSRLD512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLD512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLD512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLD512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLD512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLD512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLD512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLDMasked128 x (MOVQconst [c]) mask)
	// result: (VPSRLDMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLDMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLDMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLDMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLDMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLDMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLDMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLDMasked256 x (MOVQconst [c]) mask)
	// result: (VPSRLDMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLDMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLDMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLDMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLDMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLDMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLDMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLDMasked512 x (MOVQconst [c]) mask)
	// result: (VPSRLDMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLDMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLDMasked512const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLDMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLDMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLDMasked512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLDMasked512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQ128 x (MOVQconst [c]))
	// result: (VPSRLQ128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLQ128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQ128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLQ128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQ256 x (MOVQconst [c]))
	// result: (VPSRLQ256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLQ256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQ256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLQ256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQ512 x (MOVQconst [c]))
	// result: (VPSRLQ512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLQ512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQ512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLQ512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLQ512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLQ512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLQ512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQMasked128 x (MOVQconst [c]) mask)
	// result: (VPSRLQMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLQMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLQMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLQMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLQMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQMasked256 x (MOVQconst [c]) mask)
	// result: (VPSRLQMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLQMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLQMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLQMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLQMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQMasked512 x (MOVQconst [c]) mask)
	// result: (VPSRLQMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLQMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLQMasked512const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLQMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLQMasked512const [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLQMasked512constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLQMasked512constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVQMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVQMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLVWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLVWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLVWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLVWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLW128 x (MOVQconst [c]))
	// result: (VPSRLW128const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLW128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLW128const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLW128const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLW256 x (MOVQconst [c]))
	// result: (VPSRLW256const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLW256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLW256const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLW256const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLW512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLW512 x (MOVQconst [c]))
	// result: (VPSRLW512const [amd64CapAVXShift(c)] x)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		v.Reset(ssaop.OpAMD64VPSRLW512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLW512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLW512const [a] x)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLWMasked128 x (MOVQconst [c]) mask)
	// result: (VPSRLWMasked128const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLWMasked128const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLWMasked128const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLWMasked128const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLWMasked128const [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLWMasked128constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLWMasked128constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLWMasked256 x (MOVQconst [c]) mask)
	// result: (VPSRLWMasked256const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLWMasked256const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLWMasked256const(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLWMasked256const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	// match: (VPSRLWMasked256const [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSRLWMasked256constload {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSRLWMasked256constload)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLWMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSRLWMasked512 x (MOVQconst [c]) mask)
	// result: (VPSRLWMasked512const [amd64CapAVXShift(c)] x mask)
	for {
		x := v_0
		if v_1.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		c := ssa.AuxIntToInt64(v_1.AuxInt)
		mask := v_2
		v.Reset(ssaop.OpAMD64VPSRLWMasked512const)
		v.AuxInt = ssa.Uint8ToAuxInt(amd64CapAVXShift(c))
		v.AddArg2(x, mask)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSRLWMasked512const(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VPSRLWMasked512const [a] x mask)
	// cond: a==0
	// result: x
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		if !(a == 0) {
			break
		}
		v.CopyOf(x)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBB128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBB256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBBMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBBMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBQMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBQMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBQMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBQMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBQMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBQMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBSB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBSB128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBSB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBSB256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBSBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBSBMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBSBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBSBMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBSW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBSW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBSWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBSWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBSWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBSWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBSWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBUSB128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBUSB128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBUSB128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSB128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBUSB256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBUSB256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBUSB256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSB256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBUSBMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBUSBMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBUSBMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSBMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBUSBMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBUSBMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBUSBMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSBMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBUSW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBUSW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBUSW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBUSW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBUSW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBUSW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBUSWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBUSWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBUSWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBUSWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBUSWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBUSWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBUSWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBW128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBW128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBW128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBW128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBW256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBW256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBW256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBW256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBWMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBWMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBWMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBWMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPSUBWMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPSUBWMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPSUBWMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPSUBWMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPTERNLOGD128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPTERNLOGD128 [c] x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPTERNLOGD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x y ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPTERNLOGD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPTERNLOGD256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPTERNLOGD256 [c] x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPTERNLOGD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x y ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPTERNLOGD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPTERNLOGD512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPTERNLOGD512 [c] x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPTERNLOGD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x y ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPTERNLOGD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPTERNLOGQ128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPTERNLOGQ128 [c] x y l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPTERNLOGQ128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x y ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPTERNLOGQ128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPTERNLOGQ256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPTERNLOGQ256 [c] x y l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPTERNLOGQ256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x y ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPTERNLOGQ256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPTERNLOGQ512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPTERNLOGQ512 [c] x y l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPTERNLOGQ512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x y ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		y := v_1
		l := v_2
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPTERNLOGQ512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, y, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKHDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKHDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKHDQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKHDQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKHDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKHDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKHDQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKHDQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKHDQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKHDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKHDQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKHDQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKHQDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKHQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKHQDQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKHQDQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKHQDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKHQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKHQDQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKHQDQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKHQDQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKHQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKHQDQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKHQDQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKHWD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKHWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKHWD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKHWD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKHWD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKHWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKHWD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKHWD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKLDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKLDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKLDQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKLDQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKLDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKLDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKLDQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKLDQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKLDQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKLDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKLDQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKLDQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKLQDQ128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKLQDQ128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKLQDQ128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKLQDQ128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKLQDQ256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKLQDQ256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKLQDQ256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKLQDQ256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKLQDQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKLQDQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKLQDQ512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKLQDQ512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKLWD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKLWD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKLWD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKLWD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPUNPCKLWD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPUNPCKLWD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPUNPCKLWD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VPUNPCKLWD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VPXOR128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPXOR128 (VPMOVMToVec8x16 x) (VPMOVMToVec8x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x16 (KXORW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXOR128 (VPMOVMToVec16x8 x) (VPMOVMToVec16x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x8 (KXORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXOR128 (VPMOVMToVec32x4 x) (VPMOVMToVec32x4 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x4 (KXORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x4 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x4 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x4)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXOR128 (VPMOVMToVec64x2 x) (VPMOVMToVec64x2 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x2 (KXORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x2 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x2 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x2)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXOR128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXOR128load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXOR128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXOR256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPXOR256 (VPMOVMToVec8x32 x) (VPMOVMToVec8x32 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x32 (KXORD x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x32 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x32 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x32)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORD, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXOR256 (VPMOVMToVec16x16 x) (VPMOVMToVec16x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x16 (KXORW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXOR256 (VPMOVMToVec32x8 x) (VPMOVMToVec32x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x8 (KXORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXOR256 (VPMOVMToVec64x4 x) (VPMOVMToVec64x4 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x4 (KXORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x4 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x4 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x4)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXOR256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXOR256load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXOR256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXORD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (VPXORD512 (VPMOVMToVec8x64 x) (VPMOVMToVec8x64 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec8x64 (KXORQ x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec8x64 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORQ, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXORD512 (VPMOVMToVec16x32 x) (VPMOVMToVec16x32 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec16x32 (KXORD x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec16x32 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORD, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXORD512 (VPMOVMToVec32x16 x) (VPMOVMToVec32x16 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec32x16 (KXORW x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec32x16 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORW, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXORD512 (VPMOVMToVec64x8 x) (VPMOVMToVec64x8 y))
	// cond: v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)
	// result: (VPMOVMToVec64x8 (KXORB x y))
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			x := v_0.Args[0]
			if v_1.Op != ssaop.OpAMD64VPMOVMToVec64x8 {
				continue
			}
			y := v_1.Args[0]
			if !(v.Block.CPUfeatures.HasFeature(ssa.CPUavx512)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
			v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KXORB, typ.Mask)
			v0.AddArg2(x, y)
			v.AddArg(v0)
			return true
		}
		break
	}
	// match: (VPXORD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXORD512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXORD512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXORDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPXORDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXORDMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXORDMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXORDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPXORDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXORDMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXORDMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXORDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPXORDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXORDMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXORDMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXORQ512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPXORQ512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXORQ512load {sym} [off] x ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXORQ512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXORQMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPXORQMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXORQMasked128load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload128 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXORQMasked128load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXORQMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPXORQMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXORQMasked256load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload256 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXORQMasked256load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VPXORQMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VPXORQMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VPXORQMasked512load {sym} [off] x ptr mask mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64VMOVDQUload512 {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			mask := v_2
			if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64VPXORQMasked512load)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg4(x, ptr, mask, mem)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRCP14PD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRCP14PD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRCP14PD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRCP14PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRCP14PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRCP14PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PS512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRCP14PS512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PS512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRCP14PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PSMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRCP14PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCP14PSMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRCP14PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCP14PSMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCP14PSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCPPS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRCPPS128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCPPS128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCPPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRCPPS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRCPPS256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRCPPS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRCPPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VREDUCEPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VREDUCEPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VREDUCEPD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VREDUCEPDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VREDUCEPDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VREDUCEPDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VREDUCEPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPS128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPS128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VREDUCEPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPS256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPS256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPS512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VREDUCEPS512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPS512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPS512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VREDUCEPSMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPSMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VREDUCEPSMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPSMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VREDUCEPSMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VREDUCEPSMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VREDUCEPSMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VREDUCEPSMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRNDSCALEPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRNDSCALEPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRNDSCALEPD512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRNDSCALEPDMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPDMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRNDSCALEPDMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPDMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRNDSCALEPDMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPDMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPDMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRNDSCALEPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPS128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPS128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRNDSCALEPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPS256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPS256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPS512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRNDSCALEPS512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPS512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPS512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRNDSCALEPSMasked128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPSMasked128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRNDSCALEPSMasked256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPSMasked256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRNDSCALEPSMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRNDSCALEPSMasked512 [c] l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRNDSCALEPSMasked512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mask mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRNDSCALEPSMasked512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VROUNDPD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VROUNDPD128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VROUNDPD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VROUNDPD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VROUNDPD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VROUNDPD256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VROUNDPD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VROUNDPD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VROUNDPS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VROUNDPS128 [c] l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VROUNDPS128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VROUNDPS128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VROUNDPS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VROUNDPS256 [c] l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VROUNDPS256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VROUNDPS256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRSQRT14PD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRSQRT14PD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRSQRT14PD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRSQRT14PDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRSQRT14PDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRSQRT14PDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PS512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRSQRT14PS512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PS512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRSQRT14PSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PSMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRSQRT14PSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRT14PSMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VRSQRT14PSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRT14PSMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRT14PSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRTPS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRTPS128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRTPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VRSQRTPS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VRSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VRSQRTPS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VRSQRTPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPS128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPS256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPS512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPSMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPSMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPSMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSCALEFPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSCALEFPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSCALEFPSMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSCALEFPSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSHUFPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSHUFPD128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSHUFPD128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSHUFPD128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSHUFPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSHUFPD256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSHUFPD256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSHUFPD256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSHUFPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSHUFPD512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSHUFPD512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSHUFPD512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSHUFPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSHUFPS128 [c] x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSHUFPS128load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSHUFPS128load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSHUFPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSHUFPS256 [c] x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSHUFPS256load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSHUFPS256load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSHUFPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSHUFPS512 [c] x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSHUFPS512load {sym} [ssa.MakeValAndOff(int32(uint8(c)),off)] x ptr mem)
	for {
		c := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSHUFPS512load)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(int32(uint8(c)), off))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPD128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VSQRTPD128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPD128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPD256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VSQRTPD256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPD256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPD512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VSQRTPD512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPD512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPDMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSQRTPDMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPDMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPDMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSQRTPDMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPDMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPDMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSQRTPDMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPDMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPS128(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VSQRTPS128 l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPS128load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPS256(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VSQRTPS256 l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPS256load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPS512(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (VSQRTPS512 l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPS512load {sym} [off] ptr mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPSMasked128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSQRTPSMasked128 l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPSMasked128load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPSMasked256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSQRTPSMasked256 l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPSMasked256load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSQRTPSMasked512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSQRTPSMasked512 l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSQRTPSMasked512load {sym} [off] ptr mask mem)
	for {
		l := v_0
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_1
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSQRTPSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPD128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPD128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPD128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPD128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPD256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPD256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPD256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPD256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPD512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPD512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPD512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPD512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPDMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPDMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPDMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPDMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPDMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPDMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPDMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPDMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPDMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPDMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPDMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPDMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPS128(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPS128 x l:(VMOVDQUload128 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPS128load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPS128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPS256(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPS256 x l:(VMOVDQUload256 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPS256load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPS256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPS512(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPS512 x l:(VMOVDQUload512 {sym} [off] ptr mem))
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPS512load {sym} [off] x ptr mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPS512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(x, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPSMasked128(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPSMasked128 x l:(VMOVDQUload128 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPSMasked128load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload128 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPSMasked128load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPSMasked256(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPSMasked256 x l:(VMOVDQUload256 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPSMasked256load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload256 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPSMasked256load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64VSUBPSMasked512(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (VSUBPSMasked512 x l:(VMOVDQUload512 {sym} [off] ptr mem) mask)
	// cond: ssa.CanMergeLoad(v, l) && ssa.Clobber(l)
	// result: (VSUBPSMasked512load {sym} [off] x ptr mask mem)
	for {
		x := v_0
		l := v_1
		if l.Op != ssaop.OpAMD64VMOVDQUload512 {
			break
		}
		off := ssa.AuxIntToInt32(l.AuxInt)
		sym := ssa.AuxToSym(l.Aux)
		mem := l.Args[1]
		ptr := l.Args[0]
		mask := v_2
		if !(ssa.CanMergeLoad(v, l) && ssa.Clobber(l)) {
			break
		}
		v.Reset(ssaop.OpAMD64VSUBPSMasked512load)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg4(x, ptr, mask, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XADDLlock(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XADDLlock [off1] {sym} val (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (XADDLlock [off1+off2] {sym} val ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		ptr := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64XADDLlock)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XADDQlock(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XADDQlock [off1] {sym} val (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (XADDQlock [off1+off2] {sym} val ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		ptr := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64XADDQlock)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XCHGL(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XCHGL [off1] {sym} val (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (XCHGL [off1+off2] {sym} val ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		ptr := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64XCHGL)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, ptr, mem)
		return true
	}
	// match: (XCHGL [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && ptr.Op != ssaop.OpSB
	// result: (XCHGL [off1+off2] {ssa.MergeSym(sym1,sym2)} val ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		ptr := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && ptr.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64XCHGL)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XCHGQ(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XCHGQ [off1] {sym} val (ADDQconst [off2] ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (XCHGQ [off1+off2] {sym} val ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		ptr := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64XCHGQ)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, ptr, mem)
		return true
	}
	// match: (XCHGQ [off1] {sym1} val (LEAQ [off2] {sym2} ptr) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && ptr.Op != ssaop.OpSB
	// result: (XCHGQ [off1+off2] {ssa.MergeSym(sym1,sym2)} val ptr mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		ptr := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2) && ptr.Op != ssaop.OpSB) {
			break
		}
		v.Reset(ssaop.OpAMD64XCHGQ)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORBconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XORBconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (XORBconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (XORBconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (XORBconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORBconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORL(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XORL (SHLL (MOVLconst [1]) y) x)
	// result: (BTCL x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64SHLL {
				continue
			}
			y := v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0_0.AuxInt) != 1 {
				continue
			}
			x := v_1
			v.Reset(ssaop.OpAMD64BTCL)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (XORL x (MOVLconst [c]))
	// result: (XORLconst [c] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVLconst {
				continue
			}
			c := ssa.AuxIntToInt32(v_1.AuxInt)
			v.Reset(ssaop.OpAMD64XORLconst)
			v.AuxInt = ssa.Int32ToAuxInt(c)
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (XORL x x)
	// result: (MOVLconst [0])
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (XORL x l:(MOVLload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (XORLload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVLload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64XORLload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	// match: (XORL x (ADDLconst [-1] x))
	// cond: buildcfg.GOAMD64 >= 3
	// result: (BLSMSKL x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64ADDLconst || ssa.AuxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) {
				continue
			}
			v.Reset(ssaop.OpAMD64BLSMSKL)
			v.AddArg(x)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64XORLconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (XORLconst [1] (SETNE x))
	// result: (SETEQ x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETNE {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETEQ)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETEQ x))
	// result: (SETNE x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETEQ {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETNE)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETL x))
	// result: (SETGE x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETL {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETGE)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETGE x))
	// result: (SETL x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETGE {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETL)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETLE x))
	// result: (SETG x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETLE {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETG)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETG x))
	// result: (SETLE x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETG {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETLE)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETB x))
	// result: (SETAE x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETB {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETAE)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETAE x))
	// result: (SETB x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETAE {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETB)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETBE x))
	// result: (SETA x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETBE {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETA)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [1] (SETA x))
	// result: (SETBE x)
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 1 || v_0.Op != ssaop.OpAMD64SETA {
			break
		}
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETBE)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [c] (XORLconst [d] x))
	// result: (XORLconst [c ^ d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64XORLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64XORLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c ^ d)
		v.AddArg(x)
		return true
	}
	// match: (XORLconst [0] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (XORLconst [c] (MOVLconst [d]))
	// result: (MOVLconst [c^d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVLconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c ^ d)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORLconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XORLconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (XORLconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (XORLconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (XORLconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORLconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORLload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (XORLload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (XORLload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64XORLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (XORLload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (XORLload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORLload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (XORLload x [off] {sym} ptr (MOVSSstore [off] {sym} ptr y _))
	// result: (XORL x (MOVLf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSSstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64XORL)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVLf2i, typ.UInt32)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORLmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XORLmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (XORLmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64XORLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (XORLmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (XORLmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORLmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORQ(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XORQ (SHLQ (MOVQconst [1]) y) x)
	// result: (BTCQ x y)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64SHLQ {
				continue
			}
			y := v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_0_0.AuxInt) != 1 {
				continue
			}
			x := v_1
			v.Reset(ssaop.OpAMD64BTCQ)
			v.AddArg2(x, y)
			return true
		}
		break
	}
	// match: (XORQ (MOVQconst [c]) x)
	// cond: ssa.IsPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31
	// result: (BTCQconst [int8(ssa.Log64u(uint64(c)))] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			if v_0.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_0.AuxInt)
			x := v_1
			if !(ssa.IsPowerOfTwo(uint64(c)) && uint64(c) >= 1<<31) {
				continue
			}
			v.Reset(ssaop.OpAMD64BTCQconst)
			v.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(c))))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (XORQ x (MOVQconst [c]))
	// cond: ssa.Is32Bit(c)
	// result: (XORQconst [int32(c)] x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64MOVQconst {
				continue
			}
			c := ssa.AuxIntToInt64(v_1.AuxInt)
			if !(ssa.Is32Bit(c)) {
				continue
			}
			v.Reset(ssaop.OpAMD64XORQconst)
			v.AuxInt = ssa.Int32ToAuxInt(int32(c))
			v.AddArg(x)
			return true
		}
		break
	}
	// match: (XORQ x x)
	// result: (MOVLconst [0])
	for {
		x := v_0
		if x != v_1 {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(0)
		return true
	}
	// match: (XORQ x l:(MOVQload [off] {sym} ptr mem))
	// cond: ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)
	// result: (XORQload x [off] {sym} ptr mem)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			l := v_1
			if l.Op != ssaop.OpAMD64MOVQload {
				continue
			}
			off := ssa.AuxIntToInt32(l.AuxInt)
			sym := ssa.AuxToSym(l.Aux)
			mem := l.Args[1]
			ptr := l.Args[0]
			if !(ssa.CanMergeLoadClobber(v, l, x) && ssa.Clobber(l)) {
				continue
			}
			v.Reset(ssaop.OpAMD64XORQload)
			v.AuxInt = ssa.Int32ToAuxInt(off)
			v.Aux = ssa.SymToAux(sym)
			v.AddArg3(x, ptr, mem)
			return true
		}
		break
	}
	// match: (XORQ x (ADDQconst [-1] x))
	// cond: buildcfg.GOAMD64 >= 3
	// result: (BLSMSKQ x)
	for {
		for _i0 := 0; _i0 <= 1; _i0, v_0, v_1 = _i0+1, v_1, v_0 {
			x := v_0
			if v_1.Op != ssaop.OpAMD64ADDQconst || ssa.AuxIntToInt32(v_1.AuxInt) != -1 || x != v_1.Args[0] || !(buildcfg.GOAMD64 >= 3) {
				continue
			}
			v.Reset(ssaop.OpAMD64BLSMSKQ)
			v.AddArg(x)
			return true
		}
		break
	}
	return false
}
func rewriteValue_OpAMD64XORQconst(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (XORQconst [c] (XORQconst [d] x))
	// result: (XORQconst [c ^ d] x)
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64XORQconst {
			break
		}
		d := ssa.AuxIntToInt32(v_0.AuxInt)
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64XORQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c ^ d)
		v.AddArg(x)
		return true
	}
	// match: (XORQconst [0] x)
	// result: x
	for {
		if ssa.AuxIntToInt32(v.AuxInt) != 0 {
			break
		}
		x := v_0
		v.CopyOf(x)
		return true
	}
	// match: (XORQconst [c] (MOVQconst [d]))
	// result: (MOVQconst [int64(c)^d])
	for {
		c := ssa.AuxIntToInt32(v.AuxInt)
		if v_0.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		d := ssa.AuxIntToInt64(v_0.AuxInt)
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(int64(c) ^ d)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORQconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XORQconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (XORQconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (XORQconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (XORQconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORQload(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (XORQload [off1] {sym} val (ADDQconst [off2] base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (XORQload [off1+off2] {sym} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (XORQload [off1] {sym1} val (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (XORQload [off1+off2] {ssa.MergeSym(sym1,sym2)} val base mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		val := v_0
		if v_1.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_1.AuxInt)
		sym2 := ssa.AuxToSym(v_1.Aux)
		base := v_1.Args[0]
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQload)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(val, base, mem)
		return true
	}
	// match: (XORQload x [off] {sym} ptr (MOVSDstore [off] {sym} ptr y _))
	// result: (XORQ x (MOVQf2i y))
	for {
		off := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		x := v_0
		ptr := v_1
		if v_2.Op != ssaop.OpAMD64MOVSDstore || ssa.AuxIntToInt32(v_2.AuxInt) != off || ssa.AuxToSym(v_2.Aux) != sym {
			break
		}
		y := v_2.Args[1]
		if ptr != v_2.Args[0] {
			break
		}
		v.Reset(ssaop.OpAMD64XORQ)
		v0 := b.NewValue0(v_2.Pos, ssaop.OpAMD64MOVQf2i, typ.UInt64)
		v0.AddArg(y)
		v.AddArg2(x, v0)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORQmodify(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XORQmodify [off1] {sym} (ADDQconst [off2] base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2))
	// result: (XORQmodify [off1+off2] {sym} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1) + int64(off2))) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(base, val, mem)
		return true
	}
	// match: (XORQmodify [off1] {sym1} (LEAQ [off2] {sym2} base) val mem)
	// cond: ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)
	// result: (XORQmodify [off1+off2] {ssa.MergeSym(sym1,sym2)} base val mem)
	for {
		off1 := ssa.AuxIntToInt32(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		val := v_1
		mem := v_2
		if !(ssa.Is32Bit(int64(off1)+int64(off2)) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQmodify)
		v.AuxInt = ssa.Int32ToAuxInt(off1 + off2)
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg3(base, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpAMD64XORWconstmodify(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (XORWconstmodify [valoff1] {sym} (ADDQconst [off2] base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2)
	// result: (XORWconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {sym} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64ADDQconst {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(sym)
		v.AddArg2(base, mem)
		return true
	}
	// match: (XORWconstmodify [valoff1] {sym1} (LEAQ [off2] {sym2} base) mem)
	// cond: ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)
	// result: (XORWconstmodify [ssa.ValAndOff(valoff1).AddOffset32(off2)] {ssa.MergeSym(sym1,sym2)} base mem)
	for {
		valoff1 := ssa.AuxIntToValAndOff(v.AuxInt)
		sym1 := ssa.AuxToSym(v.Aux)
		if v_0.Op != ssaop.OpAMD64LEAQ {
			break
		}
		off2 := ssa.AuxIntToInt32(v_0.AuxInt)
		sym2 := ssa.AuxToSym(v_0.Aux)
		base := v_0.Args[0]
		mem := v_1
		if !(ssa.ValAndOff(valoff1).CanAdd32(off2) && ssa.CanMergeSym(sym1, sym2)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORWconstmodify)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.ValAndOff(valoff1).AddOffset32(off2))
		v.Aux = ssa.SymToAux(ssa.MergeSym(sym1, sym2))
		v.AddArg2(base, mem)
		return true
	}
	return false
}
func rewriteValue_OpAddr(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Addr {sym} base)
	// result: (LEAQ {sym} base)
	for {
		sym := ssa.AuxToSym(v.Aux)
		base := v_0
		v.Reset(ssaop.OpAMD64LEAQ)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg(base)
		return true
	}
}
func rewriteValue_OpAtomicAdd32(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (AtomicAdd32 ptr val mem)
	// result: (AddTupleFirst32 val (XADDLlock val ptr mem))
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64AddTupleFirst32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64XADDLlock, types.NewTuple(typ.UInt32, types.TypeMem))
		v0.AddArg3(val, ptr, mem)
		v.AddArg2(val, v0)
		return true
	}
}
func rewriteValue_OpAtomicAdd64(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (AtomicAdd64 ptr val mem)
	// result: (AddTupleFirst64 val (XADDQlock val ptr mem))
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64AddTupleFirst64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64XADDQlock, types.NewTuple(typ.UInt64, types.TypeMem))
		v0.AddArg3(val, ptr, mem)
		v.AddArg2(val, v0)
		return true
	}
}
func rewriteValue_OpAtomicAnd32(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicAnd32 ptr val mem)
	// result: (ANDLlock ptr val mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64ANDLlock)
		v.AddArg3(ptr, val, mem)
		return true
	}
}
func rewriteValue_OpAtomicAnd32value(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicAnd32value ptr val mem)
	// result: (LoweredAtomicAnd32 ptr val mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64LoweredAtomicAnd32)
		v.AddArg3(ptr, val, mem)
		return true
	}
}
func rewriteValue_OpAtomicAnd64value(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicAnd64value ptr val mem)
	// result: (LoweredAtomicAnd64 ptr val mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64LoweredAtomicAnd64)
		v.AddArg3(ptr, val, mem)
		return true
	}
}
func rewriteValue_OpAtomicAnd8(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicAnd8 ptr val mem)
	// result: (ANDBlock ptr val mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64ANDBlock)
		v.AddArg3(ptr, val, mem)
		return true
	}
}
func rewriteValue_OpAtomicCompareAndSwap32(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicCompareAndSwap32 ptr old new_ mem)
	// result: (CMPXCHGLlock ptr old new_ mem)
	for {
		ptr := v_0
		old := v_1
		new_ := v_2
		mem := v_3
		v.Reset(ssaop.OpAMD64CMPXCHGLlock)
		v.AddArg4(ptr, old, new_, mem)
		return true
	}
}
func rewriteValue_OpAtomicCompareAndSwap64(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicCompareAndSwap64 ptr old new_ mem)
	// result: (CMPXCHGQlock ptr old new_ mem)
	for {
		ptr := v_0
		old := v_1
		new_ := v_2
		mem := v_3
		v.Reset(ssaop.OpAMD64CMPXCHGQlock)
		v.AddArg4(ptr, old, new_, mem)
		return true
	}
}
func rewriteValue_OpAtomicExchange32(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicExchange32 ptr val mem)
	// result: (XCHGL val ptr mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64XCHGL)
		v.AddArg3(val, ptr, mem)
		return true
	}
}
func rewriteValue_OpAtomicExchange64(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicExchange64 ptr val mem)
	// result: (XCHGQ val ptr mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64XCHGQ)
		v.AddArg3(val, ptr, mem)
		return true
	}
}
func rewriteValue_OpAtomicExchange8(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicExchange8 ptr val mem)
	// result: (XCHGB val ptr mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64XCHGB)
		v.AddArg3(val, ptr, mem)
		return true
	}
}
func rewriteValue_OpAtomicLoad32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicLoad32 ptr mem)
	// result: (MOVLatomicload ptr mem)
	for {
		ptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVLatomicload)
		v.AddArg2(ptr, mem)
		return true
	}
}
func rewriteValue_OpAtomicLoad64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicLoad64 ptr mem)
	// result: (MOVQatomicload ptr mem)
	for {
		ptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVQatomicload)
		v.AddArg2(ptr, mem)
		return true
	}
}
func rewriteValue_OpAtomicLoad8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicLoad8 ptr mem)
	// result: (MOVBatomicload ptr mem)
	for {
		ptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVBatomicload)
		v.AddArg2(ptr, mem)
		return true
	}
}
func rewriteValue_OpAtomicLoadPtr(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicLoadPtr ptr mem)
	// result: (MOVQatomicload ptr mem)
	for {
		ptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVQatomicload)
		v.AddArg2(ptr, mem)
		return true
	}
}
func rewriteValue_OpAtomicOr32(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicOr32 ptr val mem)
	// result: (ORLlock ptr val mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64ORLlock)
		v.AddArg3(ptr, val, mem)
		return true
	}
}
func rewriteValue_OpAtomicOr32value(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicOr32value ptr val mem)
	// result: (LoweredAtomicOr32 ptr val mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64LoweredAtomicOr32)
		v.AddArg3(ptr, val, mem)
		return true
	}
}
func rewriteValue_OpAtomicOr64value(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicOr64value ptr val mem)
	// result: (LoweredAtomicOr64 ptr val mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64LoweredAtomicOr64)
		v.AddArg3(ptr, val, mem)
		return true
	}
}
func rewriteValue_OpAtomicOr8(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (AtomicOr8 ptr val mem)
	// result: (ORBlock ptr val mem)
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64ORBlock)
		v.AddArg3(ptr, val, mem)
		return true
	}
}
func rewriteValue_OpAtomicStore32(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (AtomicStore32 ptr val mem)
	// result: (Select1 (XCHGL <types.NewTuple(typ.UInt32,types.TypeMem)> val ptr mem))
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64XCHGL, types.NewTuple(typ.UInt32, types.TypeMem))
		v0.AddArg3(val, ptr, mem)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpAtomicStore64(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (AtomicStore64 ptr val mem)
	// result: (Select1 (XCHGQ <types.NewTuple(typ.UInt64,types.TypeMem)> val ptr mem))
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64XCHGQ, types.NewTuple(typ.UInt64, types.TypeMem))
		v0.AddArg3(val, ptr, mem)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpAtomicStore8(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (AtomicStore8 ptr val mem)
	// result: (Select1 (XCHGB <types.NewTuple(typ.UInt8,types.TypeMem)> val ptr mem))
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64XCHGB, types.NewTuple(typ.UInt8, types.TypeMem))
		v0.AddArg3(val, ptr, mem)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpAtomicStorePtrNoWB(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (AtomicStorePtrNoWB ptr val mem)
	// result: (Select1 (XCHGQ <types.NewTuple(typ.BytePtr,types.TypeMem)> val ptr mem))
	for {
		ptr := v_0
		val := v_1
		mem := v_2
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64XCHGQ, types.NewTuple(typ.BytePtr, types.TypeMem))
		v0.AddArg3(val, ptr, mem)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpBitLen16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (BitLen16 x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (BSRL (LEAL1 <typ.UInt32> [1] (MOVWQZX <typ.UInt32> x) (MOVWQZX <typ.UInt32> x)))
	for {
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpAMD64BSRL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64LEAL1, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWQZX, typ.UInt32)
		v1.AddArg(x)
		v0.AddArg2(v1, v1)
		v.AddArg(v0)
		return true
	}
	// match: (BitLen16 <t> x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVWQZX <x.Type> x))))
	for {
		t := v.Type
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64NEGQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ADDQconst, t)
		v0.AuxInt = ssa.Int32ToAuxInt(-32)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64LZCNTL, typ.UInt32)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWQZX, x.Type)
		v2.AddArg(x)
		v1.AddArg(v2)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpBitLen32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (BitLen32 x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (Select0 (BSRQ (LEAQ1 <typ.UInt64> [1] (MOVLQZX <typ.UInt64> x) (MOVLQZX <typ.UInt64> x))))
	for {
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64LEAQ1, typ.UInt64)
		v1.AuxInt = ssa.Int32ToAuxInt(1)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLQZX, typ.UInt64)
		v2.AddArg(x)
		v1.AddArg2(v2, v2)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	// match: (BitLen32 <t> x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL x)))
	for {
		t := v.Type
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64NEGQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ADDQconst, t)
		v0.AuxInt = ssa.Int32ToAuxInt(-32)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64LZCNTL, typ.UInt32)
		v1.AddArg(x)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpBitLen64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (BitLen64 <t> x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (ADDQconst [1] (CMOVQEQ <t> (Select0 <t> (BSRQ x)) (MOVQconst <t> [-1]) (Select1 <types.TypeFlags> (BSRQ x))))
	for {
		t := v.Type
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMOVQEQ, t)
		v1 := b.NewValue0(v.Pos, ssaop.OpSelect0, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64BSRQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v2.AddArg(x)
		v1.AddArg(v2)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, t)
		v3.AuxInt = ssa.Int64ToAuxInt(-1)
		v4 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v4.AddArg(v2)
		v0.AddArg3(v1, v3, v4)
		v.AddArg(v0)
		return true
	}
	// match: (BitLen64 <t> x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (NEGQ (ADDQconst <t> [-64] (LZCNTQ x)))
	for {
		t := v.Type
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64NEGQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ADDQconst, t)
		v0.AuxInt = ssa.Int32ToAuxInt(-64)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64LZCNTQ, typ.UInt64)
		v1.AddArg(x)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpBitLen8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (BitLen8 x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (BSRL (LEAL1 <typ.UInt32> [1] (MOVBQZX <typ.UInt32> x) (MOVBQZX <typ.UInt32> x)))
	for {
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpAMD64BSRL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64LEAL1, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(1)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBQZX, typ.UInt32)
		v1.AddArg(x)
		v0.AddArg2(v1, v1)
		v.AddArg(v0)
		return true
	}
	// match: (BitLen8 <t> x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (NEGQ (ADDQconst <t> [-32] (LZCNTL (MOVBQZX <x.Type> x))))
	for {
		t := v.Type
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64NEGQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ADDQconst, t)
		v0.AuxInt = ssa.Int32ToAuxInt(-32)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64LZCNTL, typ.UInt32)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBQZX, x.Type)
		v2.AddArg(x)
		v1.AddArg(v2)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpBswap16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Bswap16 x)
	// result: (ROLWconst [8] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64ROLWconst)
		v.AuxInt = ssa.Int8ToAuxInt(8)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeil(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Ceil x)
	// result: (ROUNDSD [2] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64ROUNDSD)
		v.AuxInt = ssa.Int8ToAuxInt(2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilFloat32x4 x)
	// result: (VROUNDPS128 [2] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilFloat32x8 x)
	// result: (VROUNDPS256 [2] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilFloat64x2 x)
	// result: (VROUNDPD128 [2] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilFloat64x4 x)
	// result: (VROUNDPD256 [2] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledFloat32x16 [a] x)
	// result: (VRNDSCALEPS512 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledFloat32x4 [a] x)
	// result: (VRNDSCALEPS128 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledFloat32x8 [a] x)
	// result: (VRNDSCALEPS256 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledFloat64x2 [a] x)
	// result: (VRNDSCALEPD128 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledFloat64x4 [a] x)
	// result: (VRNDSCALEPD256 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledFloat64x8 [a] x)
	// result: (VRNDSCALEPD512 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledResidueFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledResidueFloat32x16 [a] x)
	// result: (VREDUCEPS512 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledResidueFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledResidueFloat32x4 [a] x)
	// result: (VREDUCEPS128 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledResidueFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledResidueFloat32x8 [a] x)
	// result: (VREDUCEPS256 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledResidueFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledResidueFloat64x2 [a] x)
	// result: (VREDUCEPD128 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledResidueFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledResidueFloat64x4 [a] x)
	// result: (VREDUCEPD256 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCeilScaledResidueFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (CeilScaledResidueFloat64x8 [a] x)
	// result: (VREDUCEPD512 [a+2] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 2)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpCompressFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressFloat32x16 x mask)
	// result: (VCOMPRESSPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VCOMPRESSPSMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressFloat32x4 x mask)
	// result: (VCOMPRESSPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VCOMPRESSPSMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressFloat32x8 x mask)
	// result: (VCOMPRESSPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VCOMPRESSPSMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressFloat64x2 x mask)
	// result: (VCOMPRESSPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VCOMPRESSPDMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressFloat64x4 x mask)
	// result: (VCOMPRESSPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VCOMPRESSPDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressFloat64x8 x mask)
	// result: (VCOMPRESSPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VCOMPRESSPDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt16x16 x mask)
	// result: (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSWMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt16x32 x mask)
	// result: (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSWMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt16x8 x mask)
	// result: (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSWMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt32x16 x mask)
	// result: (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt32x4 x mask)
	// result: (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSDMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt32x8 x mask)
	// result: (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt64x2 x mask)
	// result: (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSQMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt64x4 x mask)
	// result: (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSQMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt64x8 x mask)
	// result: (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSQMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt8x16 x mask)
	// result: (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSBMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt8x32 x mask)
	// result: (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSBMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressInt8x64 x mask)
	// result: (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSBMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x64ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint16x16 x mask)
	// result: (VPCOMPRESSWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSWMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint16x32 x mask)
	// result: (VPCOMPRESSWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSWMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint16x8 x mask)
	// result: (VPCOMPRESSWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSWMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint32x16 x mask)
	// result: (VPCOMPRESSDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint32x4 x mask)
	// result: (VPCOMPRESSDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSDMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint32x8 x mask)
	// result: (VPCOMPRESSDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint64x2 x mask)
	// result: (VPCOMPRESSQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSQMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint64x4 x mask)
	// result: (VPCOMPRESSQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSQMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint64x8 x mask)
	// result: (VPCOMPRESSQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSQMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint8x16 x mask)
	// result: (VPCOMPRESSBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSBMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint8x32 x mask)
	// result: (VPCOMPRESSBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSBMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCompressUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CompressUint8x64 x mask)
	// result: (VPCOMPRESSBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPCOMPRESSBMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x64ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpCondSelect(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (CondSelect <t> x y (SETEQ cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQEQ y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETEQ {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQEQ)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETNE cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQNE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETNE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQNE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETL cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQLT y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETL {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQLT)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETG cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQGT y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETG {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQGT)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETLE cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQLE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETLE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQLE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGE cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQGE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQGE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETA cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQHI y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETA {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQHI)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETB cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQCS y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETB {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQCS)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETAE cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQCC y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETAE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQCC)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETBE cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQLS y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETBE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQLS)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETEQF cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQEQF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETEQF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQEQF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETNEF cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQNEF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETNEF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQNEF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGF cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQGTF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQGTF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGEF cond))
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQGEF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGEF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQGEF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETEQ cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLEQ y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETEQ {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLEQ)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETNE cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLNE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETNE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLNE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETL cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLLT y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETL {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLLT)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETG cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLGT y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETG {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLGT)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETLE cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLLE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETLE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLLE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGE cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLGE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLGE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETA cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLHI y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETA {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLHI)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETB cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLCS y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETB {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLCS)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETAE cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLCC y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETAE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLCC)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETBE cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLLS y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETBE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLLS)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETEQF cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLEQF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETEQF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLEQF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETNEF cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLNEF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETNEF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLNEF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGF cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLGTF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLGTF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGEF cond))
	// cond: ssa.Is32BitInt(t)
	// result: (CMOVLGEF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGEF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLGEF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETEQ cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWEQ y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETEQ {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWEQ)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETNE cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWNE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETNE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWNE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETL cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWLT y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETL {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWLT)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETG cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWGT y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETG {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWGT)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETLE cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWLE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETLE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWLE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGE cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWGE y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWGE)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETA cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWHI y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETA {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWHI)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETB cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWCS y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETB {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWCS)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETAE cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWCC y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETAE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWCC)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETBE cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWLS y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETBE {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWLS)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETEQF cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWEQF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETEQF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWEQF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETNEF cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWNEF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETNEF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWNEF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGF cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWGTF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWGTF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y (SETGEF cond))
	// cond: ssa.Is16BitInt(t)
	// result: (CMOVWGEF y x cond)
	for {
		t := v.Type
		x := v_0
		y := v_1
		if v_2.Op != ssaop.OpAMD64SETGEF {
			break
		}
		cond := v_2.Args[0]
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWGEF)
		v.AddArg3(y, x, cond)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQNE y x (CMPQconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && (ssa.Is64BitInt(t) || ssa.IsPtr(t))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && ssa.Is32BitInt(t)
	// result: (CMOVLNE y x (CMPQconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 8 && ssa.Is16BitInt(t)
	// result: (CMOVWNE y x (CMPQconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 8 && ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 4 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQNE y x (CMPLconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 4 && (ssa.Is64BitInt(t) || ssa.IsPtr(t))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 4 && ssa.Is32BitInt(t)
	// result: (CMOVLNE y x (CMPLconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 4 && ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 4 && ssa.Is16BitInt(t)
	// result: (CMOVWNE y x (CMPLconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 4 && ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 2 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQNE y x (CMPWconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 2 && (ssa.Is64BitInt(t) || ssa.IsPtr(t))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v0.AuxInt = ssa.Int16ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 2 && ssa.Is32BitInt(t)
	// result: (CMOVLNE y x (CMPWconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 2 && ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v0.AuxInt = ssa.Int16ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 2 && ssa.Is16BitInt(t)
	// result: (CMOVWNE y x (CMPWconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 2 && ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v0.AuxInt = ssa.Int16ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 1 && (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (CMOVQNE y x (CMPBconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 1 && (ssa.Is64BitInt(t) || ssa.IsPtr(t))) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 1 && ssa.Is32BitInt(t)
	// result: (CMOVLNE y x (CMPBconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 1 && ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVLNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	// match: (CondSelect <t> x y check)
	// cond: !check.Type.IsFlags() && check.Type.Size() == 1 && ssa.Is16BitInt(t)
	// result: (CMOVWNE y x (CMPBconst [0] check))
	for {
		t := v.Type
		x := v_0
		y := v_1
		check := v_2
		if !(!check.Type.IsFlags() && check.Type.Size() == 1 && ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVWNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v0.AuxInt = ssa.Int8ToAuxInt(0)
		v0.AddArg(check)
		v.AddArg3(y, x, v0)
		return true
	}
	return false
}
func rewriteValue_OpConst16(v *ssa.Value) bool {
	// match: (Const16 [c])
	// result: (MOVLconst [int32(c)])
	for {
		c := ssa.AuxIntToInt16(v.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(c))
		return true
	}
}
func rewriteValue_OpConst8(v *ssa.Value) bool {
	// match: (Const8 [c])
	// result: (MOVLconst [int32(c)])
	for {
		c := ssa.AuxIntToInt8(v.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(c))
		return true
	}
}
func rewriteValue_OpConstBool(v *ssa.Value) bool {
	// match: (ConstBool [c])
	// result: (MOVLconst [ssa.B2i32(c)])
	for {
		c := ssa.AuxIntToBool(v.AuxInt)
		v.Reset(ssaop.OpAMD64MOVLconst)
		v.AuxInt = ssa.Int32ToAuxInt(ssa.B2i32(c))
		return true
	}
}
func rewriteValue_OpConstNil(v *ssa.Value) bool {
	// match: (ConstNil )
	// result: (MOVQconst [0])
	for {
		v.Reset(ssaop.OpAMD64MOVQconst)
		v.AuxInt = ssa.Int64ToAuxInt(0)
		return true
	}
}
func rewriteValue_OpCtz16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Ctz16 x)
	// result: (BSFL (ORLconst <typ.UInt32> [1<<16] x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64BSFL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORLconst, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(1 << 16)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCtz16NonZero(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Ctz16NonZero x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (TZCNTL x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64TZCNTL)
		v.AddArg(x)
		return true
	}
	// match: (Ctz16NonZero x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (BSFL x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpAMD64BSFL)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpCtz32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Ctz32 x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (TZCNTL x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64TZCNTL)
		v.AddArg(x)
		return true
	}
	// match: (Ctz32 x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (Select0 (BSFQ (BTSQconst <typ.UInt64> [32] x)))
	for {
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64BTSQconst, typ.UInt64)
		v1.AuxInt = ssa.Int8ToAuxInt(32)
		v1.AddArg(x)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpCtz32NonZero(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Ctz32NonZero x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (TZCNTL x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64TZCNTL)
		v.AddArg(x)
		return true
	}
	// match: (Ctz32NonZero x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (BSFL x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpAMD64BSFL)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpCtz64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Ctz64 x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (TZCNTQ x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64TZCNTQ)
		v.AddArg(x)
		return true
	}
	// match: (Ctz64 <t> x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (CMOVQEQ (Select0 <t> (BSFQ x)) (MOVQconst <t> [64]) (Select1 <types.TypeFlags> (BSFQ x)))
	for {
		t := v.Type
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpAMD64CMOVQEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, t)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v1.AddArg(x)
		v0.AddArg(v1)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, t)
		v2.AuxInt = ssa.Int64ToAuxInt(64)
		v3 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v3.AddArg(v1)
		v.AddArg3(v0, v2, v3)
		return true
	}
	return false
}
func rewriteValue_OpCtz64NonZero(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Ctz64NonZero x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (TZCNTQ x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64TZCNTQ)
		v.AddArg(x)
		return true
	}
	// match: (Ctz64NonZero x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (Select0 (BSFQ x))
	for {
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64BSFQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
	return false
}
func rewriteValue_OpCtz8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Ctz8 x)
	// result: (BSFL (ORLconst <typ.UInt32> [1<<8 ] x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64BSFL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORLconst, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(1 << 8)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCtz8NonZero(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Ctz8NonZero x)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (TZCNTL x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64TZCNTL)
		v.AddArg(x)
		return true
	}
	// match: (Ctz8NonZero x)
	// cond: buildcfg.GOAMD64 < 3
	// result: (BSFL x)
	for {
		x := v_0
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpAMD64BSFL)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpCvt16toMask16x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt16toMask16x16 <t> x)
	// result: (VPMOVMToVec16x16 <types.TypeVec256> (KMOVWk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x16)
		v.Type = types.TypeVec256
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVWk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt16toMask32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt16toMask32x16 <t> x)
	// result: (VPMOVMToVec32x16 <types.TypeVec512> (KMOVWk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v.Type = types.TypeVec512
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVWk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt16toMask8x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt16toMask8x16 <t> x)
	// result: (VPMOVMToVec8x16 <types.TypeVec128> (KMOVWk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x16)
		v.Type = types.TypeVec128
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVWk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt32Fto32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Cvt32Fto32 <t> x)
	// cond: base.ConvertHash.MatchPos(v.Pos, nil)
	// result: (XORL <t> y (SARLconst <t> [31] (ANDL <t> y:(CVTTSS2SL <t> x) (NOTL <typ.Int32> (MOVLf2i x)))))
	for {
		t := v.Type
		x := v_0
		if !(base.ConvertHash.MatchPos(v.Pos, nil)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORL)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SARLconst, t)
		v0.AuxInt = ssa.Int8ToAuxInt(31)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64ANDL, t)
		y := b.NewValue0(v.Pos, ssaop.OpAMD64CVTTSS2SL, t)
		y.AddArg(x)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, typ.Int32)
		v4 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLf2i, typ.UInt32)
		v4.AddArg(x)
		v3.AddArg(v4)
		v1.AddArg2(y, v3)
		v0.AddArg(v1)
		v.AddArg2(y, v0)
		return true
	}
	// match: (Cvt32Fto32 <t> x)
	// cond: !base.ConvertHash.MatchPos(v.Pos, nil)
	// result: (CVTTSS2SL <t> x)
	for {
		t := v.Type
		x := v_0
		if !(!base.ConvertHash.MatchPos(v.Pos, nil)) {
			break
		}
		v.Reset(ssaop.OpAMD64CVTTSS2SL)
		v.Type = t
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpCvt32Fto64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Cvt32Fto64 <t> x)
	// cond: base.ConvertHash.MatchPos(v.Pos, nil)
	// result: (XORQ <t> y (SARQconst <t> [63] (ANDQ <t> y:(CVTTSS2SQ <t> x) (NOTQ <typ.Int64> (MOVQf2i (CVTSS2SD <typ.Float64> x))) )))
	for {
		t := v.Type
		x := v_0
		if !(base.ConvertHash.MatchPos(v.Pos, nil)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQ)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SARQconst, t)
		v0.AuxInt = ssa.Int8ToAuxInt(63)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64ANDQ, t)
		y := b.NewValue0(v.Pos, ssaop.OpAMD64CVTTSS2SQ, t)
		y.AddArg(x)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTQ, typ.Int64)
		v4 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQf2i, typ.UInt64)
		v5 := b.NewValue0(v.Pos, ssaop.OpAMD64CVTSS2SD, typ.Float64)
		v5.AddArg(x)
		v4.AddArg(v5)
		v3.AddArg(v4)
		v1.AddArg2(y, v3)
		v0.AddArg(v1)
		v.AddArg2(y, v0)
		return true
	}
	// match: (Cvt32Fto64 <t> x)
	// cond: !base.ConvertHash.MatchPos(v.Pos, nil)
	// result: (CVTTSS2SQ <t> x)
	for {
		t := v.Type
		x := v_0
		if !(!base.ConvertHash.MatchPos(v.Pos, nil)) {
			break
		}
		v.Reset(ssaop.OpAMD64CVTTSS2SQ)
		v.Type = t
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpCvt32toMask16x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt32toMask16x32 <t> x)
	// result: (VPMOVMToVec16x32 <types.TypeVec512> (KMOVDk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v.Type = types.TypeVec512
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVDk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt32toMask8x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt32toMask8x32 <t> x)
	// result: (VPMOVMToVec8x32 <types.TypeVec256> (KMOVDk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x32)
		v.Type = types.TypeVec256
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVDk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt64Fto32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Cvt64Fto32 <t> x)
	// cond: base.ConvertHash.MatchPos(v.Pos, nil)
	// result: (XORL <t> y (SARLconst <t> [31] (ANDL <t> y:(CVTTSD2SL <t> x) (NOTL <typ.Int32> (MOVLf2i (CVTSD2SS <typ.Float32> x))))))
	for {
		t := v.Type
		x := v_0
		if !(base.ConvertHash.MatchPos(v.Pos, nil)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORL)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SARLconst, t)
		v0.AuxInt = ssa.Int8ToAuxInt(31)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64ANDL, t)
		y := b.NewValue0(v.Pos, ssaop.OpAMD64CVTTSD2SL, t)
		y.AddArg(x)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, typ.Int32)
		v4 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLf2i, typ.UInt32)
		v5 := b.NewValue0(v.Pos, ssaop.OpAMD64CVTSD2SS, typ.Float32)
		v5.AddArg(x)
		v4.AddArg(v5)
		v3.AddArg(v4)
		v1.AddArg2(y, v3)
		v0.AddArg(v1)
		v.AddArg2(y, v0)
		return true
	}
	// match: (Cvt64Fto32 <t> x)
	// cond: !base.ConvertHash.MatchPos(v.Pos, nil)
	// result: (CVTTSD2SL <t> x)
	for {
		t := v.Type
		x := v_0
		if !(!base.ConvertHash.MatchPos(v.Pos, nil)) {
			break
		}
		v.Reset(ssaop.OpAMD64CVTTSD2SL)
		v.Type = t
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpCvt64Fto64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Cvt64Fto64 <t> x)
	// cond: base.ConvertHash.MatchPos(v.Pos, nil)
	// result: (XORQ <t> y (SARQconst <t> [63] (ANDQ <t> y:(CVTTSD2SQ <t> x) (NOTQ <typ.Int64> (MOVQf2i x)))))
	for {
		t := v.Type
		x := v_0
		if !(base.ConvertHash.MatchPos(v.Pos, nil)) {
			break
		}
		v.Reset(ssaop.OpAMD64XORQ)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SARQconst, t)
		v0.AuxInt = ssa.Int8ToAuxInt(63)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64ANDQ, t)
		y := b.NewValue0(v.Pos, ssaop.OpAMD64CVTTSD2SQ, t)
		y.AddArg(x)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTQ, typ.Int64)
		v4 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQf2i, typ.UInt64)
		v4.AddArg(x)
		v3.AddArg(v4)
		v1.AddArg2(y, v3)
		v0.AddArg(v1)
		v.AddArg2(y, v0)
		return true
	}
	// match: (Cvt64Fto64 <t> x)
	// cond: !base.ConvertHash.MatchPos(v.Pos, nil)
	// result: (CVTTSD2SQ <t> x)
	for {
		t := v.Type
		x := v_0
		if !(!base.ConvertHash.MatchPos(v.Pos, nil)) {
			break
		}
		v.Reset(ssaop.OpAMD64CVTTSD2SQ)
		v.Type = t
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpCvt64toMask8x64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt64toMask8x64 <t> x)
	// result: (VPMOVMToVec8x64 <types.TypeVec512> (KMOVQk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v.Type = types.TypeVec512
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVQk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt8toMask16x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt8toMask16x8 <t> x)
	// result: (VPMOVMToVec16x8 <types.TypeVec128> (KMOVBk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x8)
		v.Type = types.TypeVec128
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVBk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt8toMask32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt8toMask32x4 <t> x)
	// result: (VPMOVMToVec32x4 <types.TypeVec128> (KMOVBk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x4)
		v.Type = types.TypeVec128
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVBk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt8toMask32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt8toMask32x8 <t> x)
	// result: (VPMOVMToVec32x8 <types.TypeVec256> (KMOVBk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x8)
		v.Type = types.TypeVec256
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVBk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt8toMask64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt8toMask64x2 <t> x)
	// result: (VPMOVMToVec64x2 <types.TypeVec128> (KMOVBk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x2)
		v.Type = types.TypeVec128
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVBk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt8toMask64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt8toMask64x4 <t> x)
	// result: (VPMOVMToVec64x4 <types.TypeVec256> (KMOVBk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x4)
		v.Type = types.TypeVec256
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVBk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvt8toMask64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Cvt8toMask64x8 <t> x)
	// result: (VPMOVMToVec64x8 <types.TypeVec512> (KMOVBk <t> x))
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v.Type = types.TypeVec512
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64KMOVBk, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvtMask16x16to16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CvtMask16x16to16 x)
	// result: (KMOVWi (VPMOVVec16x16ToM <types.TypeMask> x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64KMOVWi)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvtMask16x32to32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CvtMask16x32to32 x)
	// result: (KMOVDi (VPMOVVec16x32ToM <types.TypeMask> x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64KMOVDi)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x32ToM, types.TypeMask)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvtMask16x8to8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CvtMask16x8to8 x)
	// result: (KMOVBi (VPMOVVec16x8ToM <types.TypeMask> x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64KMOVBi)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvtMask32x16to16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CvtMask32x16to16 x)
	// result: (KMOVWi (VPMOVVec32x16ToM <types.TypeMask> x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64KMOVWi)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvtMask64x8to8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CvtMask64x8to8 x)
	// result: (KMOVBi (VPMOVVec64x8ToM <types.TypeMask> x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64KMOVBi)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpCvtMask8x64to64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (CvtMask8x64to64 x)
	// result: (KMOVQi (VPMOVVec8x64ToM <types.TypeMask> x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64KMOVQi)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x64ToM, types.TypeMask)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpDiv16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Div16 [a] x y)
	// result: (Select0 (DIVW [a] x y))
	for {
		a := ssa.AuxIntToBool(v.AuxInt)
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
		v0.AuxInt = ssa.BoolToAuxInt(a)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpDiv16u(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Div16u x y)
	// result: (Select0 (DIVWU x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpDiv32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Div32 [a] x y)
	// result: (Select0 (DIVL [a] x y))
	for {
		a := ssa.AuxIntToBool(v.AuxInt)
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
		v0.AuxInt = ssa.BoolToAuxInt(a)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpDiv32u(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Div32u x y)
	// result: (Select0 (DIVLU x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpDiv64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Div64 [a] x y)
	// result: (Select0 (DIVQ [a] x y))
	for {
		a := ssa.AuxIntToBool(v.AuxInt)
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
		v0.AuxInt = ssa.BoolToAuxInt(a)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpDiv64u(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Div64u x y)
	// result: (Select0 (DIVQU x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpDiv8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Div8 x y)
	// result: (Select0 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
		v1 := b.NewValue0(v.Pos, ssaop.OpSignExt8to16, typ.Int16)
		v1.AddArg(x)
		v2 := b.NewValue0(v.Pos, ssaop.OpSignExt8to16, typ.Int16)
		v2.AddArg(y)
		v0.AddArg2(v1, v2)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpDiv8u(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Div8u x y)
	// result: (Select0 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
		v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to16, typ.UInt16)
		v1.AddArg(x)
		v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to16, typ.UInt16)
		v2.AddArg(y)
		v0.AddArg2(v1, v2)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEq16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Eq16 x y)
	// result: (SETEQ (CMPW x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPW, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEq32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Eq32 x y)
	// result: (SETEQ (CMPL x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPL, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEq32F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Eq32F x y)
	// result: (SETEQF (UCOMISS x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETEQF)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64UCOMISS, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEq64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Eq64 x y)
	// result: (SETEQ (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEq64F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Eq64F x y)
	// result: (SETEQF (UCOMISD x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETEQF)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64UCOMISD, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEq8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Eq8 x y)
	// result: (SETEQ (CMPB x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (EqB x y)
	// result: (SETEQ (CMPB x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqPtr(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (EqPtr x y)
	// result: (SETEQ (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualFloat32x16 x y)
	// result: (VPMOVMToVec32x16 (VCMPPS512 [0] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPS512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(0)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (EqualFloat32x4 x y)
	// result: (VCMPPS128 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpEqualFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (EqualFloat32x8 x y)
	// result: (VCMPPS256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpEqualFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (EqualFloat64x2 x y)
	// result: (VCMPPD128 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpEqualFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (EqualFloat64x4 x y)
	// result: (VCMPPD256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpEqualFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualFloat64x8 x y)
	// result: (VPMOVMToVec64x8 (VCMPPD512 [0] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(0)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualInt16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPEQW512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPEQW512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualInt32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPEQD512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPEQD512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualInt64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPEQQ512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPEQQ512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualInt8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPEQB512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPEQB512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualUint16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPEQW512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPEQW512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualUint32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPEQD512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPEQD512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualUint64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPEQQ512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPEQQ512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpEqualUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (EqualUint8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPEQB512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPEQB512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpExpandFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandFloat32x16 x mask)
	// result: (VEXPANDPSMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VEXPANDPSMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandFloat32x4 x mask)
	// result: (VEXPANDPSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VEXPANDPSMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandFloat32x8 x mask)
	// result: (VEXPANDPSMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VEXPANDPSMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandFloat64x2 x mask)
	// result: (VEXPANDPDMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VEXPANDPDMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandFloat64x4 x mask)
	// result: (VEXPANDPDMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VEXPANDPDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandFloat64x8 x mask)
	// result: (VEXPANDPDMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VEXPANDPDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt16x16 x mask)
	// result: (VPEXPANDWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDWMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt16x32 x mask)
	// result: (VPEXPANDWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDWMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt16x8 x mask)
	// result: (VPEXPANDWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDWMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt32x16 x mask)
	// result: (VPEXPANDDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt32x4 x mask)
	// result: (VPEXPANDDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDDMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt32x8 x mask)
	// result: (VPEXPANDDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt64x2 x mask)
	// result: (VPEXPANDQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDQMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt64x4 x mask)
	// result: (VPEXPANDQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDQMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt64x8 x mask)
	// result: (VPEXPANDQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDQMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt8x16 x mask)
	// result: (VPEXPANDBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDBMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt8x32 x mask)
	// result: (VPEXPANDBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDBMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandInt8x64 x mask)
	// result: (VPEXPANDBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDBMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x64ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint16x16 x mask)
	// result: (VPEXPANDWMasked256 x (VPMOVVec16x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDWMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint16x32 x mask)
	// result: (VPEXPANDWMasked512 x (VPMOVVec16x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDWMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint16x8 x mask)
	// result: (VPEXPANDWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDWMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint32x16 x mask)
	// result: (VPEXPANDDMasked512 x (VPMOVVec32x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint32x4 x mask)
	// result: (VPEXPANDDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDDMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint32x8 x mask)
	// result: (VPEXPANDDMasked256 x (VPMOVVec32x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint64x2 x mask)
	// result: (VPEXPANDQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDQMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint64x4 x mask)
	// result: (VPEXPANDQMasked256 x (VPMOVVec64x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDQMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint64x8 x mask)
	// result: (VPEXPANDQMasked512 x (VPMOVVec64x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDQMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint8x16 x mask)
	// result: (VPEXPANDBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDBMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint8x32 x mask)
	// result: (VPEXPANDBMasked256 x (VPMOVVec8x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDBMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpExpandUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (ExpandUint8x64 x mask)
	// result: (VPEXPANDBMasked512 x (VPMOVVec8x64ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPEXPANDBMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x64ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpFMA(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (FMA x y z)
	// result: (VFMADD231SD z x y)
	for {
		x := v_0
		y := v_1
		z := v_2
		v.Reset(ssaop.OpAMD64VFMADD231SD)
		v.AddArg3(z, x, y)
		return true
	}
}
func rewriteValue_OpFloor(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Floor x)
	// result: (ROUNDSD [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64ROUNDSD)
		v.AuxInt = ssa.Int8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorFloat32x4 x)
	// result: (VROUNDPS128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorFloat32x8 x)
	// result: (VROUNDPS256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorFloat64x2 x)
	// result: (VROUNDPD128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorFloat64x4 x)
	// result: (VROUNDPD256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledFloat32x16 [a] x)
	// result: (VRNDSCALEPS512 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledFloat32x4 [a] x)
	// result: (VRNDSCALEPS128 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledFloat32x8 [a] x)
	// result: (VRNDSCALEPS256 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledFloat64x2 [a] x)
	// result: (VRNDSCALEPD128 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledFloat64x4 [a] x)
	// result: (VRNDSCALEPD256 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledFloat64x8 [a] x)
	// result: (VRNDSCALEPD512 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledResidueFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledResidueFloat32x16 [a] x)
	// result: (VREDUCEPS512 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledResidueFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledResidueFloat32x4 [a] x)
	// result: (VREDUCEPS128 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledResidueFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledResidueFloat32x8 [a] x)
	// result: (VREDUCEPS256 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledResidueFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledResidueFloat64x2 [a] x)
	// result: (VREDUCEPD128 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledResidueFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledResidueFloat64x4 [a] x)
	// result: (VREDUCEPD256 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpFloorScaledResidueFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (FloorScaledResidueFloat64x8 [a] x)
	// result: (VREDUCEPD512 [a+1] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetG(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetG mem)
	// cond: v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal
	// result: (LoweredGetG mem)
	for {
		mem := v_0
		if !(v.Block.Func.OwnAux.Fn.ABI() != obj.ABIInternal) {
			break
		}
		v.Reset(ssaop.OpAMD64LoweredGetG)
		v.AddArg(mem)
		return true
	}
	return false
}
func rewriteValue_OpGetHiFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiFloat32x16 x)
	// result: (VEXTRACTF64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTF64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiFloat32x8 x)
	// result: (VEXTRACTF128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTF128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiFloat64x4 x)
	// result: (VEXTRACTF128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTF128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiFloat64x8 x)
	// result: (VEXTRACTF64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTF64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiInt16x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiInt16x16 x)
	// result: (VEXTRACTI128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiInt16x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiInt16x32 x)
	// result: (VEXTRACTI64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiInt32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiInt32x16 x)
	// result: (VEXTRACTI64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiInt32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiInt32x8 x)
	// result: (VEXTRACTI128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiInt64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiInt64x4 x)
	// result: (VEXTRACTI128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiInt64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiInt64x8 x)
	// result: (VEXTRACTI64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiInt8x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiInt8x32 x)
	// result: (VEXTRACTI128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiInt8x64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiInt8x64 x)
	// result: (VEXTRACTI64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiUint16x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiUint16x16 x)
	// result: (VEXTRACTI128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiUint16x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiUint16x32 x)
	// result: (VEXTRACTI64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiUint32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiUint32x16 x)
	// result: (VEXTRACTI64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiUint32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiUint32x8 x)
	// result: (VEXTRACTI128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiUint64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiUint64x4 x)
	// result: (VEXTRACTI128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiUint64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiUint64x8 x)
	// result: (VEXTRACTI64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiUint8x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiUint8x32 x)
	// result: (VEXTRACTI128128 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetHiUint8x64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetHiUint8x64 x)
	// result: (VEXTRACTI64X4256 [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoFloat32x16 x)
	// result: (VEXTRACTF64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTF64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoFloat32x8 x)
	// result: (VEXTRACTF128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTF128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoFloat64x4 x)
	// result: (VEXTRACTF128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTF128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoFloat64x8 x)
	// result: (VEXTRACTF64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTF64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoInt16x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoInt16x16 x)
	// result: (VEXTRACTI128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoInt16x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoInt16x32 x)
	// result: (VEXTRACTI64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoInt32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoInt32x16 x)
	// result: (VEXTRACTI64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoInt32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoInt32x8 x)
	// result: (VEXTRACTI128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoInt64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoInt64x4 x)
	// result: (VEXTRACTI128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoInt64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoInt64x8 x)
	// result: (VEXTRACTI64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoInt8x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoInt8x32 x)
	// result: (VEXTRACTI128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoInt8x64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoInt8x64 x)
	// result: (VEXTRACTI64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoUint16x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoUint16x16 x)
	// result: (VEXTRACTI128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoUint16x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoUint16x32 x)
	// result: (VEXTRACTI64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoUint32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoUint32x16 x)
	// result: (VEXTRACTI64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoUint32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoUint32x8 x)
	// result: (VEXTRACTI128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoUint64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoUint64x4 x)
	// result: (VEXTRACTI128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoUint64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoUint64x8 x)
	// result: (VEXTRACTI64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoUint8x32(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoUint8x32 x)
	// result: (VEXTRACTI128128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI128128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGetLoUint8x64(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (GetLoUint8x64 x)
	// result: (VEXTRACTI64X4256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VEXTRACTI64X4256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpGreaterEqualFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualFloat32x16 x y)
	// result: (VPMOVMToVec32x16 (VCMPPS512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPS512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (GreaterEqualFloat32x4 x y)
	// result: (VCMPPS128 [13] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(13)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpGreaterEqualFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (GreaterEqualFloat32x8 x y)
	// result: (VCMPPS256 [13] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(13)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpGreaterEqualFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (GreaterEqualFloat64x2 x y)
	// result: (VCMPPD128 [13] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(13)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpGreaterEqualFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (GreaterEqualFloat64x4 x y)
	// result: (VCMPPD256 [13] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(13)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpGreaterEqualFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualFloat64x8 x y)
	// result: (VPMOVMToVec64x8 (VCMPPD512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualInt16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPW512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualInt32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPD512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualInt64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPQ512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualInt8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPB512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualUint16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPUW512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualUint32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPUD512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualUint64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterEqualUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterEqualUint8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPUB512 [13] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(13)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterFloat32x16 x y)
	// result: (VPMOVMToVec32x16 (VCMPPS512 [14] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPS512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(14)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (GreaterFloat32x4 x y)
	// result: (VCMPPS128 [14] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(14)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpGreaterFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (GreaterFloat32x8 x y)
	// result: (VCMPPS256 [14] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(14)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpGreaterFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (GreaterFloat64x2 x y)
	// result: (VCMPPD128 [14] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(14)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpGreaterFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (GreaterFloat64x4 x y)
	// result: (VCMPPD256 [14] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(14)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpGreaterFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterFloat64x8 x y)
	// result: (VPMOVMToVec64x8 (VCMPPD512 [14] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(14)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterInt16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPGTW512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPGTW512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterInt32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPGTD512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPGTD512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterInt64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPGTQ512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPGTQ512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterInt8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPGTB512 x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPGTB512, typ.Mask)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterUint16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPUW512 [14] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(14)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterUint32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPUD512 [14] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(14)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterUint64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [14] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(14)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpGreaterUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (GreaterUint8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPUB512 [14] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(14)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpHasCPUFeature(v *ssa.Value) bool {
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (HasCPUFeature {s})
	// result: (SETNE (CMPLconst [0] (LoweredHasCPUFeature {s})))
	for {
		s := ssa.AuxToSym(v.Aux)
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v0.AuxInt = ssa.Int32ToAuxInt(0)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64LoweredHasCPUFeature, typ.UInt64)
		v1.Aux = ssa.SymToAux(s)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpIsInBounds(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (IsInBounds idx len)
	// result: (SETB (CMPQ idx len))
	for {
		idx := v_0
		len := v_1
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(idx, len)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpIsNaNFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (IsNaNFloat32x16 x)
	// result: (VPMOVMToVec32x16 (VCMPPS512 [3] x x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPS512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(3)
		v0.AddArg2(x, x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpIsNaNFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (IsNaNFloat32x4 x)
	// result: (VCMPPS128 [3] x x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VCMPPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg2(x, x)
		return true
	}
}
func rewriteValue_OpIsNaNFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (IsNaNFloat32x8 x)
	// result: (VCMPPS256 [3] x x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VCMPPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg2(x, x)
		return true
	}
}
func rewriteValue_OpIsNaNFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (IsNaNFloat64x2 x)
	// result: (VCMPPD128 [3] x x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VCMPPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg2(x, x)
		return true
	}
}
func rewriteValue_OpIsNaNFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (IsNaNFloat64x4 x)
	// result: (VCMPPD256 [3] x x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VCMPPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg2(x, x)
		return true
	}
}
func rewriteValue_OpIsNaNFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (IsNaNFloat64x8 x)
	// result: (VPMOVMToVec64x8 (VCMPPD512 [3] x x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(3)
		v0.AddArg2(x, x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpIsNonNil(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (IsNonNil p)
	// result: (SETNE (TESTQ p p))
	for {
		p := v_0
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64TESTQ, types.TypeFlags)
		v0.AddArg2(p, p)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpIsSliceInBounds(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (IsSliceInBounds idx len)
	// result: (SETBE (CMPQ idx len))
	for {
		idx := v_0
		len := v_1
		v.Reset(ssaop.OpAMD64SETBE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(idx, len)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpIsZeroVec(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (IsZeroVec x)
	// result: (SETEQ (VPTEST x x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64SETEQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
		v0.AddArg2(x, x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq16 x y)
	// result: (SETLE (CMPW x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPW, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq16U(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq16U x y)
	// result: (SETBE (CMPW x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETBE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPW, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq32 x y)
	// result: (SETLE (CMPL x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPL, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq32F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq32F x y)
	// result: (SETGEF (UCOMISS y x))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETGEF)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64UCOMISS, types.TypeFlags)
		v0.AddArg2(y, x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq32U(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq32U x y)
	// result: (SETBE (CMPL x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETBE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPL, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq64 x y)
	// result: (SETLE (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq64F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq64F x y)
	// result: (SETGEF (UCOMISD y x))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETGEF)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64UCOMISD, types.TypeFlags)
		v0.AddArg2(y, x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq64U(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq64U x y)
	// result: (SETBE (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETBE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq8 x y)
	// result: (SETLE (CMPB x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETLE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLeq8U(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Leq8U x y)
	// result: (SETBE (CMPB x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETBE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less16 x y)
	// result: (SETL (CMPW x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPW, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess16U(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less16U x y)
	// result: (SETB (CMPW x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPW, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less32 x y)
	// result: (SETL (CMPL x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPL, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess32F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less32F x y)
	// result: (SETGF (UCOMISS y x))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETGF)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64UCOMISS, types.TypeFlags)
		v0.AddArg2(y, x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess32U(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less32U x y)
	// result: (SETB (CMPL x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPL, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less64 x y)
	// result: (SETL (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess64F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less64F x y)
	// result: (SETGF (UCOMISD y x))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETGF)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64UCOMISD, types.TypeFlags)
		v0.AddArg2(y, x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess64U(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less64U x y)
	// result: (SETB (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less8 x y)
	// result: (SETL (CMPB x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLess8U(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Less8U x y)
	// result: (SETB (CMPB x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETB)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualFloat32x16 x y)
	// result: (VPMOVMToVec32x16 (VCMPPS512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPS512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LessEqualFloat32x4 x y)
	// result: (VCMPPS128 [2] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(2)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpLessEqualFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LessEqualFloat32x8 x y)
	// result: (VCMPPS256 [2] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(2)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpLessEqualFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LessEqualFloat64x2 x y)
	// result: (VCMPPD128 [2] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(2)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpLessEqualFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LessEqualFloat64x4 x y)
	// result: (VCMPPD256 [2] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(2)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpLessEqualFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualFloat64x8 x y)
	// result: (VPMOVMToVec64x8 (VCMPPD512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualInt16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPW512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualInt32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPD512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualInt64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPQ512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualInt8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPB512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualUint16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPUW512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualUint32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPUD512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualUint64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessEqualUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessEqualUint8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPUB512 [2] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(2)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessFloat32x16 x y)
	// result: (VPMOVMToVec32x16 (VCMPPS512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPS512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LessFloat32x4 x y)
	// result: (VCMPPS128 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpLessFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LessFloat32x8 x y)
	// result: (VCMPPS256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpLessFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LessFloat64x2 x y)
	// result: (VCMPPD128 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpLessFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (LessFloat64x4 x y)
	// result: (VCMPPD256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpLessFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessFloat64x8 x y)
	// result: (VPMOVMToVec64x8 (VCMPPD512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessInt16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPW512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessInt32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPD512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessInt64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPQ512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessInt8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPB512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessUint16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPUW512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessUint32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPUD512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessUint64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLessUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LessUint8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPUB512 [1] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(1)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpLoad(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (Load <t> ptr mem)
	// cond: (ssa.Is64BitInt(t) ||ssa.IsPtr(t))
	// result: (MOVQload ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(ssa.Is64BitInt(t) || ssa.IsPtr(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQload)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (Load <t> ptr mem)
	// cond: ssa.Is32BitInt(t)
	// result: (MOVLload ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(ssa.Is32BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLload)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (Load <t> ptr mem)
	// cond: ssa.Is16BitInt(t)
	// result: (MOVWload ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(ssa.Is16BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWload)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (Load <t> ptr mem)
	// cond: (t.IsBoolean() || ssa.Is8BitInt(t))
	// result: (MOVBload ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(t.IsBoolean() || ssa.Is8BitInt(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBload)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (Load <t> ptr mem)
	// cond: ssa.Is32BitFloat(t)
	// result: (MOVSSload ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(ssa.Is32BitFloat(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSSload)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (Load <t> ptr mem)
	// cond: ssa.Is64BitFloat(t)
	// result: (MOVSDload ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(ssa.Is64BitFloat(t)) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSDload)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (Load <t> ptr mem)
	// cond: t.Size() == 16
	// result: (VMOVDQUload128 ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(t.Size() == 16) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload128)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (Load <t> ptr mem)
	// cond: t.Size() == 32
	// result: (VMOVDQUload256 ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(t.Size() == 32) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload256)
		v.AddArg2(ptr, mem)
		return true
	}
	// match: (Load <t> ptr mem)
	// cond: t.Size() == 64
	// result: (VMOVDQUload512 ptr mem)
	for {
		t := v.Type
		ptr := v_0
		mem := v_1
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUload512)
		v.AddArg2(ptr, mem)
		return true
	}
	return false
}
func rewriteValue_OpLoadMasked16(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (LoadMasked16 <t> ptr mask mem)
	// cond: t.Size() == 64
	// result: (VPMASK16load512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) mem)
	for {
		t := v.Type
		ptr := v_0
		mask := v_1
		mem := v_2
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK16load512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpLoadMasked32(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (LoadMasked32 <t> ptr mask mem)
	// cond: t.Size() == 16
	// result: (VPMASK32load128 ptr mask mem)
	for {
		t := v.Type
		ptr := v_0
		mask := v_1
		mem := v_2
		if !(t.Size() == 16) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK32load128)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	// match: (LoadMasked32 <t> ptr mask mem)
	// cond: t.Size() == 32
	// result: (VPMASK32load256 ptr mask mem)
	for {
		t := v.Type
		ptr := v_0
		mask := v_1
		mem := v_2
		if !(t.Size() == 32) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK32load256)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	// match: (LoadMasked32 <t> ptr mask mem)
	// cond: t.Size() == 64
	// result: (VPMASK32load512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) mem)
	for {
		t := v.Type
		ptr := v_0
		mask := v_1
		mem := v_2
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK32load512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpLoadMasked64(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (LoadMasked64 <t> ptr mask mem)
	// cond: t.Size() == 16
	// result: (VPMASK64load128 ptr mask mem)
	for {
		t := v.Type
		ptr := v_0
		mask := v_1
		mem := v_2
		if !(t.Size() == 16) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK64load128)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	// match: (LoadMasked64 <t> ptr mask mem)
	// cond: t.Size() == 32
	// result: (VPMASK64load256 ptr mask mem)
	for {
		t := v.Type
		ptr := v_0
		mask := v_1
		mem := v_2
		if !(t.Size() == 32) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK64load256)
		v.AddArg3(ptr, mask, mem)
		return true
	}
	// match: (LoadMasked64 <t> ptr mask mem)
	// cond: t.Size() == 64
	// result: (VPMASK64load512 ptr (VPMOVVec64x8ToM <types.TypeMask> mask) mem)
	for {
		t := v.Type
		ptr := v_0
		mask := v_1
		mem := v_2
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK64load512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpLoadMasked8(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (LoadMasked8 <t> ptr mask mem)
	// cond: t.Size() == 64
	// result: (VPMASK8load512 ptr (VPMOVVec8x64ToM <types.TypeMask> mask) mem)
	for {
		t := v.Type
		ptr := v_0
		mask := v_1
		mem := v_2
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK8load512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x64ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(ptr, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpLocalAddr(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (LocalAddr <t> {sym} base mem)
	// cond: t.Elem().HasPointers()
	// result: (LEAQ {sym} (SPanchored base mem))
	for {
		t := v.Type
		sym := ssa.AuxToSym(v.Aux)
		base := v_0
		mem := v_1
		if !(t.Elem().HasPointers()) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.Aux = ssa.SymToAux(sym)
		v0 := b.NewValue0(v.Pos, ssaop.OpSPanchored, typ.Uintptr)
		v0.AddArg2(base, mem)
		v.AddArg(v0)
		return true
	}
	// match: (LocalAddr <t> {sym} base _)
	// cond: !t.Elem().HasPointers()
	// result: (LEAQ {sym} base)
	for {
		t := v.Type
		sym := ssa.AuxToSym(v.Aux)
		base := v_0
		if !(!t.Elem().HasPointers()) {
			break
		}
		v.Reset(ssaop.OpAMD64LEAQ)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg(base)
		return true
	}
	return false
}
func rewriteValue_OpLsh16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh16x16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v2.AuxInt = ssa.Int16ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh16x16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh16x32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh16x32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh16x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh16x64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh16x64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh16x8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v2.AuxInt = ssa.Int8ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh16x8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh32x16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v2.AuxInt = ssa.Int16ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh32x16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh32x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh32x32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh32x32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh32x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh32x64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh32x64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh32x8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v2.AuxInt = ssa.Int8ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh32x8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh64x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh64x16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLQ, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v2.AuxInt = ssa.Int16ToAuxInt(64)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh64x16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh64x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh64x32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLQ, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(64)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh64x32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh64x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh64x64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLQ, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(64)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh64x64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh64x8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDQ (SHLQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLQ, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v2.AuxInt = ssa.Int8ToAuxInt(64)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh64x8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh8x16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v2.AuxInt = ssa.Int16ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh8x16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh8x32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh8x32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh8x64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh8x64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpLsh8x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Lsh8x8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHLL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHLL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v2.AuxInt = ssa.Int8ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Lsh8x8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHLL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHLL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpMax32F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Max32F <t> x y)
	// result: (Neg32F <t> (Min32F <t> (Neg32F <t> x) (Neg32F <t> y)))
	for {
		t := v.Type
		x := v_0
		y := v_1
		v.Reset(ssaop.OpNeg32F)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpMin32F, t)
		v1 := b.NewValue0(v.Pos, ssaop.OpNeg32F, t)
		v1.AddArg(x)
		v2 := b.NewValue0(v.Pos, ssaop.OpNeg32F, t)
		v2.AddArg(y)
		v0.AddArg2(v1, v2)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMax64F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Max64F <t> x y)
	// result: (Neg64F <t> (Min64F <t> (Neg64F <t> x) (Neg64F <t> y)))
	for {
		t := v.Type
		x := v_0
		y := v_1
		v.Reset(ssaop.OpNeg64F)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpMin64F, t)
		v1 := b.NewValue0(v.Pos, ssaop.OpNeg64F, t)
		v1.AddArg(x)
		v2 := b.NewValue0(v.Pos, ssaop.OpNeg64F, t)
		v2.AddArg(y)
		v0.AddArg2(v1, v2)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMin32F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Min32F <t> x y)
	// result: (POR (MINSS <t> (MINSS <t> x y) x) (MINSS <t> x y))
	for {
		t := v.Type
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64POR)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MINSS, t)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MINSS, t)
		v1.AddArg2(x, y)
		v0.AddArg2(v1, x)
		v.AddArg2(v0, v1)
		return true
	}
}
func rewriteValue_OpMin64F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Min64F <t> x y)
	// result: (POR (MINSD <t> (MINSD <t> x y) x) (MINSD <t> x y))
	for {
		t := v.Type
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64POR)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MINSD, t)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MINSD, t)
		v1.AddArg2(x, y)
		v0.AddArg2(v1, x)
		v.AddArg2(v0, v1)
		return true
	}
}
func rewriteValue_OpMod16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Mod16 [a] x y)
	// result: (Select1 (DIVW [a] x y))
	for {
		a := ssa.AuxIntToBool(v.AuxInt)
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
		v0.AuxInt = ssa.BoolToAuxInt(a)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMod16u(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Mod16u x y)
	// result: (Select1 (DIVWU x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMod32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Mod32 [a] x y)
	// result: (Select1 (DIVL [a] x y))
	for {
		a := ssa.AuxIntToBool(v.AuxInt)
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVL, types.NewTuple(typ.Int32, typ.Int32))
		v0.AuxInt = ssa.BoolToAuxInt(a)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMod32u(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Mod32u x y)
	// result: (Select1 (DIVLU x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVLU, types.NewTuple(typ.UInt32, typ.UInt32))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMod64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Mod64 [a] x y)
	// result: (Select1 (DIVQ [a] x y))
	for {
		a := ssa.AuxIntToBool(v.AuxInt)
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVQ, types.NewTuple(typ.Int64, typ.Int64))
		v0.AuxInt = ssa.BoolToAuxInt(a)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMod64u(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Mod64u x y)
	// result: (Select1 (DIVQU x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVQU, types.NewTuple(typ.UInt64, typ.UInt64))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMod8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Mod8 x y)
	// result: (Select1 (DIVW (SignExt8to16 x) (SignExt8to16 y)))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVW, types.NewTuple(typ.Int16, typ.Int16))
		v1 := b.NewValue0(v.Pos, ssaop.OpSignExt8to16, typ.Int16)
		v1.AddArg(x)
		v2 := b.NewValue0(v.Pos, ssaop.OpSignExt8to16, typ.Int16)
		v2.AddArg(y)
		v0.AddArg2(v1, v2)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMod8u(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Mod8u x y)
	// result: (Select1 (DIVWU (ZeroExt8to16 x) (ZeroExt8to16 y)))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpSelect1)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64DIVWU, types.NewTuple(typ.UInt16, typ.UInt16))
		v1 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to16, typ.UInt16)
		v1.AddArg(x)
		v2 := b.NewValue0(v.Pos, ssaop.OpZeroExt8to16, typ.UInt16)
		v2.AddArg(y)
		v0.AddArg2(v1, v2)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpMove(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Move [0] _ _ mem)
	// result: mem
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 0 {
			break
		}
		mem := v_2
		v.CopyOf(mem)
		return true
	}
	// match: (Move [1] dst src mem)
	// result: (MOVBstore dst (MOVBload src mem) mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 1 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBload, typ.UInt8)
		v0.AddArg2(src, mem)
		v.AddArg3(dst, v0, mem)
		return true
	}
	// match: (Move [2] dst src mem)
	// result: (MOVWstore dst (MOVWload src mem) mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 2 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVWstore)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWload, typ.UInt16)
		v0.AddArg2(src, mem)
		v.AddArg3(dst, v0, mem)
		return true
	}
	// match: (Move [4] dst src mem)
	// result: (MOVLstore dst (MOVLload src mem) mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 4 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstore)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v0.AddArg2(src, mem)
		v.AddArg3(dst, v0, mem)
		return true
	}
	// match: (Move [8] dst src mem)
	// result: (MOVQstore dst (MOVQload src mem) mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 8 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVQstore)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v0.AddArg2(src, mem)
		v.AddArg3(dst, v0, mem)
		return true
	}
	// match: (Move [16] dst src mem)
	// result: (MOVOstore dst (MOVOload src mem) mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 16 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVOstore)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVOload, types.TypeInt128)
		v0.AddArg2(src, mem)
		v.AddArg3(dst, v0, mem)
		return true
	}
	// match: (Move [3] dst src mem)
	// result: (MOVBstore [2] dst (MOVBload [2] src mem) (MOVWstore dst (MOVWload src mem) mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 3 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(2)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBload, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(2)
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWload, typ.UInt16)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [5] dst src mem)
	// result: (MOVBstore [4] dst (MOVBload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 5 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(4)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBload, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(4)
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [6] dst src mem)
	// result: (MOVWstore [4] dst (MOVWload [4] src mem) (MOVLstore dst (MOVLload src mem) mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 6 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVWstore)
		v.AuxInt = ssa.Int32ToAuxInt(4)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWload, typ.UInt16)
		v0.AuxInt = ssa.Int32ToAuxInt(4)
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [7] dst src mem)
	// result: (MOVLstore [3] dst (MOVLload [3] src mem) (MOVLstore dst (MOVLload src mem) mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 7 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(3)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(3)
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [9] dst src mem)
	// result: (MOVBstore [8] dst (MOVBload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 9 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AuxInt = ssa.Int32ToAuxInt(8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBload, typ.UInt8)
		v0.AuxInt = ssa.Int32ToAuxInt(8)
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [10] dst src mem)
	// result: (MOVWstore [8] dst (MOVWload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 10 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVWstore)
		v.AuxInt = ssa.Int32ToAuxInt(8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWload, typ.UInt16)
		v0.AuxInt = ssa.Int32ToAuxInt(8)
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [11] dst src mem)
	// result: (MOVLstore [7] dst (MOVLload [7] src mem) (MOVQstore dst (MOVQload src mem) mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 11 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(7)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(7)
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [12] dst src mem)
	// result: (MOVLstore [8] dst (MOVLload [8] src mem) (MOVQstore dst (MOVQload src mem) mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 12 {
			break
		}
		dst := v_0
		src := v_1
		mem := v_2
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AuxInt = ssa.Int32ToAuxInt(8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLload, typ.UInt32)
		v0.AuxInt = ssa.Int32ToAuxInt(8)
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [s] dst src mem)
	// cond: s >= 13 && s <= 15
	// result: (MOVQstore [int32(s-8)] dst (MOVQload [int32(s-8)] src mem) (MOVQstore dst (MOVQload src mem) mem))
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		dst := v_0
		src := v_1
		mem := v_2
		if !(s >= 13 && s <= 15) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstore)
		v.AuxInt = ssa.Int32ToAuxInt(int32(s - 8))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v0.AuxInt = ssa.Int32ToAuxInt(int32(s - 8))
		v0.AddArg2(src, mem)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstore, types.TypeMem)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v2.AddArg2(src, mem)
		v1.AddArg3(dst, v2, mem)
		v.AddArg3(dst, v0, v1)
		return true
	}
	// match: (Move [s] dst src mem)
	// cond: s > 16 && s < 192 && ssa.LogLargeCopyValue(v, s)
	// result: (LoweredMove [s] dst src mem)
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		dst := v_0
		src := v_1
		mem := v_2
		if !(s > 16 && s < 192 && ssa.LogLargeCopyValue(v, s)) {
			break
		}
		v.Reset(ssaop.OpAMD64LoweredMove)
		v.AuxInt = ssa.Int64ToAuxInt(s)
		v.AddArg3(dst, src, mem)
		return true
	}
	// match: (Move [s] dst src mem)
	// cond: s >= 192 && s <= ssa.RepMoveThreshold && ssa.LogLargeCopyValue(v, s)
	// result: (LoweredMoveLoop [s] dst src mem)
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		dst := v_0
		src := v_1
		mem := v_2
		if !(s >= 192 && s <= ssa.RepMoveThreshold && ssa.LogLargeCopyValue(v, s)) {
			break
		}
		v.Reset(ssaop.OpAMD64LoweredMoveLoop)
		v.AuxInt = ssa.Int64ToAuxInt(s)
		v.AddArg3(dst, src, mem)
		return true
	}
	// match: (Move [s] dst src mem)
	// cond: s > ssa.RepMoveThreshold && s%8 != 0
	// result: (Move [s-s%8] (OffPtr <dst.Type> dst [s%8]) (OffPtr <src.Type> src [s%8]) (MOVQstore dst (MOVQload src mem) mem))
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		dst := v_0
		src := v_1
		mem := v_2
		if !(s > ssa.RepMoveThreshold && s%8 != 0) {
			break
		}
		v.Reset(ssaop.OpMove)
		v.AuxInt = ssa.Int64ToAuxInt(s - s%8)
		v0 := b.NewValue0(v.Pos, ssaop.OpOffPtr, dst.Type)
		v0.AuxInt = ssa.Int64ToAuxInt(s % 8)
		v0.AddArg(dst)
		v1 := b.NewValue0(v.Pos, ssaop.OpOffPtr, src.Type)
		v1.AuxInt = ssa.Int64ToAuxInt(s % 8)
		v1.AddArg(src)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstore, types.TypeMem)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQload, typ.UInt64)
		v3.AddArg2(src, mem)
		v2.AddArg3(dst, v3, mem)
		v.AddArg3(v0, v1, v2)
		return true
	}
	// match: (Move [s] dst src mem)
	// cond: s > ssa.RepMoveThreshold && s%8 == 0 && ssa.LogLargeCopyValue(v, s)
	// result: (REPMOVSQ dst src (MOVQconst [s/8]) mem)
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		dst := v_0
		src := v_1
		mem := v_2
		if !(s > ssa.RepMoveThreshold && s%8 == 0 && ssa.LogLargeCopyValue(v, s)) {
			break
		}
		v.Reset(ssaop.OpAMD64REPMOVSQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v0.AuxInt = ssa.Int64ToAuxInt(s / 8)
		v.AddArg4(dst, src, v0, mem)
		return true
	}
	return false
}
func rewriteValue_OpMul64uhilo(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (Mul64uhilo x y)
	// cond: buildcfg.GOAMD64 >= 3
	// result: (MULXQ x y)
	for {
		x := v_0
		y := v_1
		if !(buildcfg.GOAMD64 >= 3) {
			break
		}
		v.Reset(ssaop.OpAMD64MULXQ)
		v.AddArg2(x, y)
		return true
	}
	// match: (Mul64uhilo x y)
	// cond: buildcfg.GOAMD64 < 3
	// result: (MULQU2 x y)
	for {
		x := v_0
		y := v_1
		if !(buildcfg.GOAMD64 < 3) {
			break
		}
		v.Reset(ssaop.OpAMD64MULQU2)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpNeg32F(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Neg32F x)
	// result: (PXOR x (MOVSSconst <typ.Float32> [float32(math.Copysign(0, -1))]))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64PXOR)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVSSconst, typ.Float32)
		v0.AuxInt = ssa.Float32ToAuxInt(float32(math.Copysign(0, -1)))
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpNeg64F(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Neg64F x)
	// result: (PXOR x (MOVSDconst <typ.Float64> [math.Copysign(0, -1)]))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64PXOR)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVSDconst, typ.Float64)
		v0.AuxInt = ssa.Float64ToAuxInt(math.Copysign(0, -1))
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_OpNeq16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Neq16 x y)
	// result: (SETNE (CMPW x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPW, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNeq32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Neq32 x y)
	// result: (SETNE (CMPL x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPL, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNeq32F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Neq32F x y)
	// result: (SETNEF (UCOMISS x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETNEF)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64UCOMISS, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNeq64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Neq64 x y)
	// result: (SETNE (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNeq64F(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Neq64F x y)
	// result: (SETNEF (UCOMISD x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETNEF)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64UCOMISD, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNeq8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Neq8 x y)
	// result: (SETNE (CMPB x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNeqB(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (NeqB x y)
	// result: (SETNE (CMPB x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPB, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNeqPtr(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (NeqPtr x y)
	// result: (SETNE (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64SETNE)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNot(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Not x)
	// result: (XORLconst [1] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64XORLconst)
		v.AuxInt = ssa.Int32ToAuxInt(1)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpNotEqualFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualFloat32x16 x y)
	// result: (VPMOVMToVec32x16 (VCMPPS512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPS512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (NotEqualFloat32x4 x y)
	// result: (VCMPPS128 [4] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(4)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpNotEqualFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (NotEqualFloat32x8 x y)
	// result: (VCMPPS256 [4] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(4)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpNotEqualFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (NotEqualFloat64x2 x y)
	// result: (VCMPPD128 [4] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(4)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpNotEqualFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (NotEqualFloat64x4 x y)
	// result: (VCMPPD256 [4] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VCMPPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(4)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpNotEqualFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualFloat64x8 x y)
	// result: (VPMOVMToVec64x8 (VCMPPD512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VCMPPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualInt16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPW512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualInt32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPD512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualInt64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPQ512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualInt8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPB512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualUint16x32 x y)
	// result: (VPMOVMToVec16x32 (VPCMPUW512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec16x32)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUW512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualUint32x16 x y)
	// result: (VPMOVMToVec32x16 (VPCMPUD512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec32x16)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUD512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualUint64x8 x y)
	// result: (VPMOVMToVec64x8 (VPCMPUQ512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec64x8)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUQ512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpNotEqualUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (NotEqualUint8x64 x y)
	// result: (VPMOVMToVec8x64 (VPCMPUB512 [4] x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VPMOVMToVec8x64)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPCMPUB512, typ.Mask)
		v0.AuxInt = ssa.Uint8ToAuxInt(4)
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpOffPtr(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (OffPtr [off] ptr)
	// cond: ssa.Is32Bit(off)
	// result: (ADDQconst [int32(off)] ptr)
	for {
		off := ssa.AuxIntToInt64(v.AuxInt)
		ptr := v_0
		if !(ssa.Is32Bit(off)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(int32(off))
		v.AddArg(ptr)
		return true
	}
	// match: (OffPtr [off] ptr)
	// result: (ADDQ (MOVQconst [off]) ptr)
	for {
		off := ssa.AuxIntToInt64(v.AuxInt)
		ptr := v_0
		v.Reset(ssaop.OpAMD64ADDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v0.AuxInt = ssa.Int64ToAuxInt(off)
		v.AddArg2(v0, ptr)
		return true
	}
}
func rewriteValue_OpPopCount16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (PopCount16 x)
	// result: (POPCNTL (MOVWQZX <typ.UInt32> x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64POPCNTL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWQZX, typ.UInt32)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpPopCount8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (PopCount8 x)
	// result: (POPCNTL (MOVBQZX <typ.UInt32> x))
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64POPCNTL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVBQZX, typ.UInt32)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpRoundFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundFloat32x4 x)
	// result: (VROUNDPS128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundFloat32x8 x)
	// result: (VROUNDPS256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundFloat64x2 x)
	// result: (VROUNDPD128 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundFloat64x4 x)
	// result: (VROUNDPD256 [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledFloat32x16 [a] x)
	// result: (VRNDSCALEPS512 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledFloat32x4 [a] x)
	// result: (VRNDSCALEPS128 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledFloat32x8 [a] x)
	// result: (VRNDSCALEPS256 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledFloat64x2 [a] x)
	// result: (VRNDSCALEPD128 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledFloat64x4 [a] x)
	// result: (VRNDSCALEPD256 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledFloat64x8 [a] x)
	// result: (VRNDSCALEPD512 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledResidueFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledResidueFloat32x16 [a] x)
	// result: (VREDUCEPS512 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledResidueFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledResidueFloat32x4 [a] x)
	// result: (VREDUCEPS128 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledResidueFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledResidueFloat32x8 [a] x)
	// result: (VREDUCEPS256 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledResidueFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledResidueFloat64x2 [a] x)
	// result: (VREDUCEPD128 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledResidueFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledResidueFloat64x4 [a] x)
	// result: (VREDUCEPD256 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundScaledResidueFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundScaledResidueFloat64x8 [a] x)
	// result: (VREDUCEPD512 [a+0] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRoundToEven(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (RoundToEven x)
	// result: (ROUNDSD [0] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64ROUNDSD)
		v.AuxInt = ssa.Int8ToAuxInt(0)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpRsh16Ux16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh16Ux16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPWconst y [16])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRW, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v2.AuxInt = ssa.Int16ToAuxInt(16)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh16Ux16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRW x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRW)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh16Ux32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh16Ux32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPLconst y [16])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRW, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(16)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh16Ux32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRW x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRW)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh16Ux64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh16Ux64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPQconst y [16])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRW, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(16)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh16Ux64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRW x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRW)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh16Ux8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh16Ux8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRW <t> x y) (SBBLcarrymask <t> (CMPBconst y [16])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRW, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v2.AuxInt = ssa.Int8ToAuxInt(16)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh16Ux8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRW x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRW)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh16x16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [16])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARW)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v3.AuxInt = ssa.Int16ToAuxInt(16)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh16x16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARW x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARW)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh16x32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [16])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARW)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v3.AuxInt = ssa.Int32ToAuxInt(16)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh16x32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARW x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARW)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh16x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh16x64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARW <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [16])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARW)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORQ, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTQ, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v3.AuxInt = ssa.Int32ToAuxInt(16)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh16x64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARW x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARW)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh16x8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARW <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [16])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARW)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v3.AuxInt = ssa.Int8ToAuxInt(16)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh16x8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARW x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARW)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh32Ux16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh32Ux16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPWconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v2.AuxInt = ssa.Int16ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh32Ux16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh32Ux32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh32Ux32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPLconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh32Ux32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh32Ux64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh32Ux64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPQconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh32Ux64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh32Ux8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh32Ux8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRL <t> x y) (SBBLcarrymask <t> (CMPBconst y [32])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRL, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v2.AuxInt = ssa.Int8ToAuxInt(32)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh32Ux8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh32x16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [32])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v3.AuxInt = ssa.Int16ToAuxInt(32)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh32x16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh32x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh32x32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [32])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v3.AuxInt = ssa.Int32ToAuxInt(32)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh32x32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh32x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh32x64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARL <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [32])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORQ, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTQ, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v3.AuxInt = ssa.Int32ToAuxInt(32)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh32x64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh32x8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARL <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [32])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v3.AuxInt = ssa.Int8ToAuxInt(32)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh32x8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARL x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARL)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh64Ux16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh64Ux16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPWconst y [64])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRQ, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v2.AuxInt = ssa.Int16ToAuxInt(64)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh64Ux16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh64Ux32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh64Ux32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPLconst y [64])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRQ, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(64)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh64Ux32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh64Ux64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh64Ux64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPQconst y [64])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRQ, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(64)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh64Ux64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh64Ux8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh64Ux8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDQ (SHRQ <t> x y) (SBBQcarrymask <t> (CMPBconst y [64])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRQ, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v2.AuxInt = ssa.Int8ToAuxInt(64)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh64Ux8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh64x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh64x16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [64])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v3.AuxInt = ssa.Int16ToAuxInt(64)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh64x16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh64x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh64x32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [64])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v3.AuxInt = ssa.Int32ToAuxInt(64)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh64x32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh64x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh64x64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARQ <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [64])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORQ, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTQ, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v3.AuxInt = ssa.Int32ToAuxInt(64)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh64x64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh64x8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARQ <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [64])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v3.AuxInt = ssa.Int8ToAuxInt(64)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh64x8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARQ x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARQ)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh8Ux16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh8Ux16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPWconst y [8])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRB, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v2.AuxInt = ssa.Int16ToAuxInt(8)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh8Ux16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRB x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRB)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh8Ux32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh8Ux32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPLconst y [8])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRB, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(8)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh8Ux32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRB x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRB)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh8Ux64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh8Ux64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPQconst y [8])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRB, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v2.AuxInt = ssa.Int32ToAuxInt(8)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh8Ux64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRB x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRB)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh8Ux8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh8Ux8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (ANDL (SHRB <t> x y) (SBBLcarrymask <t> (CMPBconst y [8])))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SHRB, t)
		v0.AddArg2(x, y)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, t)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v2.AuxInt = ssa.Int8ToAuxInt(8)
		v2.AddArg(y)
		v1.AddArg(v2)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Rsh8Ux8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SHRB x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SHRB)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh8x16 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPWconst y [8])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARB)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPWconst, types.TypeFlags)
		v3.AuxInt = ssa.Int16ToAuxInt(8)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh8x16 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARB x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARB)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh8x32 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPLconst y [8])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARB)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
		v3.AuxInt = ssa.Int32ToAuxInt(8)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh8x32 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARB x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARB)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh8x64 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARB <t> x (ORQ <y.Type> y (NOTQ <y.Type> (SBBQcarrymask <y.Type> (CMPQconst y [8])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARB)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORQ, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTQ, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
		v3.AuxInt = ssa.Int32ToAuxInt(8)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh8x64 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARB x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARB)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpRsh8x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (Rsh8x8 <t> x y)
	// cond: !ssa.ShiftIsBounded(v)
	// result: (SARB <t> x (ORL <y.Type> y (NOTL <y.Type> (SBBLcarrymask <y.Type> (CMPBconst y [8])))))
	for {
		t := v.Type
		x := v_0
		y := v_1
		if !(!ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARB)
		v.Type = t
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ORL, y.Type)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64NOTL, y.Type)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBLcarrymask, y.Type)
		v3 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPBconst, types.TypeFlags)
		v3.AuxInt = ssa.Int8ToAuxInt(8)
		v3.AddArg(y)
		v2.AddArg(v3)
		v1.AddArg(v2)
		v0.AddArg2(y, v1)
		v.AddArg2(x, v0)
		return true
	}
	// match: (Rsh8x8 x y)
	// cond: ssa.ShiftIsBounded(v)
	// result: (SARB x y)
	for {
		x := v_0
		y := v_1
		if !(ssa.ShiftIsBounded(v)) {
			break
		}
		v.Reset(ssaop.OpAMD64SARB)
		v.AddArg2(x, y)
		return true
	}
	return false
}
func rewriteValue_OpSelect0(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Select0 (Mul64uover x y))
	// result: (Select0 <typ.UInt64> (MULQU x y))
	for {
		if v_0.Op != ssaop.OpMul64uover {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.Reset(ssaop.OpSelect0)
		v.Type = typ.UInt64
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
	// match: (Select0 (Mul32uover x y))
	// result: (Select0 <typ.UInt32> (MULLU x y))
	for {
		if v_0.Op != ssaop.OpMul32uover {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.Reset(ssaop.OpSelect0)
		v.Type = typ.UInt32
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
		v0.AddArg2(x, y)
		v.AddArg(v0)
		return true
	}
	// match: (Select0 (Add64carry x y c))
	// result: (Select0 (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
	for {
		if v_0.Op != ssaop.OpAdd64carry {
			break
		}
		c := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v1 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
		v2.AddArg(c)
		v1.AddArg(v2)
		v0.AddArg3(x, y, v1)
		v.AddArg(v0)
		return true
	}
	// match: (Select0 (Sub64borrow x y c))
	// result: (Select0 (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))
	for {
		if v_0.Op != ssaop.OpSub64borrow {
			break
		}
		c := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		v.Reset(ssaop.OpSelect0)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v1 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
		v2.AddArg(c)
		v1.AddArg(v2)
		v0.AddArg3(x, y, v1)
		v.AddArg(v0)
		return true
	}
	// match: (Select0 <t> (AddTupleFirst32 val tuple))
	// result: (ADDL val (Select0 <t> tuple))
	for {
		t := v.Type
		if v_0.Op != ssaop.OpAMD64AddTupleFirst32 {
			break
		}
		tuple := v_0.Args[1]
		val := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ADDL)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, t)
		v0.AddArg(tuple)
		v.AddArg2(val, v0)
		return true
	}
	// match: (Select0 <t> (AddTupleFirst64 val tuple))
	// result: (ADDQ val (Select0 <t> tuple))
	for {
		t := v.Type
		if v_0.Op != ssaop.OpAMD64AddTupleFirst64 {
			break
		}
		tuple := v_0.Args[1]
		val := v_0.Args[0]
		v.Reset(ssaop.OpAMD64ADDQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect0, t)
		v0.AddArg(tuple)
		v.AddArg2(val, v0)
		return true
	}
	// match: (Select0 a:(ADDQconstflags [c] x))
	// cond: a.Uses == 1
	// result: (ADDQconst [c] x)
	for {
		a := v_0
		if a.Op != ssaop.OpAMD64ADDQconstflags {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	// match: (Select0 a:(ADDLconstflags [c] x))
	// cond: a.Uses == 1
	// result: (ADDLconst [c] x)
	for {
		a := v_0
		if a.Op != ssaop.OpAMD64ADDLconstflags {
			break
		}
		c := ssa.AuxIntToInt32(a.AuxInt)
		x := a.Args[0]
		if !(a.Uses == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLconst)
		v.AuxInt = ssa.Int32ToAuxInt(c)
		v.AddArg(x)
		return true
	}
	return false
}
func rewriteValue_OpSelect1(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Select1 (Mul64uover x y))
	// result: (SETO (Select1 <types.TypeFlags> (MULQU x y)))
	for {
		if v_0.Op != ssaop.OpMul64uover {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETO)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MULQU, types.NewTuple(typ.UInt64, types.TypeFlags))
		v1.AddArg2(x, y)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	// match: (Select1 (Mul32uover x y))
	// result: (SETO (Select1 <types.TypeFlags> (MULLU x y)))
	for {
		if v_0.Op != ssaop.OpMul32uover {
			break
		}
		y := v_0.Args[1]
		x := v_0.Args[0]
		v.Reset(ssaop.OpAMD64SETO)
		v0 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MULLU, types.NewTuple(typ.UInt32, types.TypeFlags))
		v1.AddArg2(x, y)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	// match: (Select1 (Add64carry x y c))
	// result: (MOVBQZX (SETB <types.Types[types.TUINT8]> (Select1 <types.TypeFlags> (ADCQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
	for {
		if v_0.Op != ssaop.OpAdd64carry {
			break
		}
		c := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		v.Reset(ssaop.OpAMD64MOVBQZX)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SETB, types.Types[types.TUINT8])
		v1 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64ADCQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v3 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v4 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
		v4.AddArg(c)
		v3.AddArg(v4)
		v2.AddArg3(x, y, v3)
		v1.AddArg(v2)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	// match: (Select1 (Sub64borrow x y c))
	// result: (MOVBQZX (SETB <types.Types[types.TUINT8]> (Select1 <types.TypeFlags> (SBBQ x y (Select1 <types.TypeFlags> (NEGLflags c))))))
	for {
		if v_0.Op != ssaop.OpSub64borrow {
			break
		}
		c := v_0.Args[2]
		x := v_0.Args[0]
		y := v_0.Args[1]
		v.Reset(ssaop.OpAMD64MOVBQZX)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64SETB, types.Types[types.TUINT8])
		v1 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v2 := b.NewValue0(v.Pos, ssaop.OpAMD64SBBQ, types.NewTuple(typ.UInt64, types.TypeFlags))
		v3 := b.NewValue0(v.Pos, ssaop.OpSelect1, types.TypeFlags)
		v4 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGLflags, types.NewTuple(typ.UInt32, types.TypeFlags))
		v4.AddArg(c)
		v3.AddArg(v4)
		v2.AddArg3(x, y, v3)
		v1.AddArg(v2)
		v0.AddArg(v1)
		v.AddArg(v0)
		return true
	}
	// match: (Select1 (NEGLflags (MOVQconst [0])))
	// result: (FlagEQ)
	for {
		if v_0.Op != ssaop.OpAMD64NEGLflags {
			break
		}
		v_0_0 := v_0.Args[0]
		if v_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_0_0.AuxInt) != 0 {
			break
		}
		v.Reset(ssaop.OpAMD64FlagEQ)
		return true
	}
	// match: (Select1 (NEGLflags (MOVBQZX (SETB x))))
	// result: x
	for {
		if v_0.Op != ssaop.OpAMD64NEGLflags {
			break
		}
		v_0_0 := v_0.Args[0]
		if v_0_0.Op != ssaop.OpAMD64MOVBQZX {
			break
		}
		v_0_0_0 := v_0_0.Args[0]
		if v_0_0_0.Op != ssaop.OpAMD64SETB {
			break
		}
		x := v_0_0_0.Args[0]
		v.CopyOf(x)
		return true
	}
	// match: (Select1 (AddTupleFirst32 _ tuple))
	// result: (Select1 tuple)
	for {
		if v_0.Op != ssaop.OpAMD64AddTupleFirst32 {
			break
		}
		tuple := v_0.Args[1]
		v.Reset(ssaop.OpSelect1)
		v.AddArg(tuple)
		return true
	}
	// match: (Select1 (AddTupleFirst64 _ tuple))
	// result: (Select1 tuple)
	for {
		if v_0.Op != ssaop.OpAMD64AddTupleFirst64 {
			break
		}
		tuple := v_0.Args[1]
		v.Reset(ssaop.OpSelect1)
		v.AddArg(tuple)
		return true
	}
	// match: (Select1 xadd:(XADDLlock [off] {sym} val ptr mem))
	// cond: xadd.Uses == 1 && ssa.Clobber(xadd)
	// result: (ADDLlock [off] {sym} ptr val mem)
	for {
		xadd := v_0
		if xadd.Op != ssaop.OpAMD64XADDLlock {
			break
		}
		off := ssa.AuxIntToInt32(xadd.AuxInt)
		sym := ssa.AuxToSym(xadd.Aux)
		mem := xadd.Args[2]
		val := xadd.Args[0]
		ptr := xadd.Args[1]
		if !(xadd.Uses == 1 && ssa.Clobber(xadd)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDLlock)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Select1 xadd:(XADDQlock [off] {sym} val ptr mem))
	// cond: xadd.Uses == 1 && ssa.Clobber(xadd)
	// result: (ADDQlock [off] {sym} ptr val mem)
	for {
		xadd := v_0
		if xadd.Op != ssaop.OpAMD64XADDQlock {
			break
		}
		off := ssa.AuxIntToInt32(xadd.AuxInt)
		sym := ssa.AuxToSym(xadd.Aux)
		mem := xadd.Args[2]
		val := xadd.Args[0]
		ptr := xadd.Args[1]
		if !(xadd.Uses == 1 && ssa.Clobber(xadd)) {
			break
		}
		v.Reset(ssaop.OpAMD64ADDQlock)
		v.AuxInt = ssa.Int32ToAuxInt(off)
		v.Aux = ssa.SymToAux(sym)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Select1 a:(LoweredAtomicAnd64 ptr val mem))
	// cond: a.Uses == 1 && ssa.Clobber(a)
	// result: (ANDQlock ptr val mem)
	for {
		a := v_0
		if a.Op != ssaop.OpAMD64LoweredAtomicAnd64 {
			break
		}
		mem := a.Args[2]
		ptr := a.Args[0]
		val := a.Args[1]
		if !(a.Uses == 1 && ssa.Clobber(a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDQlock)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Select1 a:(LoweredAtomicAnd32 ptr val mem))
	// cond: a.Uses == 1 && ssa.Clobber(a)
	// result: (ANDLlock ptr val mem)
	for {
		a := v_0
		if a.Op != ssaop.OpAMD64LoweredAtomicAnd32 {
			break
		}
		mem := a.Args[2]
		ptr := a.Args[0]
		val := a.Args[1]
		if !(a.Uses == 1 && ssa.Clobber(a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ANDLlock)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Select1 a:(LoweredAtomicOr64 ptr val mem))
	// cond: a.Uses == 1 && ssa.Clobber(a)
	// result: (ORQlock ptr val mem)
	for {
		a := v_0
		if a.Op != ssaop.OpAMD64LoweredAtomicOr64 {
			break
		}
		mem := a.Args[2]
		ptr := a.Args[0]
		val := a.Args[1]
		if !(a.Uses == 1 && ssa.Clobber(a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORQlock)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Select1 a:(LoweredAtomicOr32 ptr val mem))
	// cond: a.Uses == 1 && ssa.Clobber(a)
	// result: (ORLlock ptr val mem)
	for {
		a := v_0
		if a.Op != ssaop.OpAMD64LoweredAtomicOr32 {
			break
		}
		mem := a.Args[2]
		ptr := a.Args[0]
		val := a.Args[1]
		if !(a.Uses == 1 && ssa.Clobber(a)) {
			break
		}
		v.Reset(ssaop.OpAMD64ORLlock)
		v.AddArg3(ptr, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpSelectN(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	config := b.Func.Config
	// match: (SelectN [0] call:(CALLstatic {sym} s1:(MOVQstoreconst _ [sc] s2:(MOVQstore _ src s3:(MOVQstore _ dst mem)))))
	// cond: sc.Val64() >= 0 && ssa.IsSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && ssa.IsInlinableMemmove(dst, src, sc.Val64(), config) && ssa.Clobber(s1, s2, s3, call)
	// result: (Move [sc.Val64()] dst src mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 0 {
			break
		}
		call := v_0
		if call.Op != ssaop.OpAMD64CALLstatic || len(call.Args) != 1 {
			break
		}
		sym := ssa.AuxToCall(call.Aux)
		s1 := call.Args[0]
		if s1.Op != ssaop.OpAMD64MOVQstoreconst {
			break
		}
		sc := ssa.AuxIntToValAndOff(s1.AuxInt)
		_ = s1.Args[1]
		s2 := s1.Args[1]
		if s2.Op != ssaop.OpAMD64MOVQstore {
			break
		}
		_ = s2.Args[2]
		src := s2.Args[1]
		s3 := s2.Args[2]
		if s3.Op != ssaop.OpAMD64MOVQstore {
			break
		}
		mem := s3.Args[2]
		dst := s3.Args[1]
		if !(sc.Val64() >= 0 && ssa.IsSameCall(sym, "runtime.memmove") && s1.Uses == 1 && s2.Uses == 1 && s3.Uses == 1 && ssa.IsInlinableMemmove(dst, src, sc.Val64(), config) && ssa.Clobber(s1, s2, s3, call)) {
			break
		}
		v.Reset(ssaop.OpMove)
		v.AuxInt = ssa.Int64ToAuxInt(sc.Val64())
		v.AddArg3(dst, src, mem)
		return true
	}
	// match: (SelectN [0] call:(CALLstatic {sym} dst src (MOVQconst [sz]) mem))
	// cond: sz >= 0 && ssa.IsSameCall(sym, "runtime.memmove") && call.Uses == 1 && ssa.IsInlinableMemmove(dst, src, sz, config) && ssa.Clobber(call)
	// result: (Move [sz] dst src mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 0 {
			break
		}
		call := v_0
		if call.Op != ssaop.OpAMD64CALLstatic || len(call.Args) != 4 {
			break
		}
		sym := ssa.AuxToCall(call.Aux)
		mem := call.Args[3]
		dst := call.Args[0]
		src := call.Args[1]
		call_2 := call.Args[2]
		if call_2.Op != ssaop.OpAMD64MOVQconst {
			break
		}
		sz := ssa.AuxIntToInt64(call_2.AuxInt)
		if !(sz >= 0 && ssa.IsSameCall(sym, "runtime.memmove") && call.Uses == 1 && ssa.IsInlinableMemmove(dst, src, sz, config) && ssa.Clobber(call)) {
			break
		}
		v.Reset(ssaop.OpMove)
		v.AuxInt = ssa.Int64ToAuxInt(sz)
		v.AddArg3(dst, src, mem)
		return true
	}
	return false
}
func rewriteValue_OpSetHiFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiFloat32x16 x y)
	// result: (VINSERTF64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTF64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiFloat32x8 x y)
	// result: (VINSERTF128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTF128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiFloat64x4 x y)
	// result: (VINSERTF128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTF128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiFloat64x8 x y)
	// result: (VINSERTF64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTF64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiInt16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiInt16x16 x y)
	// result: (VINSERTI128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiInt16x32 x y)
	// result: (VINSERTI64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiInt32x16 x y)
	// result: (VINSERTI64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiInt32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiInt32x8 x y)
	// result: (VINSERTI128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiInt64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiInt64x4 x y)
	// result: (VINSERTI128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiInt64x8 x y)
	// result: (VINSERTI64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiInt8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiInt8x32 x y)
	// result: (VINSERTI128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiInt8x64 x y)
	// result: (VINSERTI64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiUint16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiUint16x16 x y)
	// result: (VINSERTI128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiUint16x32 x y)
	// result: (VINSERTI64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiUint32x16 x y)
	// result: (VINSERTI64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiUint32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiUint32x8 x y)
	// result: (VINSERTI128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiUint64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiUint64x4 x y)
	// result: (VINSERTI128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiUint64x8 x y)
	// result: (VINSERTI64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiUint8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiUint8x32 x y)
	// result: (VINSERTI128256 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetHiUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetHiUint8x64 x y)
	// result: (VINSERTI64X4512 [1] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(1)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoFloat32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoFloat32x16 x y)
	// result: (VINSERTF64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTF64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoFloat32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoFloat32x8 x y)
	// result: (VINSERTF128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTF128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoFloat64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoFloat64x4 x y)
	// result: (VINSERTF128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTF128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoFloat64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoFloat64x8 x y)
	// result: (VINSERTF64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTF64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoInt16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoInt16x16 x y)
	// result: (VINSERTI128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoInt16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoInt16x32 x y)
	// result: (VINSERTI64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoInt32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoInt32x16 x y)
	// result: (VINSERTI64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoInt32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoInt32x8 x y)
	// result: (VINSERTI128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoInt64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoInt64x4 x y)
	// result: (VINSERTI128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoInt64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoInt64x8 x y)
	// result: (VINSERTI64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoInt8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoInt8x32 x y)
	// result: (VINSERTI128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoInt8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoInt8x64 x y)
	// result: (VINSERTI64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoUint16x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoUint16x16 x y)
	// result: (VINSERTI128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoUint16x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoUint16x32 x y)
	// result: (VINSERTI64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoUint32x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoUint32x16 x y)
	// result: (VINSERTI64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoUint32x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoUint32x8 x y)
	// result: (VINSERTI128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoUint64x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoUint64x4 x y)
	// result: (VINSERTI128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoUint64x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoUint64x8 x y)
	// result: (VINSERTI64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoUint8x32(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoUint8x32 x y)
	// result: (VINSERTI128256 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI128256)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSetLoUint8x64(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (SetLoUint8x64 x y)
	// result: (VINSERTI64X4512 [0] x y)
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64VINSERTI64X4512)
		v.AuxInt = ssa.Uint8ToAuxInt(0)
		v.AddArg2(x, y)
		return true
	}
}
func rewriteValue_OpSlicemask(v *ssa.Value) bool {
	v_0 := v.Args[0]
	b := v.Block
	// match: (Slicemask <t> x)
	// result: (SARQconst (NEGQ <t> x) [63])
	for {
		t := v.Type
		x := v_0
		v.Reset(ssaop.OpAMD64SARQconst)
		v.AuxInt = ssa.Int8ToAuxInt(63)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64NEGQ, t)
		v0.AddArg(x)
		v.AddArg(v0)
		return true
	}
}
func rewriteValue_OpSpectreIndex(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SpectreIndex <t> x y)
	// result: (CMOVQCC x (MOVQconst [0]) (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64CMOVQCC)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v0.AuxInt = ssa.Int64ToAuxInt(0)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v1.AddArg2(x, y)
		v.AddArg3(x, v0, v1)
		return true
	}
}
func rewriteValue_OpSpectreSliceIndex(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (SpectreSliceIndex <t> x y)
	// result: (CMOVQHI x (MOVQconst [0]) (CMPQ x y))
	for {
		x := v_0
		y := v_1
		v.Reset(ssaop.OpAMD64CMOVQHI)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v0.AuxInt = ssa.Int64ToAuxInt(0)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64CMPQ, types.TypeFlags)
		v1.AddArg2(x, y)
		v.AddArg3(x, v0, v1)
		return true
	}
}
func rewriteValue_OpStore(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 8 && t.IsFloat()
	// result: (MOVSDstore ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 8 && t.IsFloat()) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSDstore)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 4 && t.IsFloat()
	// result: (MOVSSstore ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 4 && t.IsFloat()) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVSSstore)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 8 && !t.IsFloat()
	// result: (MOVQstore ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 8 && !t.IsFloat()) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstore)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 4 && !t.IsFloat()
	// result: (MOVLstore ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 4 && !t.IsFloat()) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVLstore)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 2
	// result: (MOVWstore ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 2) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVWstore)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 1
	// result: (MOVBstore ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 1) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVBstore)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 16
	// result: (VMOVDQUstore128 ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 16) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore128)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 32
	// result: (VMOVDQUstore256 ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 32) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore256)
		v.AddArg3(ptr, val, mem)
		return true
	}
	// match: (Store {t} ptr val mem)
	// cond: t.Size() == 64
	// result: (VMOVDQUstore512 ptr val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		val := v_1
		mem := v_2
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VMOVDQUstore512)
		v.AddArg3(ptr, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpStoreMasked16(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (StoreMasked16 {t} ptr mask val mem)
	// cond: t.Size() == 64
	// result: (VPMASK16store512 ptr (VPMOVVec16x32ToM <types.TypeMask> mask) val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		mask := v_1
		val := v_2
		mem := v_3
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK16store512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(ptr, v0, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpStoreMasked32(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (StoreMasked32 {t} ptr mask val mem)
	// cond: t.Size() == 16
	// result: (VPMASK32store128 ptr mask val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		mask := v_1
		val := v_2
		mem := v_3
		if !(t.Size() == 16) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK32store128)
		v.AddArg4(ptr, mask, val, mem)
		return true
	}
	// match: (StoreMasked32 {t} ptr mask val mem)
	// cond: t.Size() == 32
	// result: (VPMASK32store256 ptr mask val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		mask := v_1
		val := v_2
		mem := v_3
		if !(t.Size() == 32) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK32store256)
		v.AddArg4(ptr, mask, val, mem)
		return true
	}
	// match: (StoreMasked32 {t} ptr mask val mem)
	// cond: t.Size() == 64
	// result: (VPMASK32store512 ptr (VPMOVVec32x16ToM <types.TypeMask> mask) val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		mask := v_1
		val := v_2
		mem := v_3
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK32store512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(ptr, v0, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpStoreMasked64(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (StoreMasked64 {t} ptr mask val mem)
	// cond: t.Size() == 16
	// result: (VPMASK64store128 ptr mask val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		mask := v_1
		val := v_2
		mem := v_3
		if !(t.Size() == 16) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK64store128)
		v.AddArg4(ptr, mask, val, mem)
		return true
	}
	// match: (StoreMasked64 {t} ptr mask val mem)
	// cond: t.Size() == 32
	// result: (VPMASK64store256 ptr mask val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		mask := v_1
		val := v_2
		mem := v_3
		if !(t.Size() == 32) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK64store256)
		v.AddArg4(ptr, mask, val, mem)
		return true
	}
	// match: (StoreMasked64 {t} ptr mask val mem)
	// cond: t.Size() == 64
	// result: (VPMASK64store512 ptr (VPMOVVec64x8ToM <types.TypeMask> mask) val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		mask := v_1
		val := v_2
		mem := v_3
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK64store512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(ptr, v0, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpStoreMasked8(v *ssa.Value) bool {
	v_3 := v.Args[3]
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (StoreMasked8 {t} ptr mask val mem)
	// cond: t.Size() == 64
	// result: (VPMASK8store512 ptr (VPMOVVec8x64ToM <types.TypeMask> mask) val mem)
	for {
		t := ssa.AuxToType(v.Aux)
		ptr := v_0
		mask := v_1
		val := v_2
		mem := v_3
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64VPMASK8store512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x64ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg4(ptr, v0, val, mem)
		return true
	}
	return false
}
func rewriteValue_OpTrunc(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (Trunc x)
	// result: (ROUNDSD [3] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64ROUNDSD)
		v.AuxInt = ssa.Int8ToAuxInt(3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncFloat32x4 x)
	// result: (VROUNDPS128 [3] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncFloat32x8 x)
	// result: (VROUNDPS256 [3] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncFloat64x2 x)
	// result: (VROUNDPD128 [3] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncFloat64x4 x)
	// result: (VROUNDPD256 [3] x)
	for {
		x := v_0
		v.Reset(ssaop.OpAMD64VROUNDPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledFloat32x16 [a] x)
	// result: (VRNDSCALEPS512 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledFloat32x4 [a] x)
	// result: (VRNDSCALEPS128 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledFloat32x8 [a] x)
	// result: (VRNDSCALEPS256 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledFloat64x2 [a] x)
	// result: (VRNDSCALEPD128 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledFloat64x4 [a] x)
	// result: (VRNDSCALEPD256 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledFloat64x8 [a] x)
	// result: (VRNDSCALEPD512 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VRNDSCALEPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledResidueFloat32x16(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledResidueFloat32x16 [a] x)
	// result: (VREDUCEPS512 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledResidueFloat32x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledResidueFloat32x4 [a] x)
	// result: (VREDUCEPS128 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledResidueFloat32x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledResidueFloat32x8 [a] x)
	// result: (VREDUCEPS256 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPS256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledResidueFloat64x2(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledResidueFloat64x2 [a] x)
	// result: (VREDUCEPD128 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD128)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledResidueFloat64x4(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledResidueFloat64x4 [a] x)
	// result: (VREDUCEPD256 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD256)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpTruncScaledResidueFloat64x8(v *ssa.Value) bool {
	v_0 := v.Args[0]
	// match: (TruncScaledResidueFloat64x8 [a] x)
	// result: (VREDUCEPD512 [a+3] x)
	for {
		a := ssa.AuxIntToUint8(v.AuxInt)
		x := v_0
		v.Reset(ssaop.OpAMD64VREDUCEPD512)
		v.AuxInt = ssa.Uint8ToAuxInt(a + 3)
		v.AddArg(x)
		return true
	}
}
func rewriteValue_OpZero(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	typ := &b.Func.Config.Types
	// match: (Zero [0] _ mem)
	// result: mem
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 0 {
			break
		}
		mem := v_1
		v.CopyOf(mem)
		return true
	}
	// match: (Zero [1] destptr mem)
	// result: (MOVBstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 1 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVBstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v.AddArg2(destptr, mem)
		return true
	}
	// match: (Zero [2] destptr mem)
	// result: (MOVWstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 2 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVWstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v.AddArg2(destptr, mem)
		return true
	}
	// match: (Zero [4] destptr mem)
	// result: (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 4 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVLstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v.AddArg2(destptr, mem)
		return true
	}
	// match: (Zero [8] destptr mem)
	// result: (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem)
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 8 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVQstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v.AddArg2(destptr, mem)
		return true
	}
	// match: (Zero [3] destptr mem)
	// result: (MOVBstoreconst [ssa.MakeValAndOff(0,2)] destptr (MOVWstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 3 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVBstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 2))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVWstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [5] destptr mem)
	// result: (MOVBstoreconst [ssa.MakeValAndOff(0,4)] destptr (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 5 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVBstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 4))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [6] destptr mem)
	// result: (MOVWstoreconst [ssa.MakeValAndOff(0,4)] destptr (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 6 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVWstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 4))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [7] destptr mem)
	// result: (MOVLstoreconst [ssa.MakeValAndOff(0,3)] destptr (MOVLstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 7 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVLstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 3))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVLstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [9] destptr mem)
	// result: (MOVBstoreconst [ssa.MakeValAndOff(0,8)] destptr (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 9 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVBstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 8))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [10] destptr mem)
	// result: (MOVWstoreconst [ssa.MakeValAndOff(0,8)] destptr (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 10 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVWstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 8))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [11] destptr mem)
	// result: (MOVLstoreconst [ssa.MakeValAndOff(0,7)] destptr (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 11 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVLstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 7))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [12] destptr mem)
	// result: (MOVLstoreconst [ssa.MakeValAndOff(0,8)] destptr (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		if ssa.AuxIntToInt64(v.AuxInt) != 12 {
			break
		}
		destptr := v_0
		mem := v_1
		v.Reset(ssaop.OpAMD64MOVLstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 8))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [s] destptr mem)
	// cond: s > 12 && s < 16
	// result: (MOVQstoreconst [ssa.MakeValAndOff(0,int32(s-8))] destptr (MOVQstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		destptr := v_0
		mem := v_1
		if !(s > 12 && s < 16) {
			break
		}
		v.Reset(ssaop.OpAMD64MOVQstoreconst)
		v.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, int32(s-8)))
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQstoreconst, types.TypeMem)
		v0.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v0.AddArg2(destptr, mem)
		v.AddArg2(destptr, v0)
		return true
	}
	// match: (Zero [s] destptr mem)
	// cond: s >= 16 && s < 192
	// result: (LoweredZero [s] destptr mem)
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		destptr := v_0
		mem := v_1
		if !(s >= 16 && s < 192) {
			break
		}
		v.Reset(ssaop.OpAMD64LoweredZero)
		v.AuxInt = ssa.Int64ToAuxInt(s)
		v.AddArg2(destptr, mem)
		return true
	}
	// match: (Zero [s] destptr mem)
	// cond: s >= 192 && s <= ssa.RepZeroThreshold
	// result: (LoweredZeroLoop [s] destptr mem)
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		destptr := v_0
		mem := v_1
		if !(s >= 192 && s <= ssa.RepZeroThreshold) {
			break
		}
		v.Reset(ssaop.OpAMD64LoweredZeroLoop)
		v.AuxInt = ssa.Int64ToAuxInt(s)
		v.AddArg2(destptr, mem)
		return true
	}
	// match: (Zero [s] destptr mem)
	// cond: s > ssa.RepZeroThreshold && s%8 != 0
	// result: (Zero [s-s%8] (OffPtr <destptr.Type> destptr [s%8]) (MOVOstoreconst [ssa.MakeValAndOff(0,0)] destptr mem))
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		destptr := v_0
		mem := v_1
		if !(s > ssa.RepZeroThreshold && s%8 != 0) {
			break
		}
		v.Reset(ssaop.OpZero)
		v.AuxInt = ssa.Int64ToAuxInt(s - s%8)
		v0 := b.NewValue0(v.Pos, ssaop.OpOffPtr, destptr.Type)
		v0.AuxInt = ssa.Int64ToAuxInt(s % 8)
		v0.AddArg(destptr)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVOstoreconst, types.TypeMem)
		v1.AuxInt = ssa.ValAndOffToAuxInt(ssa.MakeValAndOff(0, 0))
		v1.AddArg2(destptr, mem)
		v.AddArg2(v0, v1)
		return true
	}
	// match: (Zero [s] destptr mem)
	// cond: s > ssa.RepZeroThreshold && s%8 == 0
	// result: (REPSTOSQ destptr (MOVQconst [s/8]) (MOVQconst [0]) mem)
	for {
		s := ssa.AuxIntToInt64(v.AuxInt)
		destptr := v_0
		mem := v_1
		if !(s > ssa.RepZeroThreshold && s%8 == 0) {
			break
		}
		v.Reset(ssaop.OpAMD64REPSTOSQ)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v0.AuxInt = ssa.Int64ToAuxInt(s / 8)
		v1 := b.NewValue0(v.Pos, ssaop.OpAMD64MOVQconst, typ.UInt64)
		v1.AuxInt = ssa.Int64ToAuxInt(0)
		v.AddArg4(destptr, v0, v1, mem)
		return true
	}
	return false
}
func rewriteValue_OpZeroSIMD(v *ssa.Value) bool {
	// match: (ZeroSIMD <t>)
	// cond: t.Size() == 16
	// result: (Zero128 <t>)
	for {
		t := v.Type
		if !(t.Size() == 16) {
			break
		}
		v.Reset(ssaop.OpAMD64Zero128)
		v.Type = t
		return true
	}
	// match: (ZeroSIMD <t>)
	// cond: t.Size() == 32
	// result: (Zero256 <t>)
	for {
		t := v.Type
		if !(t.Size() == 32) {
			break
		}
		v.Reset(ssaop.OpAMD64Zero256)
		v.Type = t
		return true
	}
	// match: (ZeroSIMD <t>)
	// cond: t.Size() == 64
	// result: (Zero512 <t>)
	for {
		t := v.Type
		if !(t.Size() == 64) {
			break
		}
		v.Reset(ssaop.OpAMD64Zero512)
		v.Type = t
		return true
	}
	return false
}
func rewriteValue_OpblendMaskedInt16x32(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (blendMaskedInt16x32 x y mask)
	// result: (VPBLENDMWMasked512 x y (VPMOVVec16x32ToM <types.TypeMask> mask))
	for {
		x := v_0
		y := v_1
		mask := v_2
		v.Reset(ssaop.OpAMD64VPBLENDMWMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x32ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(x, y, v0)
		return true
	}
}
func rewriteValue_OpblendMaskedInt32x16(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (blendMaskedInt32x16 x y mask)
	// result: (VPBLENDMDMasked512 x y (VPMOVVec32x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		y := v_1
		mask := v_2
		v.Reset(ssaop.OpAMD64VPBLENDMDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(x, y, v0)
		return true
	}
}
func rewriteValue_OpblendMaskedInt64x8(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (blendMaskedInt64x8 x y mask)
	// result: (VPBLENDMQMasked512 x y (VPMOVVec64x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		y := v_1
		mask := v_2
		v.Reset(ssaop.OpAMD64VPBLENDMQMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(x, y, v0)
		return true
	}
}
func rewriteValue_OpblendMaskedInt8x64(v *ssa.Value) bool {
	v_2 := v.Args[2]
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (blendMaskedInt8x64 x y mask)
	// result: (VPBLENDMBMasked512 x y (VPMOVVec8x64ToM <types.TypeMask> mask))
	for {
		x := v_0
		y := v_1
		mask := v_2
		v.Reset(ssaop.OpAMD64VPBLENDMBMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x64ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg3(x, y, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To16MaskedFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To16MaskedFloat32x4 x mask)
	// result: (VBROADCASTSSMasked512 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To16MaskedInt16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To16MaskedInt16x8 x mask)
	// result: (VPBROADCASTWMasked256 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To16MaskedInt32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To16MaskedInt32x4 x mask)
	// result: (VPBROADCASTDMasked512 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To16MaskedInt8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To16MaskedInt8x16 x mask)
	// result: (VPBROADCASTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To16MaskedUint16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To16MaskedUint16x8 x mask)
	// result: (VPBROADCASTWMasked256 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To16MaskedUint32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To16MaskedUint32x4 x mask)
	// result: (VPBROADCASTDMasked512 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To16MaskedUint8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To16MaskedUint8x16 x mask)
	// result: (VPBROADCASTBMasked128 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To2MaskedFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To2MaskedFloat64x2 x mask)
	// result: (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To2MaskedInt64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To2MaskedInt64x2 x mask)
	// result: (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To2MaskedUint64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To2MaskedUint64x2 x mask)
	// result: (VPBROADCASTQMasked128 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To32MaskedInt16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To32MaskedInt16x8 x mask)
	// result: (VPBROADCASTWMasked512 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To32MaskedInt8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To32MaskedInt8x16 x mask)
	// result: (VPBROADCASTBMasked256 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To32MaskedUint16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To32MaskedUint16x8 x mask)
	// result: (VPBROADCASTWMasked512 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To32MaskedUint8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To32MaskedUint8x16 x mask)
	// result: (VPBROADCASTBMasked256 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To4MaskedFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To4MaskedFloat32x4 x mask)
	// result: (VBROADCASTSSMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To4MaskedFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To4MaskedFloat64x2 x mask)
	// result: (VBROADCASTSDMasked256 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VBROADCASTSDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To4MaskedInt32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To4MaskedInt32x4 x mask)
	// result: (VPBROADCASTDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To4MaskedInt64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To4MaskedInt64x2 x mask)
	// result: (VPBROADCASTQMasked256 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To4MaskedUint32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To4MaskedUint32x4 x mask)
	// result: (VPBROADCASTDMasked128 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To4MaskedUint64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To4MaskedUint64x2 x mask)
	// result: (VPBROADCASTQMasked256 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To64MaskedInt8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To64MaskedInt8x16 x mask)
	// result: (VPBROADCASTBMasked512 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To64MaskedUint8x16(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To64MaskedUint8x16 x mask)
	// result: (VPBROADCASTBMasked512 x (VPMOVVec8x16ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTBMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec8x16ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To8MaskedFloat32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To8MaskedFloat32x4 x mask)
	// result: (VBROADCASTSSMasked256 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VBROADCASTSSMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To8MaskedFloat64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To8MaskedFloat64x2 x mask)
	// result: (VBROADCASTSDMasked512 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VBROADCASTSDMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To8MaskedInt16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To8MaskedInt16x8 x mask)
	// result: (VPBROADCASTWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To8MaskedInt32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To8MaskedInt32x4 x mask)
	// result: (VPBROADCASTDMasked256 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To8MaskedInt64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To8MaskedInt64x2 x mask)
	// result: (VPBROADCASTQMasked512 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To8MaskedUint16x8(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To8MaskedUint16x8 x mask)
	// result: (VPBROADCASTWMasked128 x (VPMOVVec16x8ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTWMasked128)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec16x8ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To8MaskedUint32x4(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To8MaskedUint32x4 x mask)
	// result: (VPBROADCASTDMasked256 x (VPMOVVec32x4ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTDMasked256)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec32x4ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func rewriteValue_Opbroadcast1To8MaskedUint64x2(v *ssa.Value) bool {
	v_1 := v.Args[1]
	v_0 := v.Args[0]
	b := v.Block
	// match: (broadcast1To8MaskedUint64x2 x mask)
	// result: (VPBROADCASTQMasked512 x (VPMOVVec64x2ToM <types.TypeMask> mask))
	for {
		x := v_0
		mask := v_1
		v.Reset(ssaop.OpAMD64VPBROADCASTQMasked512)
		v0 := b.NewValue0(v.Pos, ssaop.OpAMD64VPMOVVec64x2ToM, types.TypeMask)
		v0.AddArg(mask)
		v.AddArg2(x, v0)
		return true
	}
}
func RewriteBlock(b *ssa.Block) bool {
	typ := &b.Func.Config.Types
	switch b.Kind {
	case block.BlockAMD64EQ:
		// match: (EQ (TESTL (SHLL (MOVLconst [1]) x) y))
		// result: (UGE (BTL x y))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				if v_0_0.Op != ssaop.OpAMD64SHLL {
					continue
				}
				x := v_0_0.Args[1]
				v_0_0_0 := v_0_0.Args[0]
				if v_0_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0_0_0.AuxInt) != 1 {
					continue
				}
				y := v_0_1
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTL, types.TypeFlags)
				v0.AddArg2(x, y)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTQ (SHLQ (MOVQconst [1]) x) y))
		// result: (UGE (BTQ x y))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				if v_0_0.Op != ssaop.OpAMD64SHLQ {
					continue
				}
				x := v_0_0.Args[1]
				v_0_0_0 := v_0_0.Args[0]
				if v_0_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_0_0_0.AuxInt) != 1 {
					continue
				}
				y := v_0_1
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQ, types.TypeFlags)
				v0.AddArg2(x, y)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTLconst [c] x))
		// cond: ssa.IsPowerOfTwo(uint32(c))
		// result: (UGE (BTLconst [int8(ssa.Log32u(uint32(c)))] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTLconst {
			v_0 := b.Controls[0]
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_0.Args[0]
			if !(ssa.IsPowerOfTwo(uint32(c))) {
				break
			}
			v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
			v0.AddArg(x)
			b.ResetWithControl(block.BlockAMD64UGE, v0)
			return true
		}
		// match: (EQ (TESTQconst [c] x))
		// cond: ssa.IsPowerOfTwo(uint64(c))
		// result: (UGE (BTQconst [int8(ssa.Log32u(uint32(c)))] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQconst {
			v_0 := b.Controls[0]
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_0.Args[0]
			if !(ssa.IsPowerOfTwo(uint64(c))) {
				break
			}
			v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
			v0.AddArg(x)
			b.ResetWithControl(block.BlockAMD64UGE, v0)
			return true
		}
		// match: (EQ (TESTQ (MOVQconst [c]) x))
		// cond: ssa.IsPowerOfTwo(uint64(c))
		// result: (UGE (BTQconst [int8(ssa.Log64u(uint64(c)))] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				if v_0_0.Op != ssaop.OpAMD64MOVQconst {
					continue
				}
				c := ssa.AuxIntToInt64(v_0_0.AuxInt)
				x := v_0_1
				if !(ssa.IsPowerOfTwo(uint64(c))) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(c))))
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2))
		// cond: z1==z2
		// result: (UGE (BTQconst [63] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
					continue
				}
				z1_0 := z1.Args[0]
				if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
					continue
				}
				x := z1_0.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(63)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2))
		// cond: z1==z2
		// result: (UGE (BTQconst [31] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
					continue
				}
				z1_0 := z1.Args[0]
				if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
					continue
				}
				x := z1_0.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(31)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2))
		// cond: z1==z2
		// result: (UGE (BTQconst [0] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
					continue
				}
				z1_0 := z1.Args[0]
				if z1_0.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
					continue
				}
				x := z1_0.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(0)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2))
		// cond: z1==z2
		// result: (UGE (BTLconst [0] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
					continue
				}
				z1_0 := z1.Args[0]
				if z1_0.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
					continue
				}
				x := z1_0.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(0)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTQ z1:(SHRQconst [63] x) z2))
		// cond: z1==z2
		// result: (UGE (BTQconst [63] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
					continue
				}
				x := z1.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(63)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTL z1:(SHRLconst [31] x) z2))
		// cond: z1==z2
		// result: (UGE (BTLconst [31] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
					continue
				}
				x := z1.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(31)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64UGE, v0)
				return true
			}
			break
		}
		// match: (EQ (InvertFlags cmp) yes no)
		// result: (EQ cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64EQ, cmp)
			return true
		}
		// match: (EQ (FlagEQ) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (EQ (FlagLT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (EQ (FlagLT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (EQ (FlagGT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (EQ (FlagGT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (EQ (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no)
		// result: (EQ (Select1 <types.TypeFlags> blsr) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				s := v_0_0
				if s.Op != ssaop.OpSelect0 {
					continue
				}
				blsr := s.Args[0]
				if blsr.Op != ssaop.OpAMD64BLSRQ || s != v_0_1 {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpSelect1, types.TypeFlags)
				v0.AddArg(blsr)
				b.ResetWithControl(block.BlockAMD64EQ, v0)
				return true
			}
			break
		}
		// match: (EQ (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no)
		// result: (EQ (Select1 <types.TypeFlags> blsr) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				s := v_0_0
				if s.Op != ssaop.OpSelect0 {
					continue
				}
				blsr := s.Args[0]
				if blsr.Op != ssaop.OpAMD64BLSRL || s != v_0_1 {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpSelect1, types.TypeFlags)
				v0.AddArg(blsr)
				b.ResetWithControl(block.BlockAMD64EQ, v0)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ a:(ADDQconst [c] x) a))
		// cond: t.Uses == 1 && flagify(a)
		// result: (EQ (Select1 <types.TypeFlags> a.Args[0]))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				a := t_0
				if a.Op != ssaop.OpAMD64ADDQconst {
					continue
				}
				if a != t_1 || !(t.Uses == 1 && flagify(a)) {
					continue
				}
				v0 := b.NewValue0(t.Pos, ssaop.OpSelect1, types.TypeFlags)
				v0.AddArg(a.Args[0])
				b.ResetWithControl(block.BlockAMD64EQ, v0)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL a:(ADDLconst [c] x) a))
		// cond: t.Uses == 1 && flagify(a)
		// result: (EQ (Select1 <types.TypeFlags> a.Args[0]))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				a := t_0
				if a.Op != ssaop.OpAMD64ADDLconst {
					continue
				}
				if a != t_1 || !(t.Uses == 1 && flagify(a)) {
					continue
				}
				v0 := b.NewValue0(t.Pos, ssaop.OpSelect1, types.TypeFlags)
				v0.AddArg(a.Args[0])
				b.ResetWithControl(block.BlockAMD64EQ, v0)
				return true
			}
			break
		}
		// match: (EQ (VPTEST x:(VPAND128 j k) y) yes no)
		// cond: x == y && x.Uses == 2
		// result: (EQ (VPTEST j k) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64VPTEST {
			v_0 := b.Controls[0]
			y := v_0.Args[1]
			x := v_0.Args[0]
			if x.Op != ssaop.OpAMD64VPAND128 {
				break
			}
			_ = x.Args[1]
			x_0 := x.Args[0]
			x_1 := x.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, x_0, x_1 = _i0+1, x_1, x_0 {
				j := x_0
				k := x_1
				if !(x == y && x.Uses == 2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
				v0.AddArg2(j, k)
				b.ResetWithControl(block.BlockAMD64EQ, v0)
				return true
			}
			break
		}
		// match: (EQ (VPTEST x:(VPAND256 j k) y) yes no)
		// cond: x == y && x.Uses == 2
		// result: (EQ (VPTEST j k) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64VPTEST {
			v_0 := b.Controls[0]
			y := v_0.Args[1]
			x := v_0.Args[0]
			if x.Op != ssaop.OpAMD64VPAND256 {
				break
			}
			_ = x.Args[1]
			x_0 := x.Args[0]
			x_1 := x.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, x_0, x_1 = _i0+1, x_1, x_0 {
				j := x_0
				k := x_1
				if !(x == y && x.Uses == 2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
				v0.AddArg2(j, k)
				b.ResetWithControl(block.BlockAMD64EQ, v0)
				return true
			}
			break
		}
		// match: (EQ (VPTEST x:(VPANDD512 j k) y) yes no)
		// cond: x == y && x.Uses == 2
		// result: (EQ (VPTEST j k) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64VPTEST {
			v_0 := b.Controls[0]
			y := v_0.Args[1]
			x := v_0.Args[0]
			if x.Op != ssaop.OpAMD64VPANDD512 {
				break
			}
			_ = x.Args[1]
			x_0 := x.Args[0]
			x_1 := x.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, x_0, x_1 = _i0+1, x_1, x_0 {
				j := x_0
				k := x_1
				if !(x == y && x.Uses == 2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
				v0.AddArg2(j, k)
				b.ResetWithControl(block.BlockAMD64EQ, v0)
				return true
			}
			break
		}
		// match: (EQ (VPTEST x:(VPANDQ512 j k) y) yes no)
		// cond: x == y && x.Uses == 2
		// result: (EQ (VPTEST j k) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64VPTEST {
			v_0 := b.Controls[0]
			y := v_0.Args[1]
			x := v_0.Args[0]
			if x.Op != ssaop.OpAMD64VPANDQ512 {
				break
			}
			_ = x.Args[1]
			x_0 := x.Args[0]
			x_1 := x.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, x_0, x_1 = _i0+1, x_1, x_0 {
				j := x_0
				k := x_1
				if !(x == y && x.Uses == 2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
				v0.AddArg2(j, k)
				b.ResetWithControl(block.BlockAMD64EQ, v0)
				return true
			}
			break
		}
		// match: (EQ (VPTEST x:(VPANDN128 j k) y) yes no)
		// cond: x == y && x.Uses == 2
		// result: (ULT (VPTEST k j) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64VPTEST {
			v_0 := b.Controls[0]
			y := v_0.Args[1]
			x := v_0.Args[0]
			if x.Op != ssaop.OpAMD64VPANDN128 {
				break
			}
			k := x.Args[1]
			j := x.Args[0]
			if !(x == y && x.Uses == 2) {
				break
			}
			v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
			v0.AddArg2(k, j)
			b.ResetWithControl(block.BlockAMD64ULT, v0)
			return true
		}
		// match: (EQ (VPTEST x:(VPANDN256 j k) y) yes no)
		// cond: x == y && x.Uses == 2
		// result: (ULT (VPTEST k j) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64VPTEST {
			v_0 := b.Controls[0]
			y := v_0.Args[1]
			x := v_0.Args[0]
			if x.Op != ssaop.OpAMD64VPANDN256 {
				break
			}
			k := x.Args[1]
			j := x.Args[0]
			if !(x == y && x.Uses == 2) {
				break
			}
			v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
			v0.AddArg2(k, j)
			b.ResetWithControl(block.BlockAMD64ULT, v0)
			return true
		}
		// match: (EQ (VPTEST x:(VPANDND512 j k) y) yes no)
		// cond: x == y && x.Uses == 2
		// result: (ULT (VPTEST k j) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64VPTEST {
			v_0 := b.Controls[0]
			y := v_0.Args[1]
			x := v_0.Args[0]
			if x.Op != ssaop.OpAMD64VPANDND512 {
				break
			}
			k := x.Args[1]
			j := x.Args[0]
			if !(x == y && x.Uses == 2) {
				break
			}
			v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
			v0.AddArg2(k, j)
			b.ResetWithControl(block.BlockAMD64ULT, v0)
			return true
		}
		// match: (EQ (VPTEST x:(VPANDNQ512 j k) y) yes no)
		// cond: x == y && x.Uses == 2
		// result: (ULT (VPTEST k j) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64VPTEST {
			v_0 := b.Controls[0]
			y := v_0.Args[1]
			x := v_0.Args[0]
			if x.Op != ssaop.OpAMD64VPANDNQ512 {
				break
			}
			k := x.Args[1]
			j := x.Args[0]
			if !(x == y && x.Uses == 2) {
				break
			}
			v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64VPTEST, types.TypeFlags)
			v0.AddArg2(k, j)
			b.ResetWithControl(block.BlockAMD64ULT, v0)
			return true
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQ {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQ flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQ, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETL flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETL {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETG flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETG {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETLE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETA flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETA {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETB flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETB {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETAE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETBE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQ {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETNE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQ flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQ, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETL flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETL {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETG flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETG {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETLE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETLE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETGE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETA flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETA {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETB flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETB {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETAE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETAE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTL x:(MOVBQZX s:(SETBE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETBE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQ {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETNE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQ flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQ, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETL flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETL {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETG flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETG {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETLE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETLE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETGE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETA flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETA {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETB flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETB {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETAE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETAE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTW x:(MOVBQZX s:(SETBE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETBE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETEQ flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (NE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETEQ {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETNE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (EQ flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETNE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQ, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETL flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (GE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETL {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETG flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (LE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETG {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETLE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (GT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETLE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETGE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (LT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETGE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETA flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (ULE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETA {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETB flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETB {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETAE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (ULT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETAE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULT, flags)
				return true
			}
			break
		}
		// match: (EQ t:(TESTB s:(SETBE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETBE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
	case block.BlockAMD64GE:
		// match: (GE c:(CMPQconst [128] z) yes no)
		// cond: c.Uses == 1
		// result: (GT (CMPQconst [127] z) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64CMPQconst {
			c := b.Controls[0]
			if ssa.AuxIntToInt32(c.AuxInt) != 128 {
				break
			}
			z := c.Args[0]
			if !(c.Uses == 1) {
				break
			}
			v0 := b.NewValue0(c.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int32ToAuxInt(127)
			v0.AddArg(z)
			b.ResetWithControl(block.BlockAMD64GT, v0)
			return true
		}
		// match: (GE c:(CMPLconst [128] z) yes no)
		// cond: c.Uses == 1
		// result: (GT (CMPLconst [127] z) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64CMPLconst {
			c := b.Controls[0]
			if ssa.AuxIntToInt32(c.AuxInt) != 128 {
				break
			}
			z := c.Args[0]
			if !(c.Uses == 1) {
				break
			}
			v0 := b.NewValue0(c.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int32ToAuxInt(127)
			v0.AddArg(z)
			b.ResetWithControl(block.BlockAMD64GT, v0)
			return true
		}
		// match: (GE (InvertFlags cmp) yes no)
		// result: (LE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64LE, cmp)
			return true
		}
		// match: (GE (FlagEQ) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (GE (FlagLT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (GE (FlagLT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (GE (FlagGT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (GE (FlagGT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
	case block.BlockAMD64GT:
		// match: (GT (InvertFlags cmp) yes no)
		// result: (LT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64LT, cmp)
			return true
		}
		// match: (GT (FlagEQ) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (GT (FlagLT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (GT (FlagLT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (GT (FlagGT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (GT (FlagGT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
	case block.BlockIf:
		// match: (If (SETL cmp) yes no)
		// result: (LT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETL {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64LT, cmp)
			return true
		}
		// match: (If (SETLE cmp) yes no)
		// result: (LE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETLE {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64LE, cmp)
			return true
		}
		// match: (If (SETG cmp) yes no)
		// result: (GT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETG {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64GT, cmp)
			return true
		}
		// match: (If (SETGE cmp) yes no)
		// result: (GE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETGE {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64GE, cmp)
			return true
		}
		// match: (If (SETEQ cmp) yes no)
		// result: (EQ cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETEQ {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64EQ, cmp)
			return true
		}
		// match: (If (SETNE cmp) yes no)
		// result: (NE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETNE {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64NE, cmp)
			return true
		}
		// match: (If (SETB cmp) yes no)
		// result: (ULT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETB {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64ULT, cmp)
			return true
		}
		// match: (If (SETBE cmp) yes no)
		// result: (ULE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETBE {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64ULE, cmp)
			return true
		}
		// match: (If (SETA cmp) yes no)
		// result: (UGT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETA {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64UGT, cmp)
			return true
		}
		// match: (If (SETAE cmp) yes no)
		// result: (UGE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETAE {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64UGE, cmp)
			return true
		}
		// match: (If (SETO cmp) yes no)
		// result: (OS cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETO {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64OS, cmp)
			return true
		}
		// match: (If (SETGF cmp) yes no)
		// result: (UGT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETGF {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64UGT, cmp)
			return true
		}
		// match: (If (SETGEF cmp) yes no)
		// result: (UGE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETGEF {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64UGE, cmp)
			return true
		}
		// match: (If (SETEQF cmp) yes no)
		// result: (EQF cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETEQF {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64EQF, cmp)
			return true
		}
		// match: (If (SETNEF cmp) yes no)
		// result: (NEF cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64SETNEF {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64NEF, cmp)
			return true
		}
		// match: (If cond yes no)
		// result: (NE (TESTB cond cond) yes no)
		for {
			cond := b.Controls[0]
			v0 := b.NewValue0(cond.Pos, ssaop.OpAMD64TESTB, types.TypeFlags)
			v0.AddArg2(cond, cond)
			b.ResetWithControl(block.BlockAMD64NE, v0)
			return true
		}
	case block.BlockJumpTable:
		// match: (JumpTable idx)
		// result: (JUMPTABLE {ssa.MakeJumpTableSym(b)} idx (LEAQ <typ.Uintptr> {ssa.MakeJumpTableSym(b)} (SB)))
		for {
			idx := b.Controls[0]
			v0 := b.NewValue0(b.Pos, ssaop.OpAMD64LEAQ, typ.Uintptr)
			v0.Aux = ssa.SymToAux(ssa.MakeJumpTableSym(b))
			v1 := b.NewValue0(b.Pos, ssaop.OpSB, typ.Uintptr)
			v0.AddArg(v1)
			b.ResetWithControl2(block.BlockAMD64JUMPTABLE, idx, v0)
			b.Aux = ssa.SymToAux(ssa.MakeJumpTableSym(b))
			return true
		}
	case block.BlockAMD64LE:
		// match: (LE (InvertFlags cmp) yes no)
		// result: (GE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64GE, cmp)
			return true
		}
		// match: (LE (FlagEQ) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (LE (FlagLT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (LE (FlagLT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (LE (FlagGT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (LE (FlagGT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
	case block.BlockAMD64LT:
		// match: (LT c:(CMPQconst [128] z) yes no)
		// cond: c.Uses == 1
		// result: (LE (CMPQconst [127] z) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64CMPQconst {
			c := b.Controls[0]
			if ssa.AuxIntToInt32(c.AuxInt) != 128 {
				break
			}
			z := c.Args[0]
			if !(c.Uses == 1) {
				break
			}
			v0 := b.NewValue0(c.Pos, ssaop.OpAMD64CMPQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int32ToAuxInt(127)
			v0.AddArg(z)
			b.ResetWithControl(block.BlockAMD64LE, v0)
			return true
		}
		// match: (LT c:(CMPLconst [128] z) yes no)
		// cond: c.Uses == 1
		// result: (LE (CMPLconst [127] z) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64CMPLconst {
			c := b.Controls[0]
			if ssa.AuxIntToInt32(c.AuxInt) != 128 {
				break
			}
			z := c.Args[0]
			if !(c.Uses == 1) {
				break
			}
			v0 := b.NewValue0(c.Pos, ssaop.OpAMD64CMPLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int32ToAuxInt(127)
			v0.AddArg(z)
			b.ResetWithControl(block.BlockAMD64LE, v0)
			return true
		}
		// match: (LT (InvertFlags cmp) yes no)
		// result: (GT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64GT, cmp)
			return true
		}
		// match: (LT (FlagEQ) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (LT (FlagLT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (LT (FlagLT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (LT (FlagGT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (LT (FlagGT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
	case block.BlockAMD64NE:
		// match: (NE (TESTB (SETL cmp) (SETL cmp)) yes no)
		// result: (LT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETL {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETL || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64LT, cmp)
			return true
		}
		// match: (NE (TESTB (SETLE cmp) (SETLE cmp)) yes no)
		// result: (LE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETLE {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETLE || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64LE, cmp)
			return true
		}
		// match: (NE (TESTB (SETG cmp) (SETG cmp)) yes no)
		// result: (GT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETG {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETG || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64GT, cmp)
			return true
		}
		// match: (NE (TESTB (SETGE cmp) (SETGE cmp)) yes no)
		// result: (GE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETGE {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETGE || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64GE, cmp)
			return true
		}
		// match: (NE (TESTB (SETEQ cmp) (SETEQ cmp)) yes no)
		// result: (EQ cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETEQ {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETEQ || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64EQ, cmp)
			return true
		}
		// match: (NE (TESTB (SETNE cmp) (SETNE cmp)) yes no)
		// result: (NE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETNE {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETNE || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64NE, cmp)
			return true
		}
		// match: (NE (TESTB (SETB cmp) (SETB cmp)) yes no)
		// result: (ULT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETB {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETB || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64ULT, cmp)
			return true
		}
		// match: (NE (TESTB (SETBE cmp) (SETBE cmp)) yes no)
		// result: (ULE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETBE {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETBE || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64ULE, cmp)
			return true
		}
		// match: (NE (TESTB (SETA cmp) (SETA cmp)) yes no)
		// result: (UGT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETA {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETA || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64UGT, cmp)
			return true
		}
		// match: (NE (TESTB (SETAE cmp) (SETAE cmp)) yes no)
		// result: (UGE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETAE {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETAE || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64UGE, cmp)
			return true
		}
		// match: (NE (TESTB (SETO cmp) (SETO cmp)) yes no)
		// result: (OS cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETO {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETO || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64OS, cmp)
			return true
		}
		// match: (NE (TESTL (SHLL (MOVLconst [1]) x) y))
		// result: (ULT (BTL x y))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				if v_0_0.Op != ssaop.OpAMD64SHLL {
					continue
				}
				x := v_0_0.Args[1]
				v_0_0_0 := v_0_0.Args[0]
				if v_0_0_0.Op != ssaop.OpAMD64MOVLconst || ssa.AuxIntToInt32(v_0_0_0.AuxInt) != 1 {
					continue
				}
				y := v_0_1
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTL, types.TypeFlags)
				v0.AddArg2(x, y)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTQ (SHLQ (MOVQconst [1]) x) y))
		// result: (ULT (BTQ x y))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				if v_0_0.Op != ssaop.OpAMD64SHLQ {
					continue
				}
				x := v_0_0.Args[1]
				v_0_0_0 := v_0_0.Args[0]
				if v_0_0_0.Op != ssaop.OpAMD64MOVQconst || ssa.AuxIntToInt64(v_0_0_0.AuxInt) != 1 {
					continue
				}
				y := v_0_1
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQ, types.TypeFlags)
				v0.AddArg2(x, y)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTLconst [c] x))
		// cond: ssa.IsPowerOfTwo(uint32(c))
		// result: (ULT (BTLconst [int8(ssa.Log32u(uint32(c)))] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTLconst {
			v_0 := b.Controls[0]
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_0.Args[0]
			if !(ssa.IsPowerOfTwo(uint32(c))) {
				break
			}
			v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
			v0.AddArg(x)
			b.ResetWithControl(block.BlockAMD64ULT, v0)
			return true
		}
		// match: (NE (TESTQconst [c] x))
		// cond: ssa.IsPowerOfTwo(uint64(c))
		// result: (ULT (BTQconst [int8(ssa.Log32u(uint32(c)))] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQconst {
			v_0 := b.Controls[0]
			c := ssa.AuxIntToInt32(v_0.AuxInt)
			x := v_0.Args[0]
			if !(ssa.IsPowerOfTwo(uint64(c))) {
				break
			}
			v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
			v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log32u(uint32(c))))
			v0.AddArg(x)
			b.ResetWithControl(block.BlockAMD64ULT, v0)
			return true
		}
		// match: (NE (TESTQ (MOVQconst [c]) x))
		// cond: ssa.IsPowerOfTwo(uint64(c))
		// result: (ULT (BTQconst [int8(ssa.Log64u(uint64(c)))] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				if v_0_0.Op != ssaop.OpAMD64MOVQconst {
					continue
				}
				c := ssa.AuxIntToInt64(v_0_0.AuxInt)
				x := v_0_1
				if !(ssa.IsPowerOfTwo(uint64(c))) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(int8(ssa.Log64u(uint64(c))))
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTQ z1:(SHLQconst [63] (SHRQconst [63] x)) z2))
		// cond: z1==z2
		// result: (ULT (BTQconst [63] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
					continue
				}
				z1_0 := z1.Args[0]
				if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
					continue
				}
				x := z1_0.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(63)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTL z1:(SHLLconst [31] (SHRQconst [31] x)) z2))
		// cond: z1==z2
		// result: (ULT (BTQconst [31] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
					continue
				}
				z1_0 := z1.Args[0]
				if z1_0.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
					continue
				}
				x := z1_0.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(31)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTQ z1:(SHRQconst [63] (SHLQconst [63] x)) z2))
		// cond: z1==z2
		// result: (ULT (BTQconst [0] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
					continue
				}
				z1_0 := z1.Args[0]
				if z1_0.Op != ssaop.OpAMD64SHLQconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 63 {
					continue
				}
				x := z1_0.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(0)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTL z1:(SHRLconst [31] (SHLLconst [31] x)) z2))
		// cond: z1==z2
		// result: (ULT (BTLconst [0] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
					continue
				}
				z1_0 := z1.Args[0]
				if z1_0.Op != ssaop.OpAMD64SHLLconst || ssa.AuxIntToInt8(z1_0.AuxInt) != 31 {
					continue
				}
				x := z1_0.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(0)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTQ z1:(SHRQconst [63] x) z2))
		// cond: z1==z2
		// result: (ULT (BTQconst [63] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHRQconst || ssa.AuxIntToInt8(z1.AuxInt) != 63 {
					continue
				}
				x := z1.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTQconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(63)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTL z1:(SHRLconst [31] x) z2))
		// cond: z1==z2
		// result: (ULT (BTLconst [31] x))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				z1 := v_0_0
				if z1.Op != ssaop.OpAMD64SHRLconst || ssa.AuxIntToInt8(z1.AuxInt) != 31 {
					continue
				}
				x := z1.Args[0]
				z2 := v_0_1
				if !(z1 == z2) {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpAMD64BTLconst, types.TypeFlags)
				v0.AuxInt = ssa.Int8ToAuxInt(31)
				v0.AddArg(x)
				b.ResetWithControl(block.BlockAMD64ULT, v0)
				return true
			}
			break
		}
		// match: (NE (TESTB (SETGF cmp) (SETGF cmp)) yes no)
		// result: (UGT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETGF {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETGF || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64UGT, cmp)
			return true
		}
		// match: (NE (TESTB (SETGEF cmp) (SETGEF cmp)) yes no)
		// result: (UGE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETGEF {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETGEF || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64UGE, cmp)
			return true
		}
		// match: (NE (TESTB (SETEQF cmp) (SETEQF cmp)) yes no)
		// result: (EQF cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETEQF {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETEQF || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64EQF, cmp)
			return true
		}
		// match: (NE (TESTB (SETNEF cmp) (SETNEF cmp)) yes no)
		// result: (NEF cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			if v_0_0.Op != ssaop.OpAMD64SETNEF {
				break
			}
			cmp := v_0_0.Args[0]
			v_0_1 := v_0.Args[1]
			if v_0_1.Op != ssaop.OpAMD64SETNEF || cmp != v_0_1.Args[0] {
				break
			}
			b.ResetWithControl(block.BlockAMD64NEF, cmp)
			return true
		}
		// match: (NE (InvertFlags cmp) yes no)
		// result: (NE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64NE, cmp)
			return true
		}
		// match: (NE (FlagEQ) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (NE (FlagLT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (NE (FlagLT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (NE (FlagGT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (NE (FlagGT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (NE (TESTQ s:(Select0 blsr:(BLSRQ _)) s) yes no)
		// result: (NE (Select1 <types.TypeFlags> blsr) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				s := v_0_0
				if s.Op != ssaop.OpSelect0 {
					continue
				}
				blsr := s.Args[0]
				if blsr.Op != ssaop.OpAMD64BLSRQ || s != v_0_1 {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpSelect1, types.TypeFlags)
				v0.AddArg(blsr)
				b.ResetWithControl(block.BlockAMD64NE, v0)
				return true
			}
			break
		}
		// match: (NE (TESTL s:(Select0 blsr:(BLSRL _)) s) yes no)
		// result: (NE (Select1 <types.TypeFlags> blsr) yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			_ = v_0.Args[1]
			v_0_0 := v_0.Args[0]
			v_0_1 := v_0.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, v_0_0, v_0_1 = _i0+1, v_0_1, v_0_0 {
				s := v_0_0
				if s.Op != ssaop.OpSelect0 {
					continue
				}
				blsr := s.Args[0]
				if blsr.Op != ssaop.OpAMD64BLSRL || s != v_0_1 {
					continue
				}
				v0 := b.NewValue0(v_0.Pos, ssaop.OpSelect1, types.TypeFlags)
				v0.AddArg(blsr)
				b.ResetWithControl(block.BlockAMD64NE, v0)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ a:(ADDQconst [c] x) a))
		// cond: t.Uses == 1 && flagify(a)
		// result: (NE (Select1 <types.TypeFlags> a.Args[0]))
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				a := t_0
				if a.Op != ssaop.OpAMD64ADDQconst {
					continue
				}
				if a != t_1 || !(t.Uses == 1 && flagify(a)) {
					continue
				}
				v0 := b.NewValue0(t.Pos, ssaop.OpSelect1, types.TypeFlags)
				v0.AddArg(a.Args[0])
				b.ResetWithControl(block.BlockAMD64NE, v0)
				return true
			}
			break
		}
		// match: (NE t:(TESTL a:(ADDLconst [c] x) a))
		// cond: t.Uses == 1 && flagify(a)
		// result: (NE (Select1 <types.TypeFlags> a.Args[0]))
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				a := t_0
				if a.Op != ssaop.OpAMD64ADDLconst {
					continue
				}
				if a != t_1 || !(t.Uses == 1 && flagify(a)) {
					continue
				}
				v0 := b.NewValue0(t.Pos, ssaop.OpSelect1, types.TypeFlags)
				v0.AddArg(a.Args[0])
				b.ResetWithControl(block.BlockAMD64NE, v0)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETEQ flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQ flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQ {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQ, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETNE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETL flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETL {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETG flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETG {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETLE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETLE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETGE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETA flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETA {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETB flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETB {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETAE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETAE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETBE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETBE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETEQF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQF flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQF, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETNEF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NEF flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNEF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NEF, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETGF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTQ x:(MOVBQZX s:(SETGEF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGEF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETEQ flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQ flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQ {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQ, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETNE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETL flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETL {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETG flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETG {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETLE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETLE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETGE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETA flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETA {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETB flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETB {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETAE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETAE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETBE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETBE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETEQF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQF flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQF, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETNEF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NEF flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNEF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NEF, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETGF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTL x:(MOVBQZX s:(SETGEF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGEF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETEQ flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQ flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQ {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQ, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETNE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETL flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETL {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETG flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETG {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETLE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (LE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETLE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETGE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (GE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETA flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETA {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETB flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETB {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETAE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETAE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETBE flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (ULE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETBE {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETEQF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (EQF flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETEQF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQF, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETNEF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (NEF flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETNEF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NEF, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETGF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTW x:(MOVBQZX s:(SETGEF flags)) x) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				x := t_0
				if x.Op != ssaop.OpAMD64MOVBQZX {
					continue
				}
				s := x.Args[0]
				if s.Op != ssaop.OpAMD64SETGEF {
					continue
				}
				flags := s.Args[0]
				if x != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETEQ flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (EQ flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETEQ {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQ, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETNE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (NE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETNE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETL flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (LT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETL {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETG flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (GT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETG {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETLE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (LE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETLE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64LE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETGE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (GE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETGE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64GE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETA flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETA {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETB flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (ULT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETB {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETAE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETAE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETBE flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (ULE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETBE {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64ULE, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETEQF flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (EQF flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETEQF {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64EQF, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETNEF flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (NEF flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETNEF {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64NEF, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETGF flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (UGT flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETGF {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGT, flags)
				return true
			}
			break
		}
		// match: (NE t:(TESTB s:(SETGEF flags) s) yes no)
		// cond: t.Block == s.Block
		// result: (UGE flags yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			t := b.Controls[0]
			_ = t.Args[1]
			t_0 := t.Args[0]
			t_1 := t.Args[1]
			for _i0 := 0; _i0 <= 1; _i0, t_0, t_1 = _i0+1, t_1, t_0 {
				s := t_0
				if s.Op != ssaop.OpAMD64SETGEF {
					continue
				}
				flags := s.Args[0]
				if s != t_1 || !(t.Block == s.Block) {
					continue
				}
				b.ResetWithControl(block.BlockAMD64UGE, flags)
				return true
			}
			break
		}
	case block.BlockAMD64UGE:
		// match: (UGE (TESTQ x x) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			x := v_0.Args[1]
			if x != v_0.Args[0] {
				break
			}
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (UGE (TESTL x x) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			x := v_0.Args[1]
			if x != v_0.Args[0] {
				break
			}
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (UGE (TESTW x x) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			v_0 := b.Controls[0]
			x := v_0.Args[1]
			if x != v_0.Args[0] {
				break
			}
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (UGE (TESTB x x) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			x := v_0.Args[1]
			if x != v_0.Args[0] {
				break
			}
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (UGE (InvertFlags cmp) yes no)
		// result: (ULE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64ULE, cmp)
			return true
		}
		// match: (UGE (FlagEQ) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (UGE (FlagLT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (UGE (FlagLT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (UGE (FlagGT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (UGE (FlagGT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
	case block.BlockAMD64UGT:
		// match: (UGT (InvertFlags cmp) yes no)
		// result: (ULT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64ULT, cmp)
			return true
		}
		// match: (UGT (FlagEQ) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (UGT (FlagLT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (UGT (FlagLT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (UGT (FlagGT_ULT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (UGT (FlagGT_UGT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			return true
		}
	case block.BlockAMD64ULE:
		// match: (ULE (InvertFlags cmp) yes no)
		// result: (UGE cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64UGE, cmp)
			return true
		}
		// match: (ULE (FlagEQ) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (ULE (FlagLT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (ULE (FlagLT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (ULE (FlagGT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (ULE (FlagGT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
	case block.BlockAMD64ULT:
		// match: (ULT (TESTQ x x) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64TESTQ {
			v_0 := b.Controls[0]
			x := v_0.Args[1]
			if x != v_0.Args[0] {
				break
			}
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (ULT (TESTL x x) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64TESTL {
			v_0 := b.Controls[0]
			x := v_0.Args[1]
			if x != v_0.Args[0] {
				break
			}
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (ULT (TESTW x x) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64TESTW {
			v_0 := b.Controls[0]
			x := v_0.Args[1]
			if x != v_0.Args[0] {
				break
			}
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (ULT (TESTB x x) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64TESTB {
			v_0 := b.Controls[0]
			x := v_0.Args[1]
			if x != v_0.Args[0] {
				break
			}
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (ULT (InvertFlags cmp) yes no)
		// result: (UGT cmp yes no)
		for b.Controls[0].Op == ssaop.OpAMD64InvertFlags {
			v_0 := b.Controls[0]
			cmp := v_0.Args[0]
			b.ResetWithControl(block.BlockAMD64UGT, cmp)
			return true
		}
		// match: (ULT (FlagEQ) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagEQ {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (ULT (FlagLT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (ULT (FlagLT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagLT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
		// match: (ULT (FlagGT_ULT) yes no)
		// result: (First yes no)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_ULT {
			b.Reset(block.BlockFirst)
			return true
		}
		// match: (ULT (FlagGT_UGT) yes no)
		// result: (First no yes)
		for b.Controls[0].Op == ssaop.OpAMD64FlagGT_UGT {
			b.Reset(block.BlockFirst)
			b.SwapSuccessors()
			return true
		}
	}
	return false
}