1
2
3
4
5 package loong64
6
7 import (
8 "cmd/internal/obj"
9 "cmd/internal/objabi"
10 "fmt"
11 "log"
12 "math/bits"
13 "slices"
14 )
15
16
17
18
19 type ctxt0 struct {
20 ctxt *obj.Link
21 newprog obj.ProgAlloc
22 cursym *obj.LSym
23 autosize int32
24 instoffset int64
25 pc int64
26 }
27
28
29
30 const (
31 FuncAlign = 4
32 loopAlign = 16
33 )
34
35 type Optab struct {
36 as obj.As
37 from1 uint8
38 reg uint8
39 from3 uint8
40 to1 uint8
41 to2 uint8
42 type_ int8
43 size int8
44 param int16
45 flag uint8
46 }
47
48 const (
49 NOTUSETMP = 1 << iota
50
51
52
53 branchLoopHead
54 )
55
56 var optab = []Optab{
57 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, C_NONE, 0, 0, 0, 0},
58
59 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
60 {AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
61 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
62 {AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
63 {AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
64
65 {ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
66 {ASUBV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
67 {AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
68 {AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
69 {AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
70 {ASUB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
71 {ASUBV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
72 {AADD, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
73 {AADDV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
74 {AAND, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
75 {ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
76 {ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
77 {AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
78 {ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
79 {ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
80 {ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
81 {ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
82 {AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
83 {AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
84 {AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
85 {AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
86 {AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
87 {AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
88 {ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
89
90 {AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
91 {AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
92 {AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0},
93 {AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0},
94 {AVANDV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
95 {AVANDV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
96 {AXVANDV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
97 {AXVANDV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
98 {AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
99 {AVANDB, C_U8CON, C_NONE, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
100 {AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
101 {AXVANDB, C_U8CON, C_NONE, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
102
103 {AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
104 {AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
105 {AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
106 {AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
107
108 {AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
109 {AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
110 {AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
111 {AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
112 {AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
113 {AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
114 {AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
115 {AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
116
117 {AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
118 {AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
119 {AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
120 {AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
121 {AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
122 {AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
123 {AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
124 {AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
125
126 {AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
127 {AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
128 {AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
129 {AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
130 {AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
131 {AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
132 {AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
133 {AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
134
135 {AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
136 {AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
137 {AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
138 {AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
139 {AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
140 {AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
141 {AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
142 {AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
143
144 {ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
145 {AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
146 {AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
147 {AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
148 {AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
149 {AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0},
150 {AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0},
151 {AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
152 {AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
153
154 {AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
155 {AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
156
157 {AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
158 {AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
159
160 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
161 {AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
162 {AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
163 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
164 {AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
165 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
166 {AMOVWU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
167 {AMOVV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
168 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
169 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
170 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
171 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
172 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
173 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
174 {ASC, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
175 {ASCV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
176
177 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
178 {AMOVWU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
179 {AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
180 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
181 {AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
182 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
183 {AMOVWU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
184 {AMOVV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
185 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
186 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
187 {AVMOVQ, C_SOREG, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
188 {AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
189 {AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
190 {AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
191 {ALL, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
192 {ALLV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
193
194 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
195 {AMOVWU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
196 {AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
197 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
198 {AMOVBU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
199 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
200 {AMOVWU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
201 {AMOVV, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
202 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
203 {AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
204 {ASC, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
205 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
206 {AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
207 {AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
208 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
209 {AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
210 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
211 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
212 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
213 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
214 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
215 {AMOVWP, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 73, 4, 0, 0},
216 {AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 73, 4, 0, 0},
217
218 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
219 {AMOVWU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
220 {AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
221 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
222 {AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
223 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
224 {AMOVWU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
225 {AMOVV, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
226 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
227 {AMOVBU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
228 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
229 {AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
230 {AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
231 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
232 {AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
233 {AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
234 {AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
235 {AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
236 {AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
237 {AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
238 {AMOVWP, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0},
239 {AMOVWP, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0},
240
241 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
242 {AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
243 {AMOVW, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
244 {AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
245
246 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
247 {AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
248 {AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
249 {AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
250
251 {AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
252 {AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
253 {AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
254 {AMOVV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
255 {AMOVV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 67, 4, 0, NOTUSETMP},
256 {AMOVV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 68, 8, 0, NOTUSETMP},
257 {AMOVV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 69, 12, 0, NOTUSETMP},
258 {AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
259
260 {AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
261 {AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
262 {AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
263 {AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
264
265 {AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
266 {AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
267 {AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
268 {AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
269
270 {AADDV16, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
271 {AADDV16, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
272
273 {AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
274 {AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
275 {AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
276 {AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
277
278 {AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
279 {AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
280 {AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
281 {AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
282 {AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
283 {AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
284
285 {AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
286 {AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
287 {AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
288 {AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
289 {AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
290 {AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
291
292 {AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
293 {AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
294 {AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
295 {AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
296 {AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
297 {AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
298 {AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
299 {AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
300 {AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
301 {AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
302 {AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
303 {AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
304 {AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
305 {AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
306 {AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
307 {AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
308
309 {ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
310 {ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
311
312 {ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
313 {ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
314
315 {ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0},
316 {ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
317 {ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
318
319 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
320 {ASYSCALL, C_U15CON, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
321
322 {ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
323 {ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
324 {ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
325 {ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
326 {ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
327
328 {AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
329 {AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0},
330
331 {AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0},
332 {AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0},
333
334 {AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
335 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
336 {AMOVF, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
337 {AMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
338
339 {AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
340 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
341 {AMOVF, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
342 {AMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
343 {AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
344 {AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
345
346 {AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
347 {AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
348 {AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0},
349 {AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0},
350
351 {AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
352 {AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
353 {AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0},
354 {AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0},
355 {AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
356 {AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
357
358 {AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
359 {AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
360 {AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
361 {AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
362 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
363 {AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
364 {AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
365 {AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0},
366 {AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
367 {AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
368
369 {AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0},
370
371 {AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
372 {AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
373 {AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
374 {AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
375 {AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
376
377 {AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
378 {AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
379 {AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
380 {AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
381 {AMOVWU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
382
383 {AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0},
384 {AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0},
385
386 {AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0},
387
388 {ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
389 {ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
390
391 {ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0},
392 {AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0},
393 {ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
394
395
396 {AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
397 {AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
398 {AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
399 {AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
400 {AMOVD, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
401 {AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
402 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
403
404
405 {AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
406 {AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
407 {AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
408 {AMOVWU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
409 {AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
410 {AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
411 {AMOVD, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
412 {AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0},
413 {AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0},
414
415 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
416 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
417 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
418 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
419
420 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 43, 4, 0, 0},
421 {AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 44, 4, 0, 0},
422
423 {AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
424 {AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
425 {AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0},
426
427 {AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
428
429 {AVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
430 {AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
431
432 {APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
433 {APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
434
435 {AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
436
437 {obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
438 {obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
439 {obj.APCDATA, C_DCON, C_NONE, C_NONE, C_DCON, C_NONE, 0, 0, 0, 0},
440 {obj.AFUNCDATA, C_U12CON, C_NONE, C_NONE, C_ADDR, C_NONE, 0, 0, 0, 0},
441 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
442 {obj.ANOP, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
443 {obj.ANOP, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
444 {obj.ANOP, C_REG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
445 {obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
446 }
447
448 var atomicInst = map[obj.As]uint32{
449 AAMSWAPB: 0x070B8 << 15,
450 AAMSWAPH: 0x070B9 << 15,
451 AAMSWAPW: 0x070C0 << 15,
452 AAMSWAPV: 0x070C1 << 15,
453 AAMCASB: 0x070B0 << 15,
454 AAMCASH: 0x070B1 << 15,
455 AAMCASW: 0x070B2 << 15,
456 AAMCASV: 0x070B3 << 15,
457 AAMADDW: 0x070C2 << 15,
458 AAMADDV: 0x070C3 << 15,
459 AAMANDW: 0x070C4 << 15,
460 AAMANDV: 0x070C5 << 15,
461 AAMORW: 0x070C6 << 15,
462 AAMORV: 0x070C7 << 15,
463 AAMXORW: 0x070C8 << 15,
464 AAMXORV: 0x070C9 << 15,
465 AAMMAXW: 0x070CA << 15,
466 AAMMAXV: 0x070CB << 15,
467 AAMMINW: 0x070CC << 15,
468 AAMMINV: 0x070CD << 15,
469 AAMMAXWU: 0x070CE << 15,
470 AAMMAXVU: 0x070CF << 15,
471 AAMMINWU: 0x070D0 << 15,
472 AAMMINVU: 0x070D1 << 15,
473 AAMSWAPDBB: 0x070BC << 15,
474 AAMSWAPDBH: 0x070BD << 15,
475 AAMSWAPDBW: 0x070D2 << 15,
476 AAMSWAPDBV: 0x070D3 << 15,
477 AAMCASDBB: 0x070B4 << 15,
478 AAMCASDBH: 0x070B5 << 15,
479 AAMCASDBW: 0x070B6 << 15,
480 AAMCASDBV: 0x070B7 << 15,
481 AAMADDDBW: 0x070D4 << 15,
482 AAMADDDBV: 0x070D5 << 15,
483 AAMANDDBW: 0x070D6 << 15,
484 AAMANDDBV: 0x070D7 << 15,
485 AAMORDBW: 0x070D8 << 15,
486 AAMORDBV: 0x070D9 << 15,
487 AAMXORDBW: 0x070DA << 15,
488 AAMXORDBV: 0x070DB << 15,
489 AAMMAXDBW: 0x070DC << 15,
490 AAMMAXDBV: 0x070DD << 15,
491 AAMMINDBW: 0x070DE << 15,
492 AAMMINDBV: 0x070DF << 15,
493 AAMMAXDBWU: 0x070E0 << 15,
494 AAMMAXDBVU: 0x070E1 << 15,
495 AAMMINDBWU: 0x070E2 << 15,
496 AAMMINDBVU: 0x070E3 << 15,
497 }
498
499 func IsAtomicInst(as obj.As) bool {
500 _, ok := atomicInst[as]
501
502 return ok
503 }
504
505
506
507 func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int {
508 if !((alignedValue&(alignedValue-1) == 0) && 8 <= alignedValue && alignedValue <= 2048) {
509 ctxt.Diag("alignment value of an instruction must be a power of two and in the range [8, 2048], got %d\n", alignedValue)
510 }
511 return int(-pc & (alignedValue - 1))
512 }
513
514 var oprange [ALAST & obj.AMask][]Optab
515
516 var xcmp [C_NCLASS][C_NCLASS]bool
517
518 func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
519 if ctxt.Retpoline {
520 ctxt.Diag("-spectre=ret not supported on loong64")
521 ctxt.Retpoline = false
522 }
523
524 p := cursym.Func().Text
525 if p == nil || p.Link == nil {
526 return
527 }
528
529 c := ctxt0{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset + ctxt.Arch.FixedFrameSize)}
530
531 if oprange[AOR&obj.AMask] == nil {
532 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
533 }
534
535 pc := int64(0)
536 p.Pc = pc
537
538 var m int
539 var o *Optab
540 for p = p.Link; p != nil; p = p.Link {
541 p.Pc = pc
542 o = c.oplook(p)
543 m = int(o.size)
544 if m == 0 {
545 switch p.As {
546 case obj.APCALIGN:
547 alignedValue := p.From.Offset
548 m = pcAlignPadLength(ctxt, pc, alignedValue)
549
550 if int32(alignedValue) > cursym.Func().Align {
551 cursym.Func().Align = int32(alignedValue)
552 }
553 break
554 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
555 continue
556 default:
557 c.ctxt.Diag("zero-width instruction\n%v", p)
558 }
559 }
560
561 pc += int64(m)
562 }
563
564 c.cursym.Size = pc
565
566
567
568 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
569 if q := p.To.Target(); q != nil && q.Pc < p.Pc {
570 q.Mark |= branchLoopHead
571 }
572 }
573
574
575 for {
576 rescan := false
577 pc = 0
578 prev := c.cursym.Func().Text
579 for p = prev.Link; p != nil; prev, p = p, p.Link {
580 p.Pc = pc
581 o = c.oplook(p)
582
583
584
585
586
587
588
589 if p.Mark&branchLoopHead != 0 && pc&(loopAlign-1) != 0 &&
590 !(prev.As == obj.APCALIGN && prev.From.Offset >= loopAlign) {
591 q := c.newprog()
592 prev.Link = q
593 q.Link = p
594 q.Pc = pc
595 q.As = obj.APCALIGN
596 q.From.Type = obj.TYPE_CONST
597 q.From.Offset = loopAlign
598
599
600
601
602
603
604
605 pc += int64(pcAlignPadLength(ctxt, pc, loopAlign))
606 p.Pc = pc
607 rescan = true
608 }
609
610
611
612
613
614 if o.type_ == 6 && p.To.Target() != nil {
615 otxt := p.To.Target().Pc - pc
616
617
618
619
620
621 bound := int64(1 << (18 - 1))
622
623 switch p.As {
624 case ABFPT, ABFPF:
625 bound = int64(1 << (23 - 1))
626 }
627
628 if otxt < -bound || otxt >= bound {
629 q := c.newprog()
630 q.Link = p.Link
631 p.Link = q
632 q.As = AJMP
633 q.Pos = p.Pos
634 q.To.Type = obj.TYPE_BRANCH
635 q.To.SetTarget(p.To.Target())
636 p.To.SetTarget(q)
637 q = c.newprog()
638 q.Link = p.Link
639 p.Link = q
640 q.As = AJMP
641 q.Pos = p.Pos
642 q.To.Type = obj.TYPE_BRANCH
643 q.To.SetTarget(q.Link.Link)
644 rescan = true
645 }
646 }
647
648 m = int(o.size)
649 if m == 0 {
650 switch p.As {
651 case obj.APCALIGN:
652 alignedValue := p.From.Offset
653 m = pcAlignPadLength(ctxt, pc, alignedValue)
654 break
655 case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
656 continue
657 default:
658 c.ctxt.Diag("zero-width instruction\n%v", p)
659 }
660 }
661
662 pc += int64(m)
663 }
664
665 c.cursym.Size = pc
666
667 if !rescan {
668 break
669 }
670 }
671
672 pc += -pc & (FuncAlign - 1)
673 c.cursym.Size = pc
674
675
676
677 c.cursym.Grow(c.cursym.Size)
678
679 bp := c.cursym.P
680 var i int32
681 var out [5]uint32
682 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
683 c.pc = p.Pc
684 o = c.oplook(p)
685 if int(o.size) > 4*len(out) {
686 log.Fatalf("out array in span0 is too small, need at least %d for %v", o.size/4, p)
687 }
688 if p.As == obj.APCALIGN {
689 alignedValue := p.From.Offset
690 v := pcAlignPadLength(c.ctxt, p.Pc, alignedValue)
691 for i = 0; i < int32(v/4); i++ {
692
693 c.ctxt.Arch.ByteOrder.PutUint32(bp, OP_12IRR(c.opirr(AAND), 0, 0, 0))
694 bp = bp[4:]
695 }
696 continue
697 }
698 c.asmout(p, o, out[:])
699 for i = 0; i < int32(o.size/4); i++ {
700 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
701 bp = bp[4:]
702 }
703 }
704
705
706
707
708
709 obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, c.isRestartable)
710 }
711
712
713 func (c *ctxt0) isUnsafePoint(p *obj.Prog) bool {
714
715
716 return p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP
717 }
718
719
720
721 func (c *ctxt0) isRestartable(p *obj.Prog) bool {
722 if c.isUnsafePoint(p) {
723 return false
724 }
725
726
727
728
729
730
731
732 o := c.oplook(p)
733 return o.size > 4 && o.flag&NOTUSETMP == 0
734 }
735
736 func isint32(v int64) bool {
737 return int64(int32(v)) == v
738 }
739
740 func (c *ctxt0) aclass(a *obj.Addr) int {
741 switch a.Type {
742 case obj.TYPE_NONE:
743 return C_NONE
744
745 case obj.TYPE_REG:
746 return c.rclass(a.Reg)
747
748 case obj.TYPE_MEM:
749 switch a.Name {
750 case obj.NAME_EXTERN,
751 obj.NAME_STATIC:
752 if a.Sym == nil {
753 break
754 }
755 c.instoffset = a.Offset
756 if a.Sym.Type == objabi.STLSBSS {
757 if c.ctxt.Flag_shared {
758 return C_TLS_IE
759 } else {
760 return C_TLS_LE
761 }
762 }
763 return C_ADDR
764
765 case obj.NAME_AUTO:
766 if a.Reg == REGSP {
767
768
769 a.Reg = obj.REG_NONE
770 }
771 c.instoffset = int64(c.autosize) + a.Offset
772 if c.instoffset >= -BIG && c.instoffset < BIG {
773 return C_SAUTO
774 }
775 return C_LAUTO
776
777 case obj.NAME_PARAM:
778 if a.Reg == REGSP {
779
780
781 a.Reg = obj.REG_NONE
782 }
783 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
784 if c.instoffset >= -BIG && c.instoffset < BIG {
785 return C_SAUTO
786 }
787 return C_LAUTO
788
789 case obj.NAME_NONE:
790 if a.Index != 0 {
791 if a.Offset != 0 {
792 return C_GOK
793 }
794
795 return C_ROFF
796 }
797
798 c.instoffset = a.Offset
799 if c.instoffset == 0 {
800 return C_ZOREG
801 }
802 if c.instoffset >= -BIG && c.instoffset < BIG {
803 return C_SOREG
804 }
805 return C_LOREG
806
807 case obj.NAME_GOTREF:
808 return C_GOTADDR
809 }
810
811 return C_GOK
812
813 case obj.TYPE_TEXTSIZE:
814 return C_TEXTSIZE
815
816 case obj.TYPE_CONST,
817 obj.TYPE_ADDR:
818 switch a.Name {
819 case obj.NAME_NONE:
820 c.instoffset = a.Offset
821 if a.Reg != 0 {
822 if -BIG <= c.instoffset && c.instoffset <= BIG {
823 return C_SACON
824 }
825 if isint32(c.instoffset) {
826 return C_LACON
827 }
828 return C_DACON
829 }
830
831 case obj.NAME_EXTERN,
832 obj.NAME_STATIC:
833 s := a.Sym
834 if s == nil {
835 return C_GOK
836 }
837
838 c.instoffset = a.Offset
839 if s.Type == objabi.STLSBSS {
840 c.ctxt.Diag("taking address of TLS variable is not supported")
841 }
842 return C_EXTADDR
843
844 case obj.NAME_AUTO:
845 if a.Reg == REGSP {
846
847
848 a.Reg = obj.REG_NONE
849 }
850 c.instoffset = int64(c.autosize) + a.Offset
851 if c.instoffset >= -BIG && c.instoffset < BIG {
852 return C_SACON
853 }
854 return C_LACON
855
856 case obj.NAME_PARAM:
857 if a.Reg == REGSP {
858
859
860 a.Reg = obj.REG_NONE
861 }
862 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
863 if c.instoffset >= -BIG && c.instoffset < BIG {
864 return C_SACON
865 }
866 return C_LACON
867
868 default:
869 return C_GOK
870 }
871
872 if c.instoffset != int64(int32(c.instoffset)) {
873 return dconClass(c.instoffset)
874 }
875
876 if c.instoffset >= 0 {
877 sbits := bits.Len64(uint64(c.instoffset))
878 switch {
879 case sbits <= 8:
880 return C_ZCON + sbits
881 case sbits <= 12:
882 if c.instoffset <= 0x7ff {
883 return C_US12CON
884 }
885 return C_U12CON
886 case sbits <= 13:
887 if c.instoffset&0xfff == 0 {
888 return C_U13CON20_0
889 }
890 return C_U13CON
891 case sbits <= 15:
892 if c.instoffset&0xfff == 0 {
893 return C_U15CON20_0
894 }
895 return C_U15CON
896 }
897 } else {
898 sbits := bits.Len64(uint64(^c.instoffset))
899 switch {
900 case sbits < 5:
901 return C_S5CON
902 case sbits < 12:
903 return C_S12CON
904 case sbits < 13:
905 if c.instoffset&0xfff == 0 {
906 return C_S13CON20_0
907 }
908 return C_S13CON
909 }
910 }
911
912 if c.instoffset&0xfff == 0 {
913 return C_32CON20_0
914 }
915 return C_32CON
916
917 case obj.TYPE_BRANCH:
918 return C_BRAN
919 }
920
921 return C_GOK
922 }
923
924
925
926
927
928
929
930 const (
931 ALL1 = iota
932 ALL0
933 ST1
934 ST0
935 )
936
937
938
939 func mask(suf int8, len int8) (uint64, uint64) {
940 if len == 12 {
941 if suf == 0 {
942 return 0xfff, 0x800
943 } else {
944 return 0xfff0000000000000, 0x8000000000000000
945 }
946 } else {
947 if suf == 12 {
948 return 0xfffff000, 0x80000000
949 } else {
950 return 0xfffff00000000, 0x8000000000000
951 }
952 }
953 }
954
955
956
957
958
959 func bitField(val int64, suf int8, len int8) int8 {
960 mask1, mask2 := mask(suf, len)
961 if uint64(val)&mask1 == mask1 {
962 return ALL1
963 } else if uint64(val)&mask1 == 0x0 {
964 return ALL0
965 } else if uint64(val)&mask2 == mask2 {
966 return ST1
967 } else {
968 return ST0
969 }
970 }
971
972
973
974
975
976
977
978
979
980 func dconClass(offset int64) int {
981 tzb := bits.TrailingZeros64(uint64(offset))
982 hi12 := bitField(offset, 52, 12)
983 hi20 := bitField(offset, 32, 20)
984 lo20 := bitField(offset, 12, 20)
985 lo12 := bitField(offset, 0, 12)
986 if tzb >= 52 {
987 return C_DCON12_0
988 }
989 if tzb >= 32 {
990 if ((hi20 == ALL1 || hi20 == ST1) && hi12 == ALL1) || ((hi20 == ALL0 || hi20 == ST0) && hi12 == ALL0) {
991 return C_DCON20S_0
992 }
993 return C_DCON32_0
994 }
995 if tzb >= 12 {
996 if lo20 == ST1 || lo20 == ALL1 {
997 if hi20 == ALL1 {
998 return C_DCON12_20S
999 }
1000 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1001 return C_DCON20S_20
1002 }
1003 return C_DCON32_20
1004 }
1005 if hi20 == ALL0 {
1006 return C_DCON12_20S
1007 }
1008 if (hi20 == ST0 && hi12 == ALL0) || ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) {
1009 return C_DCON20S_20
1010 }
1011 return C_DCON32_20
1012 }
1013 if lo12 == ST1 || lo12 == ALL1 {
1014 if lo20 == ALL1 {
1015 if hi20 == ALL1 {
1016 return C_DCON12_12S
1017 }
1018 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1019 return C_DCON20S_12S
1020 }
1021 return C_DCON32_12S
1022 }
1023 if lo20 == ST1 {
1024 if hi20 == ALL1 {
1025
1026 return C_DCON12_32S
1027 }
1028 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1029 return C_DCON20S_32
1030 }
1031 return C_DCON
1032 }
1033 if lo20 == ALL0 {
1034 if hi20 == ALL0 {
1035 return C_DCON12_12U
1036 }
1037 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1038 return C_DCON20S_12U
1039 }
1040 return C_DCON32_12U
1041 }
1042 if hi20 == ALL0 {
1043 return C_DCON12_32S
1044 }
1045 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1046 return C_DCON20S_32
1047 }
1048 return C_DCON
1049 }
1050 if lo20 == ALL0 {
1051 if hi20 == ALL0 {
1052 return C_DCON12_12U
1053 }
1054 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1055 return C_DCON20S_12U
1056 }
1057 return C_DCON32_12U
1058 }
1059 if lo20 == ST1 || lo20 == ALL1 {
1060 if hi20 == ALL1 {
1061 return C_DCON12_32S
1062 }
1063 if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
1064 return C_DCON20S_32
1065 }
1066 return C_DCON
1067 }
1068 if hi20 == ALL0 {
1069 return C_DCON12_32S
1070 }
1071 if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
1072 return C_DCON20S_32
1073 }
1074 return C_DCON
1075 }
1076
1077
1078
1079 func (c *ctxt0) rclass(r int16) int {
1080 switch {
1081 case REG_R0 <= r && r <= REG_R31:
1082 return C_REG
1083 case REG_F0 <= r && r <= REG_F31:
1084 return C_FREG
1085 case REG_FCC0 <= r && r <= REG_FCC7:
1086 return C_FCCREG
1087 case REG_FCSR0 <= r && r <= REG_FCSR3:
1088 return C_FCSRREG
1089 case REG_V0 <= r && r <= REG_V31:
1090 return C_VREG
1091 case REG_X0 <= r && r <= REG_X31:
1092 return C_XREG
1093 case r >= REG_ARNG && r < REG_ELEM:
1094 return C_ARNG
1095 case r >= REG_ELEM && r < REG_ELEM_END:
1096 return C_ELEM
1097 }
1098
1099 return C_GOK
1100 }
1101
1102 func oclass(a *obj.Addr) int {
1103 return int(a.Class) - 1
1104 }
1105
1106 func prasm(p *obj.Prog) {
1107 fmt.Printf("%v\n", p)
1108 }
1109
1110 func (c *ctxt0) oplook(p *obj.Prog) *Optab {
1111 if oprange[AOR&obj.AMask] == nil {
1112 c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
1113 }
1114
1115 restArgsIndex := 0
1116 restArgsLen := len(p.RestArgs)
1117 if restArgsLen > 2 {
1118 c.ctxt.Diag("too many RestArgs: got %v, maximum is 2\n", restArgsLen)
1119 return nil
1120 }
1121
1122 restArgsv := [2]int{C_NONE + 1, C_NONE + 1}
1123 for i, ap := range p.RestArgs {
1124 restArgsv[i] = int(ap.Addr.Class)
1125 if restArgsv[i] == 0 {
1126 restArgsv[i] = c.aclass(&ap.Addr) + 1
1127 ap.Addr.Class = int8(restArgsv[i])
1128 }
1129 }
1130
1131 a1 := int(p.Optab)
1132 if a1 != 0 {
1133 return &optab[a1-1]
1134 }
1135
1136
1137 a1 = int(p.From.Class)
1138 if a1 == 0 {
1139 a1 = c.aclass(&p.From) + 1
1140 p.From.Class = int8(a1)
1141 }
1142 a1--
1143
1144
1145 a4 := int(p.To.Class)
1146 if a4 == 0 {
1147 a4 = c.aclass(&p.To) + 1
1148 p.To.Class = int8(a4)
1149 }
1150 a4--
1151
1152
1153 a2 := C_NONE
1154 if p.Reg != 0 {
1155 a2 = c.rclass(p.Reg)
1156 } else if restArgsLen > 0 {
1157 a2 = restArgsv[restArgsIndex] - 1
1158 restArgsIndex++
1159 }
1160
1161
1162 a5 := C_NONE
1163 if p.RegTo2 != 0 {
1164 a5 = C_REG
1165 }
1166
1167
1168 a3 := C_NONE
1169 if restArgsLen > 0 && restArgsIndex < restArgsLen {
1170 a3 = restArgsv[restArgsIndex] - 1
1171 restArgsIndex++
1172 }
1173
1174 ops := oprange[p.As&obj.AMask]
1175 c1 := &xcmp[a1]
1176 c2 := &xcmp[a2]
1177 c3 := &xcmp[a3]
1178 c4 := &xcmp[a4]
1179 c5 := &xcmp[a5]
1180 for i := range ops {
1181 op := &ops[i]
1182 if c1[op.from1] && c2[op.reg] && c3[op.from3] && c4[op.to1] && c5[op.to2] {
1183 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1184 return op
1185 }
1186 }
1187
1188 c.ctxt.Diag("illegal combination %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5))
1189 prasm(p)
1190
1191 return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}
1192 }
1193
1194 func cmp(a int, b int) bool {
1195 if a == b {
1196 return true
1197 }
1198 switch a {
1199 case C_DCON:
1200 return cmp(C_32CON, b) || cmp(C_DCON12_20S, b) || cmp(C_DCON32_12S, b) || b == C_DCON12_0
1201 case C_32CON:
1202 return cmp(C_32CON20_0, b) || cmp(C_U15CON, b) || cmp(C_13CON, b) || cmp(C_12CON, b)
1203 case C_32CON20_0:
1204 return b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_S13CON20_0 || b == C_ZCON
1205 case C_U15CON:
1206 return cmp(C_U12CON, b) || b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_U13CON
1207 case C_13CON:
1208 return cmp(C_U13CON, b) || cmp(C_S13CON, b)
1209 case C_U13CON:
1210 return cmp(C_12CON, b) || b == C_U13CON20_0
1211 case C_S13CON:
1212 return cmp(C_12CON, b) || b == C_S13CON20_0
1213 case C_12CON:
1214 return cmp(C_U12CON, b) || cmp(C_S12CON, b)
1215 case C_UU12CON:
1216 return cmp(C_U12CON, b)
1217 case C_U12CON:
1218 return cmp(C_U8CON, b) || b == C_US12CON
1219 case C_U8CON:
1220 return cmp(C_U7CON, b)
1221 case C_U7CON:
1222 return cmp(C_U6CON, b)
1223 case C_U6CON:
1224 return cmp(C_U5CON, b)
1225 case C_U5CON:
1226 return cmp(C_U4CON, b)
1227 case C_U4CON:
1228 return cmp(C_U3CON, b)
1229 case C_U3CON:
1230 return cmp(C_U2CON, b)
1231 case C_U2CON:
1232 return cmp(C_U1CON, b)
1233 case C_U1CON:
1234 return cmp(C_ZCON, b)
1235 case C_US12CON:
1236 return cmp(C_S12CON, b)
1237 case C_S12CON:
1238 return cmp(C_S5CON, b) || cmp(C_U8CON, b) || b == C_US12CON
1239 case C_S5CON:
1240 return cmp(C_ZCON, b) || cmp(C_U4CON, b)
1241
1242 case C_DCON12_20S:
1243 if b == C_DCON20S_20 || b == C_DCON12_12S ||
1244 b == C_DCON20S_12S || b == C_DCON12_12U ||
1245 b == C_DCON20S_12U || b == C_DCON20S_0 {
1246 return true
1247 }
1248
1249 case C_DCON32_12S:
1250 if b == C_DCON32_20 || b == C_DCON12_32S ||
1251 b == C_DCON20S_32 || b == C_DCON32_12U ||
1252 b == C_DCON32_0 {
1253 return true
1254 }
1255
1256 case C_LACON:
1257 return b == C_SACON
1258
1259 case C_LAUTO:
1260 return b == C_SAUTO
1261
1262 case C_REG:
1263 return b == C_ZCON
1264
1265 case C_LOREG:
1266 return b == C_ZOREG || b == C_SOREG
1267
1268 case C_SOREG:
1269 return b == C_ZOREG
1270 }
1271
1272 return false
1273 }
1274
1275 func ocmp(p1, p2 Optab) int {
1276 if p1.as != p2.as {
1277 return int(p1.as) - int(p2.as)
1278 }
1279 if p1.from1 != p2.from1 {
1280 return int(p1.from1) - int(p2.from1)
1281 }
1282 if p1.reg != p2.reg {
1283 return int(p1.reg) - int(p2.reg)
1284 }
1285 if p1.to1 != p2.to1 {
1286 return int(p1.to1) - int(p2.to1)
1287 }
1288 return 0
1289 }
1290
1291 func opset(a, b0 obj.As) {
1292 oprange[a&obj.AMask] = oprange[b0]
1293 }
1294
1295 func buildop(ctxt *obj.Link) {
1296 if ctxt.DiagFunc == nil {
1297 ctxt.DiagFunc = func(format string, args ...interface{}) {
1298 log.Printf(format, args...)
1299 }
1300 }
1301
1302 if oprange[AOR&obj.AMask] != nil {
1303
1304
1305
1306 return
1307 }
1308
1309 for i := range C_NCLASS {
1310 for j := range C_NCLASS {
1311 if cmp(j, i) {
1312 xcmp[i][j] = true
1313 }
1314 }
1315 }
1316
1317 slices.SortFunc(optab, ocmp)
1318 for i := 0; i < len(optab); i++ {
1319 as, start := optab[i].as, i
1320 for ; i < len(optab)-1; i++ {
1321 if optab[i+1].as != as {
1322 break
1323 }
1324 }
1325 r0 := as & obj.AMask
1326 oprange[r0] = optab[start : i+1]
1327 switch as {
1328 default:
1329 ctxt.Diag("unknown op in build: %v", as)
1330 ctxt.DiagFlush()
1331 log.Fatalf("bad code")
1332
1333 case AABSF:
1334 opset(AMOVFD, r0)
1335 opset(AMOVDF, r0)
1336 opset(AMOVWF, r0)
1337 opset(AMOVFW, r0)
1338 opset(AMOVWD, r0)
1339 opset(AMOVDW, r0)
1340 opset(ANEGF, r0)
1341 opset(ANEGD, r0)
1342 opset(AABSD, r0)
1343 opset(ATRUNCDW, r0)
1344 opset(ATRUNCFW, r0)
1345 opset(ASQRTF, r0)
1346 opset(ASQRTD, r0)
1347 opset(AFCLASSF, r0)
1348 opset(AFCLASSD, r0)
1349 opset(AFLOGBF, r0)
1350 opset(AFLOGBD, r0)
1351
1352 case AMOVVF:
1353 opset(AMOVVD, r0)
1354 opset(AMOVFV, r0)
1355 opset(AMOVDV, r0)
1356 opset(ATRUNCDV, r0)
1357 opset(ATRUNCFV, r0)
1358 opset(AFFINTFW, r0)
1359 opset(AFFINTFV, r0)
1360 opset(AFFINTDW, r0)
1361 opset(AFFINTDV, r0)
1362 opset(AFTINTWF, r0)
1363 opset(AFTINTWD, r0)
1364 opset(AFTINTVF, r0)
1365 opset(AFTINTVD, r0)
1366 opset(AFTINTRPWF, r0)
1367 opset(AFTINTRPWD, r0)
1368 opset(AFTINTRPVF, r0)
1369 opset(AFTINTRPVD, r0)
1370 opset(AFTINTRMWF, r0)
1371 opset(AFTINTRMWD, r0)
1372 opset(AFTINTRMVF, r0)
1373 opset(AFTINTRMVD, r0)
1374 opset(AFTINTRZWF, r0)
1375 opset(AFTINTRZWD, r0)
1376 opset(AFTINTRZVF, r0)
1377 opset(AFTINTRZVD, r0)
1378 opset(AFTINTRNEWF, r0)
1379 opset(AFTINTRNEWD, r0)
1380 opset(AFTINTRNEVF, r0)
1381 opset(AFTINTRNEVD, r0)
1382
1383 case AADD:
1384 opset(ASGT, r0)
1385 opset(ASGTU, r0)
1386 opset(AADDU, r0)
1387
1388 case AADDV:
1389 opset(AADDVU, r0)
1390
1391 case AADDF:
1392 opset(ADIVF, r0)
1393 opset(ADIVD, r0)
1394 opset(AMULF, r0)
1395 opset(AMULD, r0)
1396 opset(ASUBF, r0)
1397 opset(ASUBD, r0)
1398 opset(AADDD, r0)
1399 opset(AFMINF, r0)
1400 opset(AFMIND, r0)
1401 opset(AFMAXF, r0)
1402 opset(AFMAXD, r0)
1403 opset(AFCOPYSGF, r0)
1404 opset(AFCOPYSGD, r0)
1405 opset(AFSCALEBF, r0)
1406 opset(AFSCALEBD, r0)
1407 opset(AFMAXAF, r0)
1408 opset(AFMAXAD, r0)
1409 opset(AFMINAF, r0)
1410 opset(AFMINAD, r0)
1411
1412 case AFMADDF:
1413 opset(AFMADDD, r0)
1414 opset(AFMSUBF, r0)
1415 opset(AFMSUBD, r0)
1416 opset(AFNMADDF, r0)
1417 opset(AFNMADDD, r0)
1418 opset(AFNMSUBF, r0)
1419 opset(AFNMSUBD, r0)
1420
1421 case AAND:
1422 opset(AOR, r0)
1423 opset(AXOR, r0)
1424 opset(AORN, r0)
1425 opset(AANDN, r0)
1426
1427 case ABEQ:
1428 opset(ABNE, r0)
1429 opset(ABLT, r0)
1430 opset(ABGE, r0)
1431 opset(ABGEU, r0)
1432 opset(ABLTU, r0)
1433
1434 case ABLEZ:
1435 opset(ABGEZ, r0)
1436 opset(ABLTZ, r0)
1437 opset(ABGTZ, r0)
1438
1439 case AMOVB:
1440 opset(AMOVH, r0)
1441
1442 case AMOVBU:
1443 opset(AMOVHU, r0)
1444
1445 case AMOVWP:
1446 opset(AMOVVP, r0)
1447
1448 case AMUL:
1449 opset(AMULU, r0)
1450 opset(AMULH, r0)
1451 opset(AMULHU, r0)
1452 opset(AREM, r0)
1453 opset(AREMU, r0)
1454 opset(ADIV, r0)
1455 opset(ADIVU, r0)
1456
1457 case AMULV:
1458 opset(AMULVU, r0)
1459 opset(AMULHV, r0)
1460 opset(AMULHVU, r0)
1461 opset(AREMV, r0)
1462 opset(AREMVU, r0)
1463 opset(ADIVV, r0)
1464 opset(ADIVVU, r0)
1465
1466 case ASLL:
1467 opset(ASRL, r0)
1468 opset(ASRA, r0)
1469 opset(AROTR, r0)
1470
1471 case ASLLV:
1472 opset(ASRAV, r0)
1473 opset(ASRLV, r0)
1474 opset(AROTRV, r0)
1475
1476 case ABSTRPICKW:
1477 opset(ABSTRPICKV, r0)
1478 opset(ABSTRINSW, r0)
1479 opset(ABSTRINSV, r0)
1480
1481 case ASUB:
1482 opset(ASUBU, r0)
1483 opset(ANOR, r0)
1484
1485 case ASUBV:
1486 opset(ASUBVU, r0)
1487
1488 case ASYSCALL:
1489 opset(ADBAR, r0)
1490 opset(ABREAK, r0)
1491
1492 case ACMPEQF:
1493 opset(ACMPGTF, r0)
1494 opset(ACMPGTD, r0)
1495 opset(ACMPGEF, r0)
1496 opset(ACMPGED, r0)
1497 opset(ACMPEQD, r0)
1498
1499 case ABFPT:
1500 opset(ABFPF, r0)
1501
1502 case AALSLV:
1503 opset(AALSLW, r0)
1504 opset(AALSLWU, r0)
1505
1506 case AMOVW,
1507 AMOVD,
1508 AMOVF,
1509 AMOVV,
1510 ARFE,
1511 AJAL,
1512 AJMP,
1513 AMOVWU,
1514 AVMOVQ,
1515 AXVMOVQ,
1516 ALL,
1517 ALLV,
1518 ASC,
1519 ASCV,
1520 ANEGW,
1521 ANEGV,
1522 AWORD,
1523 APRELD,
1524 APRELDX,
1525 AFSEL,
1526 AADDV16,
1527 obj.ANOP,
1528 obj.ATEXT,
1529 obj.AFUNCDATA,
1530 obj.APCALIGN,
1531 obj.APCDATA:
1532 break
1533
1534 case ARDTIMELW:
1535 opset(ARDTIMEHW, r0)
1536 opset(ARDTIMED, r0)
1537
1538 case ACLOW:
1539 opset(ACLZW, r0)
1540 opset(ACTOW, r0)
1541 opset(ACTZW, r0)
1542 opset(ACLOV, r0)
1543 opset(ACLZV, r0)
1544 opset(ACTOV, r0)
1545 opset(ACTZV, r0)
1546 opset(AREVB2H, r0)
1547 opset(AREVB4H, r0)
1548 opset(AREVB2W, r0)
1549 opset(AREVBV, r0)
1550 opset(AREVH2W, r0)
1551 opset(AREVHV, r0)
1552 opset(ABITREV4B, r0)
1553 opset(ABITREV8B, r0)
1554 opset(ABITREVW, r0)
1555 opset(ABITREVV, r0)
1556 opset(AEXTWB, r0)
1557 opset(AEXTWH, r0)
1558 opset(ACPUCFG, r0)
1559
1560 case ATEQ:
1561 opset(ATNE, r0)
1562
1563 case AMASKEQZ:
1564 opset(AMASKNEZ, r0)
1565 opset(ACRCWBW, r0)
1566 opset(ACRCWHW, r0)
1567 opset(ACRCWWW, r0)
1568 opset(ACRCWVW, r0)
1569 opset(ACRCCWBW, r0)
1570 opset(ACRCCWHW, r0)
1571 opset(ACRCCWWW, r0)
1572 opset(ACRCCWVW, r0)
1573
1574 case ANOOP:
1575 opset(obj.AUNDEF, r0)
1576
1577 case AAMSWAPW:
1578 for i := range atomicInst {
1579 if i == AAMSWAPW {
1580 continue
1581 }
1582 opset(i, r0)
1583 }
1584
1585 case AVSEQB:
1586 opset(AVSEQH, r0)
1587 opset(AVSEQW, r0)
1588 opset(AVSEQV, r0)
1589 opset(AVILVLB, r0)
1590 opset(AVILVLH, r0)
1591 opset(AVILVLW, r0)
1592 opset(AVILVLV, r0)
1593 opset(AVILVHB, r0)
1594 opset(AVILVHH, r0)
1595 opset(AVILVHW, r0)
1596 opset(AVILVHV, r0)
1597 opset(AVMULB, r0)
1598 opset(AVMULH, r0)
1599 opset(AVMULW, r0)
1600 opset(AVMULV, r0)
1601 opset(AVMUHB, r0)
1602 opset(AVMUHH, r0)
1603 opset(AVMUHW, r0)
1604 opset(AVMUHV, r0)
1605 opset(AVMUHBU, r0)
1606 opset(AVMUHHU, r0)
1607 opset(AVMUHWU, r0)
1608 opset(AVMUHVU, r0)
1609 opset(AVDIVB, r0)
1610 opset(AVDIVH, r0)
1611 opset(AVDIVW, r0)
1612 opset(AVDIVV, r0)
1613 opset(AVMODB, r0)
1614 opset(AVMODH, r0)
1615 opset(AVMODW, r0)
1616 opset(AVMODV, r0)
1617 opset(AVDIVBU, r0)
1618 opset(AVDIVHU, r0)
1619 opset(AVDIVWU, r0)
1620 opset(AVDIVVU, r0)
1621 opset(AVMODBU, r0)
1622 opset(AVMODHU, r0)
1623 opset(AVMODWU, r0)
1624 opset(AVMODVU, r0)
1625 opset(AVMULWEVHB, r0)
1626 opset(AVMULWEVWH, r0)
1627 opset(AVMULWEVVW, r0)
1628 opset(AVMULWEVQV, r0)
1629 opset(AVMULWODHB, r0)
1630 opset(AVMULWODWH, r0)
1631 opset(AVMULWODVW, r0)
1632 opset(AVMULWODQV, r0)
1633 opset(AVMULWEVHBU, r0)
1634 opset(AVMULWEVWHU, r0)
1635 opset(AVMULWEVVWU, r0)
1636 opset(AVMULWEVQVU, r0)
1637 opset(AVMULWODHBU, r0)
1638 opset(AVMULWODWHU, r0)
1639 opset(AVMULWODVWU, r0)
1640 opset(AVMULWODQVU, r0)
1641 opset(AVMULWEVHBUB, r0)
1642 opset(AVMULWEVWHUH, r0)
1643 opset(AVMULWEVVWUW, r0)
1644 opset(AVMULWEVQVUV, r0)
1645 opset(AVMULWODHBUB, r0)
1646 opset(AVMULWODWHUH, r0)
1647 opset(AVMULWODVWUW, r0)
1648 opset(AVMULWODQVUV, r0)
1649 opset(AVADDF, r0)
1650 opset(AVADDD, r0)
1651 opset(AVSUBF, r0)
1652 opset(AVSUBD, r0)
1653 opset(AVMULF, r0)
1654 opset(AVMULD, r0)
1655 opset(AVDIVF, r0)
1656 opset(AVDIVD, r0)
1657
1658 case AXVSEQB:
1659 opset(AXVSEQH, r0)
1660 opset(AXVSEQW, r0)
1661 opset(AXVSEQV, r0)
1662 opset(AXVILVLB, r0)
1663 opset(AXVILVLH, r0)
1664 opset(AXVILVLW, r0)
1665 opset(AXVILVLV, r0)
1666 opset(AXVILVHB, r0)
1667 opset(AXVILVHH, r0)
1668 opset(AXVILVHW, r0)
1669 opset(AXVILVHV, r0)
1670 opset(AXVMULB, r0)
1671 opset(AXVMULH, r0)
1672 opset(AXVMULW, r0)
1673 opset(AXVMULV, r0)
1674 opset(AXVMUHB, r0)
1675 opset(AXVMUHH, r0)
1676 opset(AXVMUHW, r0)
1677 opset(AXVMUHV, r0)
1678 opset(AXVMUHBU, r0)
1679 opset(AXVMUHHU, r0)
1680 opset(AXVMUHWU, r0)
1681 opset(AXVMUHVU, r0)
1682 opset(AXVDIVB, r0)
1683 opset(AXVDIVH, r0)
1684 opset(AXVDIVW, r0)
1685 opset(AXVDIVV, r0)
1686 opset(AXVMODB, r0)
1687 opset(AXVMODH, r0)
1688 opset(AXVMODW, r0)
1689 opset(AXVMODV, r0)
1690 opset(AXVDIVBU, r0)
1691 opset(AXVDIVHU, r0)
1692 opset(AXVDIVWU, r0)
1693 opset(AXVDIVVU, r0)
1694 opset(AXVMODBU, r0)
1695 opset(AXVMODHU, r0)
1696 opset(AXVMODWU, r0)
1697 opset(AXVMODVU, r0)
1698 opset(AXVMULWEVHB, r0)
1699 opset(AXVMULWEVWH, r0)
1700 opset(AXVMULWEVVW, r0)
1701 opset(AXVMULWEVQV, r0)
1702 opset(AXVMULWODHB, r0)
1703 opset(AXVMULWODWH, r0)
1704 opset(AXVMULWODVW, r0)
1705 opset(AXVMULWODQV, r0)
1706 opset(AXVMULWEVHBU, r0)
1707 opset(AXVMULWEVWHU, r0)
1708 opset(AXVMULWEVVWU, r0)
1709 opset(AXVMULWEVQVU, r0)
1710 opset(AXVMULWODHBU, r0)
1711 opset(AXVMULWODWHU, r0)
1712 opset(AXVMULWODVWU, r0)
1713 opset(AXVMULWODQVU, r0)
1714 opset(AXVMULWEVHBUB, r0)
1715 opset(AXVMULWEVWHUH, r0)
1716 opset(AXVMULWEVVWUW, r0)
1717 opset(AXVMULWEVQVUV, r0)
1718 opset(AXVMULWODHBUB, r0)
1719 opset(AXVMULWODWHUH, r0)
1720 opset(AXVMULWODVWUW, r0)
1721 opset(AXVMULWODQVUV, r0)
1722 opset(AXVADDF, r0)
1723 opset(AXVADDD, r0)
1724 opset(AXVSUBF, r0)
1725 opset(AXVSUBD, r0)
1726 opset(AXVMULF, r0)
1727 opset(AXVMULD, r0)
1728 opset(AXVDIVF, r0)
1729 opset(AXVDIVD, r0)
1730
1731 case AVANDB:
1732 opset(AVORB, r0)
1733 opset(AVXORB, r0)
1734 opset(AVNORB, r0)
1735 opset(AVSHUF4IB, r0)
1736 opset(AVSHUF4IH, r0)
1737 opset(AVSHUF4IW, r0)
1738 opset(AVSHUF4IV, r0)
1739
1740 case AXVANDB:
1741 opset(AXVORB, r0)
1742 opset(AXVXORB, r0)
1743 opset(AXVNORB, r0)
1744 opset(AXVSHUF4IB, r0)
1745 opset(AXVSHUF4IH, r0)
1746 opset(AXVSHUF4IW, r0)
1747 opset(AXVSHUF4IV, r0)
1748
1749 case AVANDV:
1750 opset(AVORV, r0)
1751 opset(AVXORV, r0)
1752 opset(AVNORV, r0)
1753 opset(AVANDNV, r0)
1754 opset(AVORNV, r0)
1755
1756 case AXVANDV:
1757 opset(AXVORV, r0)
1758 opset(AXVXORV, r0)
1759 opset(AXVNORV, r0)
1760 opset(AXVANDNV, r0)
1761 opset(AXVORNV, r0)
1762
1763 case AVPCNTB:
1764 opset(AVPCNTH, r0)
1765 opset(AVPCNTW, r0)
1766 opset(AVPCNTV, r0)
1767 opset(AVFSQRTF, r0)
1768 opset(AVFSQRTD, r0)
1769 opset(AVFRECIPF, r0)
1770 opset(AVFRECIPD, r0)
1771 opset(AVFRSQRTF, r0)
1772 opset(AVFRSQRTD, r0)
1773 opset(AVNEGB, r0)
1774 opset(AVNEGH, r0)
1775 opset(AVNEGW, r0)
1776 opset(AVNEGV, r0)
1777 opset(AVFRINTRNEF, r0)
1778 opset(AVFRINTRNED, r0)
1779 opset(AVFRINTRZF, r0)
1780 opset(AVFRINTRZD, r0)
1781 opset(AVFRINTRPF, r0)
1782 opset(AVFRINTRPD, r0)
1783 opset(AVFRINTRMF, r0)
1784 opset(AVFRINTRMD, r0)
1785 opset(AVFRINTF, r0)
1786 opset(AVFRINTD, r0)
1787 opset(AVFCLASSF, r0)
1788 opset(AVFCLASSD, r0)
1789
1790 case AXVPCNTB:
1791 opset(AXVPCNTH, r0)
1792 opset(AXVPCNTW, r0)
1793 opset(AXVPCNTV, r0)
1794 opset(AXVFSQRTF, r0)
1795 opset(AXVFSQRTD, r0)
1796 opset(AXVFRECIPF, r0)
1797 opset(AXVFRECIPD, r0)
1798 opset(AXVFRSQRTF, r0)
1799 opset(AXVFRSQRTD, r0)
1800 opset(AXVNEGB, r0)
1801 opset(AXVNEGH, r0)
1802 opset(AXVNEGW, r0)
1803 opset(AXVNEGV, r0)
1804 opset(AXVFRINTRNEF, r0)
1805 opset(AXVFRINTRNED, r0)
1806 opset(AXVFRINTRZF, r0)
1807 opset(AXVFRINTRZD, r0)
1808 opset(AXVFRINTRPF, r0)
1809 opset(AXVFRINTRPD, r0)
1810 opset(AXVFRINTRMF, r0)
1811 opset(AXVFRINTRMD, r0)
1812 opset(AXVFRINTF, r0)
1813 opset(AXVFRINTD, r0)
1814 opset(AXVFCLASSF, r0)
1815 opset(AXVFCLASSD, r0)
1816
1817 case AVADDB:
1818 opset(AVADDH, r0)
1819 opset(AVADDW, r0)
1820 opset(AVADDV, r0)
1821 opset(AVADDQ, r0)
1822 opset(AVSUBB, r0)
1823 opset(AVSUBH, r0)
1824 opset(AVSUBW, r0)
1825 opset(AVSUBV, r0)
1826 opset(AVSUBQ, r0)
1827
1828 case AXVADDB:
1829 opset(AXVADDH, r0)
1830 opset(AXVADDW, r0)
1831 opset(AXVADDV, r0)
1832 opset(AXVADDQ, r0)
1833 opset(AXVSUBB, r0)
1834 opset(AXVSUBH, r0)
1835 opset(AXVSUBW, r0)
1836 opset(AXVSUBV, r0)
1837 opset(AXVSUBQ, r0)
1838
1839 case AVSLLB:
1840 opset(AVSRLB, r0)
1841 opset(AVSRAB, r0)
1842 opset(AVROTRB, r0)
1843 opset(AVBITCLRB, r0)
1844 opset(AVBITSETB, r0)
1845 opset(AVBITREVB, r0)
1846
1847 case AXVSLLB:
1848 opset(AXVSRLB, r0)
1849 opset(AXVSRAB, r0)
1850 opset(AXVROTRB, r0)
1851 opset(AXVBITCLRB, r0)
1852 opset(AXVBITSETB, r0)
1853 opset(AXVBITREVB, r0)
1854
1855 case AVSLLH:
1856 opset(AVSRLH, r0)
1857 opset(AVSRAH, r0)
1858 opset(AVROTRH, r0)
1859 opset(AVBITCLRH, r0)
1860 opset(AVBITSETH, r0)
1861 opset(AVBITREVH, r0)
1862
1863 case AXVSLLH:
1864 opset(AXVSRLH, r0)
1865 opset(AXVSRAH, r0)
1866 opset(AXVROTRH, r0)
1867 opset(AXVBITCLRH, r0)
1868 opset(AXVBITSETH, r0)
1869 opset(AXVBITREVH, r0)
1870
1871 case AVSLLW:
1872 opset(AVSRLW, r0)
1873 opset(AVSRAW, r0)
1874 opset(AVROTRW, r0)
1875 opset(AVADDBU, r0)
1876 opset(AVADDHU, r0)
1877 opset(AVADDWU, r0)
1878 opset(AVADDVU, r0)
1879 opset(AVSUBBU, r0)
1880 opset(AVSUBHU, r0)
1881 opset(AVSUBWU, r0)
1882 opset(AVSUBVU, r0)
1883 opset(AVBITCLRW, r0)
1884 opset(AVBITSETW, r0)
1885 opset(AVBITREVW, r0)
1886
1887 case AXVSLLW:
1888 opset(AXVSRLW, r0)
1889 opset(AXVSRAW, r0)
1890 opset(AXVROTRW, r0)
1891 opset(AXVADDBU, r0)
1892 opset(AXVADDHU, r0)
1893 opset(AXVADDWU, r0)
1894 opset(AXVADDVU, r0)
1895 opset(AXVSUBBU, r0)
1896 opset(AXVSUBHU, r0)
1897 opset(AXVSUBWU, r0)
1898 opset(AXVSUBVU, r0)
1899 opset(AXVBITCLRW, r0)
1900 opset(AXVBITSETW, r0)
1901 opset(AXVBITREVW, r0)
1902
1903 case AVSLLV:
1904 opset(AVSRLV, r0)
1905 opset(AVSRAV, r0)
1906 opset(AVROTRV, r0)
1907 opset(AVBITCLRV, r0)
1908 opset(AVBITSETV, r0)
1909 opset(AVBITREVV, r0)
1910
1911 case AXVSLLV:
1912 opset(AXVSRLV, r0)
1913 opset(AXVSRAV, r0)
1914 opset(AXVROTRV, r0)
1915 opset(AXVBITCLRV, r0)
1916 opset(AXVBITSETV, r0)
1917 opset(AXVBITREVV, r0)
1918
1919 case AVSETEQV:
1920 opset(AVSETNEV, r0)
1921 opset(AVSETANYEQB, r0)
1922 opset(AVSETANYEQH, r0)
1923 opset(AVSETANYEQW, r0)
1924 opset(AVSETANYEQV, r0)
1925 opset(AVSETALLNEB, r0)
1926 opset(AVSETALLNEH, r0)
1927 opset(AVSETALLNEW, r0)
1928 opset(AVSETALLNEV, r0)
1929
1930 case AXVSETEQV:
1931 opset(AXVSETNEV, r0)
1932 opset(AXVSETANYEQB, r0)
1933 opset(AXVSETANYEQH, r0)
1934 opset(AXVSETANYEQW, r0)
1935 opset(AXVSETANYEQV, r0)
1936 opset(AXVSETALLNEB, r0)
1937 opset(AXVSETALLNEH, r0)
1938 opset(AXVSETALLNEW, r0)
1939 opset(AXVSETALLNEV, r0)
1940
1941 }
1942 }
1943 }
1944
1945 func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
1946 return op | (r1&0x1F)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4 & 0x1F)
1947 }
1948
1949
1950
1951
1952 func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32 {
1953 return op | (r1&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1954 }
1955
1956
1957
1958 func OP_RR(op uint32, r2 uint32, r3 uint32) uint32 {
1959 return op | (r2&0x1F)<<5 | (r3&0x1F)<<0
1960 }
1961
1962 func OP_2IRRR(op uint32, i uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
1963 return op | (i&0x3)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4&0x1F)<<0
1964 }
1965
1966 func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32 {
1967 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | ((i >> 16) & 0x1F)
1968 }
1969
1970 func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1971 return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1972 }
1973
1974 func OP_14IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1975 return op | (i&0x3FFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1976 }
1977
1978 func OP_12IR_5I(op uint32, i1 uint32, r2 uint32, i2 uint32) uint32 {
1979 return op | (i1&0xFFF)<<10 | (r2&0x1F)<<5 | (i2&0x1F)<<0
1980 }
1981
1982 func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1983 return op | (i&0xFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1984 }
1985
1986 func OP_11IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1987 return op | (i&0x7FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1988 }
1989
1990 func OP_10IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1991 return op | (i&0x3FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1992 }
1993
1994 func OP_9IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1995 return op | (i&0x1FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
1996 }
1997
1998 func OP_8IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
1999 return op | (i&0xFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2000 }
2001
2002 func OP_6IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2003 return op | (i&0x3F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2004 }
2005
2006 func OP_5IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2007 return op | (i&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2008 }
2009
2010 func OP_4IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2011 return op | (i&0xF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2012 }
2013
2014 func OP_3IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
2015 return op | (i&0x7)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
2016 }
2017
2018 func OP_IR(op uint32, i uint32, r2 uint32) uint32 {
2019 return op | (i&0xFFFFF)<<5 | (r2&0x1F)<<0
2020 }
2021
2022 func OP_15I(op uint32, i uint32) uint32 {
2023 return op | (i&0x7FFF)<<0
2024 }
2025
2026
2027
2028
2029
2030 func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32 {
2031 return op | (i1 << 16) | (r2&0x1F)<<5 | (i3 << 10) | (r4&0x1F)<<0
2032 }
2033
2034
2035 func OP_B_BL(op uint32, i uint32) uint32 {
2036 return op | ((i & 0xFFFF) << 10) | ((i >> 16) & 0x3FF)
2037 }
2038
2039 func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
2040 o1 := uint32(0)
2041 o2 := uint32(0)
2042 o3 := uint32(0)
2043 o4 := uint32(0)
2044 o5 := uint32(0)
2045
2046 add := AADDU
2047 add = AADDVU
2048
2049 switch o.type_ {
2050 default:
2051 c.ctxt.Diag("unknown type %d %v", o.type_)
2052 prasm(p)
2053
2054 case 0:
2055 break
2056
2057 case 1:
2058 a := AOR
2059 if p.As == AMOVW {
2060 a = ASLL
2061 }
2062 o1 = OP_RRR(c.oprrr(a), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
2063
2064 case 2:
2065 r := int(p.Reg)
2066 if p.As == ANEGW || p.As == ANEGV {
2067 r = REGZERO
2068 }
2069 if r == 0 {
2070 r = int(p.To.Reg)
2071 }
2072 o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
2073
2074 case 3:
2075 v := c.regoff(&p.From)
2076
2077 r := int(p.From.Reg)
2078 if r == 0 {
2079 r = int(o.param)
2080 }
2081 a := add
2082 if o.from1 == C_12CON && v > 0 {
2083 a = AOR
2084 }
2085
2086 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.To.Reg))
2087
2088 case 4:
2089 v := c.regoff(&p.From)
2090 r := int(p.Reg)
2091 if r == 0 {
2092 r = int(p.To.Reg)
2093 }
2094 if p.As == AADDV16 {
2095 if v&65535 != 0 {
2096 c.ctxt.Diag("%v: the constant must be a multiple of 65536.\n", p)
2097 }
2098 o1 = OP_16IRR(c.opirr(p.As), uint32(v>>16), uint32(r), uint32(p.To.Reg))
2099 } else {
2100 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2101 }
2102
2103 case 5:
2104 v := c.regoff(&p.From)
2105 o1 = OP_15I(c.opi(p.As), uint32(v))
2106
2107 case 6:
2108 v := int32(0)
2109 if p.To.Target() != nil {
2110 v = int32(p.To.Target().Pc-p.Pc) >> 2
2111 }
2112 as, rd, rj, width := p.As, p.Reg, p.From.Reg, 16
2113 switch as {
2114 case ABGTZ, ABLEZ:
2115 rd, rj = rj, rd
2116 case ABFPT, ABFPF:
2117 width = 21
2118
2119
2120 if rj == 0 {
2121 rj = REG_FCC0
2122 }
2123 case ABEQ, ABNE:
2124 if rd == 0 || rd == REGZERO || rj == REGZERO {
2125
2126 width = 21
2127 as = -as
2128 if rj == 0 || rj == REGZERO {
2129 rj = rd
2130 }
2131 }
2132 }
2133 switch width {
2134 case 21:
2135 if (v<<11)>>11 != v {
2136 c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
2137 }
2138 o1 = OP_16IR_5I(c.opirr(as), uint32(v), uint32(rj))
2139 case 16:
2140 if (v<<16)>>16 != v {
2141 c.ctxt.Diag("16 bit-width, short branch too far\n%v", p)
2142 }
2143 o1 = OP_16IRR(c.opirr(as), uint32(v), uint32(rj), uint32(rd))
2144 default:
2145 c.ctxt.Diag("unexpected branch encoding\n%v", p)
2146 }
2147
2148 case 7:
2149 r := int(p.To.Reg)
2150 if r == 0 {
2151 r = int(o.param)
2152 }
2153 v := c.regoff(&p.To)
2154 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2155
2156 case 8:
2157 r := int(p.From.Reg)
2158 if r == 0 {
2159 r = int(o.param)
2160 }
2161 v := c.regoff(&p.From)
2162 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2163
2164 case 9:
2165 o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
2166
2167 case 10:
2168 v := c.regoff(&p.From)
2169 a := AOR
2170 if v < 0 {
2171 a = AADDU
2172 }
2173 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2174 r := int(p.Reg)
2175 if r == 0 {
2176 r = int(p.To.Reg)
2177 }
2178 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2179
2180 case 11:
2181 v := int32(0)
2182 if p.To.Target() != nil {
2183 v = int32(p.To.Target().Pc-p.Pc) >> 2
2184 }
2185 o1 = OP_B_BL(c.opirr(p.As), uint32(v))
2186 if p.To.Sym != nil {
2187 c.cursym.AddRel(c.ctxt, obj.Reloc{
2188 Type: objabi.R_CALLLOONG64,
2189 Off: int32(c.pc),
2190 Siz: 4,
2191 Sym: p.To.Sym,
2192 Add: p.To.Offset,
2193 })
2194 }
2195
2196 case 12:
2197 switch p.As {
2198 case AMOVB:
2199 o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg))
2200 case AMOVH:
2201 o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg))
2202 case AMOVBU:
2203 o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg))
2204 case AMOVHU:
2205 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2206 case AMOVWU:
2207 o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg))
2208 default:
2209 c.ctxt.Diag("unexpected encoding\n%v", p)
2210 }
2211
2212 case 13:
2213 v := c.regoff(&p.From)
2214 r := int(p.Reg)
2215 if r == 0 {
2216 r = int(p.To.Reg)
2217 }
2218 o1 = OP_3IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2219
2220 case 14:
2221 v := c.regoff(&p.From)
2222 r := int(p.Reg)
2223 if r == 0 {
2224 r = int(p.To.Reg)
2225 }
2226 o1 = OP_4IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2227
2228 case 15:
2229 v := c.regoff(&p.From)
2230 r := int(p.Reg)
2231 if r == 0 {
2232 r = REGZERO
2233 }
2234
2242 if p.As == ATEQ {
2243 o1 = OP_16IRR(c.opirr(ABNE), uint32(2), uint32(r), uint32(p.To.Reg))
2244 } else {
2245 o1 = OP_16IRR(c.opirr(ABEQ), uint32(2), uint32(r), uint32(p.To.Reg))
2246 }
2247 o2 = OP_15I(c.opi(ABREAK), uint32(v))
2248
2249 case 16:
2250 v := c.regoff(&p.From)
2251 r := int(p.Reg)
2252 if r == 0 {
2253 r = int(p.To.Reg)
2254 }
2255
2256
2257 if v >= 32 && vshift(p.As) {
2258 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x3f, uint32(r), uint32(p.To.Reg))
2259 } else {
2260 o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x1f, uint32(r), uint32(p.To.Reg))
2261 }
2262
2263 case 17:
2264 rd, rj := p.To.Reg, p.Reg
2265 if rj == obj.REG_NONE {
2266 rj = rd
2267 }
2268 msb, lsb := p.From.Offset, p.GetFrom3().Offset
2269
2270
2271 var b uint32
2272 if p.As == ABSTRPICKW || p.As == ABSTRINSW {
2273 b = 32
2274 } else {
2275 b = 64
2276 }
2277 if lsb < 0 || uint32(lsb) >= b || msb < 0 || uint32(msb) >= b || uint32(lsb) > uint32(msb) {
2278 c.ctxt.Diag("illegal bit number\n%v", p)
2279 }
2280
2281 o1 = OP_IRIR(c.opirir(p.As), uint32(msb), uint32(rj), uint32(lsb), uint32(rd))
2282
2283 case 18:
2284 r := int(p.Reg)
2285 if r == 0 {
2286 r = int(o.param)
2287 }
2288 o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.To.Reg), uint32(r))
2289 if p.As == obj.ACALL {
2290 c.cursym.AddRel(c.ctxt, obj.Reloc{
2291 Type: objabi.R_CALLIND,
2292 Off: int32(c.pc),
2293 })
2294 }
2295
2296 case 19:
2297
2298
2299 v := c.regoff(&p.From)
2300 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2301 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2302
2303 case 20:
2304 o1 = OP_RRR(c.oprrr(p.As), uint32(p.To.Index), uint32(p.To.Reg), uint32(p.From.Reg))
2305
2306 case 21:
2307 o1 = OP_RRR(c.oprrr(-p.As), uint32(p.From.Index), uint32(p.From.Reg), uint32(p.To.Reg))
2308
2309 case 22:
2310 v := c.regoff(&p.From)
2311 r := int(p.Reg)
2312 if r == 0 {
2313 r = int(p.To.Reg)
2314 }
2315
2316 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2317
2318 case 23:
2319 v := c.regoff(&p.From)
2320 r := int(p.Reg)
2321 if r == 0 {
2322 r = int(p.To.Reg)
2323 }
2324
2325
2326 if p.As == AVSHUF4IV || p.As == AXVSHUF4IV {
2327 operand := uint32(v)
2328 c.checkoperand(p, operand, 15)
2329 }
2330
2331 o1 = OP_8IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2332
2333 case 24:
2334 v := c.regoff(&p.From)
2335 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2336 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2337 r := int(p.Reg)
2338 if r == 0 {
2339 r = int(p.To.Reg)
2340 }
2341 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2342
2343 case 25:
2344 v := c.regoff(&p.From)
2345 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2346
2347 case 26:
2348 v := c.regoff(&p.From)
2349 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2350 r := int(p.Reg)
2351 if r == 0 {
2352 r = int(p.To.Reg)
2353 }
2354 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2355
2356 case 27:
2357 v := c.regoff(&p.From)
2358 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2359 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2360 r := int(p.From.Reg)
2361 if r == 0 {
2362 r = int(o.param)
2363 }
2364 o3 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2365
2366 case 28:
2367 v := c.regoff(&p.From)
2368 r := int(p.From.Reg)
2369 if r == 0 {
2370 r = int(o.param)
2371 }
2372 switch o.size {
2373 case 12:
2374 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2375 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2376 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2377
2378 case 4:
2379 o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2380 }
2381
2382 case 29:
2383 v := c.regoff(&p.To)
2384 r := int(p.To.Reg)
2385 if r == 0 {
2386 r = int(o.param)
2387 }
2388 switch o.size {
2389 case 12:
2390 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2391 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2392 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2393
2394 case 4:
2395 o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
2396 }
2397
2398 case 30:
2399 a := c.specialFpMovInst(p.As, oclass(&p.From), oclass(&p.To))
2400 o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
2401
2402 case 31:
2403 v := c.regoff(&p.From)
2404 r := int(p.Reg)
2405 if r == 0 {
2406 r = int(p.To.Reg)
2407 }
2408 o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2409
2410 case 32:
2411 v := c.regoff(&p.From)
2412 r := int(p.Reg)
2413 if r == 0 {
2414 r = int(p.To.Reg)
2415 }
2416 o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
2417
2418 case 33:
2419 ca := uint32(p.From.Reg)
2420 fk := uint32(p.Reg)
2421 fd := uint32(p.To.Reg)
2422 fj := fd
2423 if len(p.RestArgs) > 0 {
2424 fj = uint32(p.GetFrom3().Reg)
2425 }
2426 o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F)
2427
2428 case 34:
2429 v := c.regoff(&p.From)
2430 a := AADDU
2431 if v > 0 {
2432 a = AOR
2433 }
2434 a2 := c.specialFpMovInst(p.As, C_REG, oclass(&p.To))
2435 o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
2436 o2 = OP_RR(a2, uint32(REGTMP), uint32(p.To.Reg))
2437
2438 case 35:
2439 v := c.regoff(&p.To)
2440 r := int(p.To.Reg)
2441 if r == 0 {
2442 r = int(o.param)
2443 }
2444 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2445 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2446 o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
2447
2448 case 36:
2449 v := c.regoff(&p.From)
2450 r := int(p.From.Reg)
2451 if r == 0 {
2452 r = int(o.param)
2453 }
2454 o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
2455 o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
2456 o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
2457
2458 case 37:
2459 r := int(p.To.Reg)
2460 if len(p.RestArgs) > 0 {
2461 r = int(p.GetFrom3().Reg)
2462 }
2463 o1 = OP_RRRR(c.oprrrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(r), uint32(p.To.Reg))
2464
2465 case 38:
2466 o1 = uint32(c.regoff(&p.From))
2467
2468 case 39:
2469 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2470 if v == 0 {
2471 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2472 }
2473
2474 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2475 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2476 index := uint32(p.To.Index)
2477 c.checkindex(p, index, m)
2478 o1 = v | (index << 10) | (Rj << 5) | Vd
2479
2480 case 40:
2481 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2482 if v == 0 {
2483 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2484 }
2485
2486 Vj := uint32(p.From.Reg & EXT_REG_MASK)
2487 Rd := uint32(p.To.Reg & EXT_REG_MASK)
2488 index := uint32(p.From.Index)
2489 c.checkindex(p, index, m)
2490 o1 = v | (index << 10) | (Vj << 5) | Rd
2491
2492 case 41:
2493 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2494 if v == 0 {
2495 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2496 }
2497
2498 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2499 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2500 o1 = v | (Rj << 5) | Vd
2501
2502 case 42:
2503 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2504 if v == 0 {
2505 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2506 }
2507
2508 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2509 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2510 o1 = v | (Xj << 5) | Xd
2511
2512 case 43:
2513 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2514 if v == 0 {
2515 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2516 }
2517
2518 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2519 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2520 index := uint32(p.To.Index)
2521 c.checkindex(p, index, m)
2522 o1 = v | (index << 10) | (Xj << 5) | Xd
2523
2524 case 44:
2525 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2526 if v == 0 {
2527 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2528 }
2529
2530 Xj := uint32(p.From.Reg & EXT_REG_MASK)
2531 Xd := uint32(p.To.Reg & EXT_REG_MASK)
2532 index := uint32(p.From.Index)
2533 c.checkindex(p, index, m)
2534 o1 = v | (index << 10) | (Xj << 5) | Xd
2535
2536 case 45:
2537 v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
2538 if v == 0 {
2539 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2540 }
2541
2542 vj := uint32(p.From.Reg & EXT_REG_MASK)
2543 vd := uint32(p.To.Reg & EXT_REG_MASK)
2544 index := uint32(p.From.Index)
2545 c.checkindex(p, index, m)
2546 o1 = v | (index << 10) | (vj << 5) | vd
2547
2548 case 46:
2549 v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, true)
2550 if v == 0 {
2551 c.ctxt.Diag("illegal arng type combination: %v\n", p)
2552 }
2553
2554 si := c.regoff(&p.From)
2555 Rj := uint32(p.From.Reg & EXT_REG_MASK)
2556 Vd := uint32(p.To.Reg & EXT_REG_MASK)
2557 switch v & 0xc00000 {
2558 case 0x800000:
2559 o1 = OP_12IRR(v, uint32(si), Rj, Vd)
2560 case 0x400000:
2561 if si&1 != 0 {
2562 c.ctxt.Diag("%v: offset must be a multiple of 2.\n", p)
2563 }
2564 o1 = OP_11IRR(v, uint32(si>>1), Rj, Vd)
2565 case 0x0:
2566 switch v & 0x300000 {
2567 case 0x200000:
2568 if si&3 != 0 {
2569 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
2570 }
2571 o1 = OP_10IRR(v, uint32(si>>2), Rj, Vd)
2572 case 0x100000:
2573 if si&7 != 0 {
2574 c.ctxt.Diag("%v: offset must be a multiple of 8.\n", p)
2575 }
2576 o1 = OP_9IRR(v, uint32(si>>3), Rj, Vd)
2577 }
2578 }
2579
2580 case 47:
2581 offs := c.regoff(&p.From)
2582 hint := p.GetFrom3().Offset
2583 o1 = OP_12IR_5I(c.opiir(p.As), uint32(offs), uint32(p.From.Reg), uint32(hint))
2584
2585 case 48:
2586 offs := c.regoff(&p.From)
2587 hint := p.RestArgs[1].Offset
2588 n := uint64(p.GetFrom3().Offset)
2589
2590 addrSeq := (n >> 0) & 0x1
2591 blkSize := (n >> 1) & 0x7ff
2592 blkNums := (n >> 12) & 0x1ff
2593 stride := (n >> 21) & 0xffff
2594
2595 if blkSize > 1024 {
2596 c.ctxt.Diag("%v: block_size amount out of range[16, 1024]: %v\n", p, blkSize)
2597 }
2598
2599 if blkNums > 256 {
2600 c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkSize)
2601 }
2602
2603 v := (uint64(offs) & 0xffff)
2604 v += addrSeq << 16
2605 v += ((blkSize / 16) - 1) << 20
2606 v += (blkNums - 1) << 32
2607 v += stride << 44
2608
2609 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2610 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2611 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2612 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2613 o5 = OP_5IRR(c.opirr(p.As), uint32(REGTMP), uint32(p.From.Reg), uint32(hint))
2614
2615 case 49:
2616 if p.As == ANOOP {
2617
2618 o1 = OP_12IRR(c.opirr(AAND), 0, 0, 0)
2619 } else {
2620
2621 o1 = OP_15I(c.opi(ABREAK), 0)
2622 }
2623
2624
2625 case 50:
2626 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2627 c.cursym.AddRel(c.ctxt, obj.Reloc{
2628 Type: objabi.R_LOONG64_ADDR_HI,
2629 Off: int32(c.pc),
2630 Siz: 4,
2631 Sym: p.To.Sym,
2632 Add: p.To.Offset,
2633 })
2634 o2 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2635 c.cursym.AddRel(c.ctxt, obj.Reloc{
2636 Type: objabi.R_LOONG64_ADDR_LO,
2637 Off: int32(c.pc + 4),
2638 Siz: 4,
2639 Sym: p.To.Sym,
2640 Add: p.To.Offset,
2641 })
2642
2643 case 51:
2644 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2645 c.cursym.AddRel(c.ctxt, obj.Reloc{
2646 Type: objabi.R_LOONG64_ADDR_HI,
2647 Off: int32(c.pc),
2648 Siz: 4,
2649 Sym: p.From.Sym,
2650 Add: p.From.Offset,
2651 })
2652 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2653 c.cursym.AddRel(c.ctxt, obj.Reloc{
2654 Type: objabi.R_LOONG64_ADDR_LO,
2655 Off: int32(c.pc + 4),
2656 Siz: 4,
2657 Sym: p.From.Sym,
2658 Add: p.From.Offset,
2659 })
2660
2661 case 52:
2662
2663
2664 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2665 c.cursym.AddRel(c.ctxt, obj.Reloc{
2666 Type: objabi.R_LOONG64_ADDR_HI,
2667 Off: int32(c.pc),
2668 Siz: 4,
2669 Sym: p.From.Sym,
2670 Add: p.From.Offset,
2671 })
2672 o2 = OP_12IRR(c.opirr(add), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2673 c.cursym.AddRel(c.ctxt, obj.Reloc{
2674 Type: objabi.R_LOONG64_ADDR_LO,
2675 Off: int32(c.pc + 4),
2676 Siz: 4,
2677 Sym: p.From.Sym,
2678 Add: p.From.Offset,
2679 })
2680
2681 case 53:
2682
2683
2684 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2685 c.cursym.AddRel(c.ctxt, obj.Reloc{
2686 Type: objabi.R_LOONG64_TLS_LE_HI,
2687 Off: int32(c.pc),
2688 Siz: 4,
2689 Sym: p.To.Sym,
2690 Add: p.To.Offset,
2691 })
2692 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2693 c.cursym.AddRel(c.ctxt, obj.Reloc{
2694 Type: objabi.R_LOONG64_TLS_LE_LO,
2695 Off: int32(c.pc + 4),
2696 Siz: 4,
2697 Sym: p.To.Sym,
2698 Add: p.To.Offset,
2699 })
2700 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2701 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2702
2703 case 54:
2704
2705
2706 o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
2707 c.cursym.AddRel(c.ctxt, obj.Reloc{
2708 Type: objabi.R_LOONG64_TLS_LE_HI,
2709 Off: int32(c.pc),
2710 Siz: 4,
2711 Sym: p.From.Sym,
2712 Add: p.From.Offset,
2713 })
2714 o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
2715 c.cursym.AddRel(c.ctxt, obj.Reloc{
2716 Type: objabi.R_LOONG64_TLS_LE_LO,
2717 Off: int32(c.pc + 4),
2718 Siz: 4,
2719 Sym: p.From.Sym,
2720 Add: p.From.Offset,
2721 })
2722 o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
2723 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2724
2725 case 56:
2726 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2727 c.cursym.AddRel(c.ctxt, obj.Reloc{
2728 Type: objabi.R_LOONG64_TLS_IE_HI,
2729 Off: int32(c.pc),
2730 Siz: 4,
2731 Sym: p.To.Sym,
2732 })
2733 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2734 c.cursym.AddRel(c.ctxt, obj.Reloc{
2735 Type: objabi.R_LOONG64_TLS_IE_LO,
2736 Off: int32(c.pc + 4),
2737 Siz: 4,
2738 Sym: p.To.Sym,
2739 })
2740 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
2741 o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
2742
2743 case 57:
2744 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
2745 c.cursym.AddRel(c.ctxt, obj.Reloc{
2746 Type: objabi.R_LOONG64_TLS_IE_HI,
2747 Off: int32(c.pc),
2748 Siz: 4,
2749 Sym: p.From.Sym,
2750 })
2751 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
2752 c.cursym.AddRel(c.ctxt, obj.Reloc{
2753 Type: objabi.R_LOONG64_TLS_IE_LO,
2754 Off: int32(c.pc + 4),
2755 Siz: 4,
2756 Sym: p.From.Sym,
2757 })
2758 o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
2759 o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
2760
2761 case 59:
2762
2763
2764 v := c.vregoff(&p.From)
2765 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2766 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2767 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2768 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2769
2770 case 60:
2771 v := c.vregoff(&p.From)
2772 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2773 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2774 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2775 o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2776 r := int(p.Reg)
2777 if r == 0 {
2778 r = int(p.To.Reg)
2779 }
2780 o5 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2781
2782 case 61:
2783 o1 = uint32(c.vregoff(&p.From))
2784 o2 = uint32(c.vregoff(&p.From) >> 32)
2785
2786 case 62:
2787 o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
2788
2789 case 64:
2790 sa := p.From.Offset - 1
2791 if sa < 0 || sa > 3 {
2792 c.ctxt.Diag("%v: shift amount out of range[1, 4].\n", p)
2793 }
2794 r := p.GetFrom3().Reg
2795 o1 = OP_2IRRR(c.opirrr(p.As), uint32(sa), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
2796
2797 case 65:
2798 o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
2799 c.cursym.AddRel(c.ctxt, obj.Reloc{
2800 Type: objabi.R_LOONG64_GOT_HI,
2801 Off: int32(c.pc),
2802 Siz: 4,
2803 Sym: p.From.Sym,
2804 })
2805 o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
2806 c.cursym.AddRel(c.ctxt, obj.Reloc{
2807 Type: objabi.R_LOONG64_GOT_LO,
2808 Off: int32(c.pc + 4),
2809 Siz: 4,
2810 Sym: p.From.Sym,
2811 })
2812
2813 case 66:
2814 rk := p.From.Reg
2815 rj := p.To.Reg
2816 rd := p.RegTo2
2817
2818
2819
2820 if rd == rj || rd == rk {
2821 c.ctxt.Diag("illegal register combination: %v\n", p)
2822 }
2823 o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
2824
2825 case 67:
2826 v := c.vregoff(&p.From)
2827 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(p.To.Reg))
2828
2829 case 68:
2830 v := c.vregoff(&p.From)
2831 contype := c.aclass(&p.From)
2832 switch contype {
2833 default:
2834 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2835 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2836 case C_DCON20S_20:
2837 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2838 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2839 case C_DCON12_12S:
2840 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(p.To.Reg))
2841 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2842 case C_DCON20S_12S, C_DCON20S_0:
2843 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
2844 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2845 case C_DCON12_12U:
2846 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2847 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2848 case C_DCON20S_12U:
2849 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2850 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2851 }
2852
2853 case 69:
2854 v := c.vregoff(&p.From)
2855 contype := c.aclass(&p.From)
2856 switch contype {
2857 default:
2858 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
2859 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2860 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2861 case C_DCON32_20:
2862 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2863 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2864 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2865 case C_DCON12_32S:
2866 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2867 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2868 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2869 case C_DCON20S_32:
2870 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
2871 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
2872 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2873 case C_DCON32_12U:
2874 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
2875 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
2876 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
2877 }
2878
2879 case 70:
2880 v := c.vregoff(&p.From)
2881 r := int(p.Reg)
2882 if r == 0 {
2883 r = int(p.To.Reg)
2884 }
2885 o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(REGTMP))
2886 o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2887
2888 case 71:
2889 v := c.vregoff(&p.From)
2890 r := int(p.Reg)
2891 if r == 0 {
2892 r = int(p.To.Reg)
2893 }
2894 contype := c.aclass(&p.From)
2895 switch contype {
2896 default:
2897 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2898 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2899 case C_DCON20S_20:
2900 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2901 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2902 case C_DCON12_12S:
2903 o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(REGTMP))
2904 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2905 case C_DCON20S_12S, C_DCON20S_0:
2906 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
2907 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2908 case C_DCON12_12U:
2909 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
2910 o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2911 case C_DCON20S_12U:
2912 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
2913 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2914 }
2915 o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2916
2917 case 72:
2918 v := c.vregoff(&p.From)
2919 r := int(p.Reg)
2920 if r == 0 {
2921 r = int(p.To.Reg)
2922 }
2923 contype := c.aclass(&p.From)
2924 switch contype {
2925 default:
2926 o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
2927 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2928 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2929 case C_DCON32_20:
2930 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2931 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2932 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2933 case C_DCON12_32S:
2934 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2935 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2936 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2937 case C_DCON20S_32:
2938 o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
2939 o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
2940 o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2941 case C_DCON32_12U:
2942 o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
2943 o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
2944 o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
2945 }
2946 o4 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
2947
2948 case 73:
2949 v := c.regoff(&p.To)
2950 if v&3 != 0 {
2951 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
2952 }
2953 o1 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(p.To.Reg), uint32(p.From.Reg))
2954
2955 case 74:
2956 v := c.regoff(&p.From)
2957 if v&3 != 0 {
2958 c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
2959 }
2960 o1 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(p.From.Reg), uint32(p.To.Reg))
2961 }
2962
2963 out[0] = o1
2964 out[1] = o2
2965 out[2] = o3
2966 out[3] = o4
2967 out[4] = o5
2968 }
2969
2970
2971 func (c *ctxt0) checkoperand(p *obj.Prog, operand uint32, mask uint32) {
2972 if (operand & ^mask) != 0 {
2973 c.ctxt.Diag("operand out of range 0 to %d: %v", mask, p)
2974 }
2975 }
2976
2977
2978 func (c *ctxt0) checkindex(p *obj.Prog, index uint32, mask uint32) {
2979 if (index & ^mask) != 0 {
2980 c.ctxt.Diag("register element index out of range 0 to %d: %v", mask, p)
2981 }
2982 }
2983
2984 func (c *ctxt0) vregoff(a *obj.Addr) int64 {
2985 c.instoffset = 0
2986 c.aclass(a)
2987 return c.instoffset
2988 }
2989
2990 func (c *ctxt0) regoff(a *obj.Addr) int32 {
2991 return int32(c.vregoff(a))
2992 }
2993
2994 func (c *ctxt0) oprrrr(a obj.As) uint32 {
2995 switch a {
2996 case AFMADDF:
2997 return 0x81 << 20
2998 case AFMADDD:
2999 return 0x82 << 20
3000 case AFMSUBF:
3001 return 0x85 << 20
3002 case AFMSUBD:
3003 return 0x86 << 20
3004 case AFNMADDF:
3005 return 0x89 << 20
3006 case AFNMADDD:
3007 return 0x8a << 20
3008 case AFNMSUBF:
3009 return 0x8d << 20
3010 case AFNMSUBD:
3011 return 0x8e << 20
3012 }
3013
3014 c.ctxt.Diag("bad rrrr opcode %v", a)
3015 return 0
3016 }
3017
3018 func (c *ctxt0) oprrr(a obj.As) uint32 {
3019 switch a {
3020 case AADD:
3021 return 0x20 << 15
3022 case AADDU:
3023 return 0x20 << 15
3024 case ASGT:
3025 return 0x24 << 15
3026 case ASGTU:
3027 return 0x25 << 15
3028 case AMASKEQZ:
3029 return 0x26 << 15
3030 case AMASKNEZ:
3031 return 0x27 << 15
3032 case AAND:
3033 return 0x29 << 15
3034 case AOR:
3035 return 0x2a << 15
3036 case AXOR:
3037 return 0x2b << 15
3038 case AORN:
3039 return 0x2c << 15
3040 case AANDN:
3041 return 0x2d << 15
3042 case ASUB:
3043 return 0x22 << 15
3044 case ASUBU, ANEGW:
3045 return 0x22 << 15
3046 case ANOR:
3047 return 0x28 << 15
3048 case ASLL:
3049 return 0x2e << 15
3050 case ASRL:
3051 return 0x2f << 15
3052 case ASRA:
3053 return 0x30 << 15
3054 case AROTR:
3055 return 0x36 << 15
3056 case ASLLV:
3057 return 0x31 << 15
3058 case ASRLV:
3059 return 0x32 << 15
3060 case ASRAV:
3061 return 0x33 << 15
3062 case AROTRV:
3063 return 0x37 << 15
3064 case AADDV:
3065 return 0x21 << 15
3066 case AADDVU:
3067 return 0x21 << 15
3068 case ASUBV:
3069 return 0x23 << 15
3070 case ASUBVU, ANEGV:
3071 return 0x23 << 15
3072
3073 case AMUL:
3074 return 0x38 << 15
3075 case AMULU:
3076 return 0x38 << 15
3077 case AMULH:
3078 return 0x39 << 15
3079 case AMULHU:
3080 return 0x3a << 15
3081 case AMULV:
3082 return 0x3b << 15
3083 case AMULVU:
3084 return 0x3b << 15
3085 case AMULHV:
3086 return 0x3c << 15
3087 case AMULHVU:
3088 return 0x3d << 15
3089 case ADIV:
3090 return 0x40 << 15
3091 case ADIVU:
3092 return 0x42 << 15
3093 case ADIVV:
3094 return 0x44 << 15
3095 case ADIVVU:
3096 return 0x46 << 15
3097 case AREM:
3098 return 0x41 << 15
3099 case AREMU:
3100 return 0x43 << 15
3101 case AREMV:
3102 return 0x45 << 15
3103 case AREMVU:
3104 return 0x47 << 15
3105 case ACRCWBW:
3106 return 0x48 << 15
3107 case ACRCWHW:
3108 return 0x49 << 15
3109 case ACRCWWW:
3110 return 0x4a << 15
3111 case ACRCWVW:
3112 return 0x4b << 15
3113 case ACRCCWBW:
3114 return 0x4c << 15
3115 case ACRCCWHW:
3116 return 0x4d << 15
3117 case ACRCCWWW:
3118 return 0x4e << 15
3119 case ACRCCWVW:
3120 return 0x4f << 15
3121 case AJMP:
3122 return 0x13 << 26
3123 case AJAL:
3124 return (0x13 << 26) | 1
3125
3126 case ADIVF:
3127 return 0x20d << 15
3128 case ADIVD:
3129 return 0x20e << 15
3130 case AMULF:
3131 return 0x209 << 15
3132 case AMULD:
3133 return 0x20a << 15
3134 case ASUBF:
3135 return 0x205 << 15
3136 case ASUBD:
3137 return 0x206 << 15
3138 case AADDF:
3139 return 0x201 << 15
3140 case AADDD:
3141 return 0x202 << 15
3142 case ACMPEQF:
3143 return 0x0c1<<20 | 0x4<<15
3144 case ACMPEQD:
3145 return 0x0c2<<20 | 0x4<<15
3146 case ACMPGED:
3147 return 0x0c2<<20 | 0x7<<15
3148 case ACMPGEF:
3149 return 0x0c1<<20 | 0x7<<15
3150 case ACMPGTD:
3151 return 0x0c2<<20 | 0x3<<15
3152 case ACMPGTF:
3153 return 0x0c1<<20 | 0x3<<15
3154 case AFMINF:
3155 return 0x215 << 15
3156 case AFMIND:
3157 return 0x216 << 15
3158 case AFMAXF:
3159 return 0x211 << 15
3160 case AFMAXD:
3161 return 0x212 << 15
3162 case AFMAXAF:
3163 return 0x219 << 15
3164 case AFMAXAD:
3165 return 0x21a << 15
3166 case AFMINAF:
3167 return 0x21d << 15
3168 case AFMINAD:
3169 return 0x21e << 15
3170 case AFSCALEBF:
3171 return 0x221 << 15
3172 case AFSCALEBD:
3173 return 0x222 << 15
3174 case AFCOPYSGF:
3175 return 0x225 << 15
3176 case AFCOPYSGD:
3177 return 0x226 << 15
3178 case -AMOVB:
3179 return 0x07000 << 15
3180 case -AMOVH:
3181 return 0x07008 << 15
3182 case -AMOVW:
3183 return 0x07010 << 15
3184 case -AMOVV:
3185 return 0x07018 << 15
3186 case -AMOVBU:
3187 return 0x07040 << 15
3188 case -AMOVHU:
3189 return 0x07048 << 15
3190 case -AMOVWU:
3191 return 0x07050 << 15
3192 case AMOVB:
3193 return 0x07020 << 15
3194 case AMOVH:
3195 return 0x07028 << 15
3196 case AMOVW:
3197 return 0x07030 << 15
3198 case AMOVV:
3199 return 0x07038 << 15
3200 case -AMOVF:
3201 return 0x07060 << 15
3202 case -AMOVD:
3203 return 0x07068 << 15
3204 case AMOVF:
3205 return 0x07070 << 15
3206 case AMOVD:
3207 return 0x07078 << 15
3208 case -AVMOVQ:
3209 return 0x07080 << 15
3210 case -AXVMOVQ:
3211 return 0x07090 << 15
3212 case AVMOVQ:
3213 return 0x07088 << 15
3214 case AXVMOVQ:
3215 return 0x07098 << 15
3216 case AVSEQB:
3217 return 0x0e000 << 15
3218 case AXVSEQB:
3219 return 0x0e800 << 15
3220 case AVSEQH:
3221 return 0x0e001 << 15
3222 case AXVSEQH:
3223 return 0x0e801 << 15
3224 case AVSEQW:
3225 return 0x0e002 << 15
3226 case AXVSEQW:
3227 return 0x0e802 << 15
3228 case AVSEQV:
3229 return 0x0e003 << 15
3230 case AXVSEQV:
3231 return 0x0e803 << 15
3232 case AVANDV:
3233 return 0x0E24C << 15
3234 case AVORV:
3235 return 0x0E24D << 15
3236 case AVXORV:
3237 return 0x0E24E << 15
3238 case AVNORV:
3239 return 0x0E24F << 15
3240 case AVANDNV:
3241 return 0x0E250 << 15
3242 case AVORNV:
3243 return 0x0E251 << 15
3244 case AXVANDV:
3245 return 0x0EA4C << 15
3246 case AXVORV:
3247 return 0x0EA4D << 15
3248 case AXVXORV:
3249 return 0x0EA4E << 15
3250 case AXVNORV:
3251 return 0x0EA4F << 15
3252 case AXVANDNV:
3253 return 0x0EA50 << 15
3254 case AXVORNV:
3255 return 0x0EA51 << 15
3256 case AVDIVB:
3257 return 0xe1c0 << 15
3258 case AVDIVH:
3259 return 0xe1c1 << 15
3260 case AVDIVW:
3261 return 0xe1c2 << 15
3262 case AVDIVV:
3263 return 0xe1c3 << 15
3264 case AVMODB:
3265 return 0xe1c4 << 15
3266 case AVMODH:
3267 return 0xe1c5 << 15
3268 case AVMODW:
3269 return 0xe1c6 << 15
3270 case AVMODV:
3271 return 0xe1c7 << 15
3272 case AVDIVBU:
3273 return 0xe1c8 << 15
3274 case AVDIVHU:
3275 return 0xe1c9 << 15
3276 case AVDIVWU:
3277 return 0xe1ca << 15
3278 case AVDIVVU:
3279 return 0xe1cb << 15
3280 case AVMODBU:
3281 return 0xe1cc << 15
3282 case AVMODHU:
3283 return 0xe1cd << 15
3284 case AVMODWU:
3285 return 0xe1ce << 15
3286 case AVMODVU:
3287 return 0xe1cf << 15
3288 case AXVDIVB:
3289 return 0xe9c0 << 15
3290 case AXVDIVH:
3291 return 0xe9c1 << 15
3292 case AXVDIVW:
3293 return 0xe9c2 << 15
3294 case AXVDIVV:
3295 return 0xe9c3 << 15
3296 case AXVMODB:
3297 return 0xe9c4 << 15
3298 case AXVMODH:
3299 return 0xe9c5 << 15
3300 case AXVMODW:
3301 return 0xe9c6 << 15
3302 case AXVMODV:
3303 return 0xe9c7 << 15
3304 case AXVDIVBU:
3305 return 0xe9c8 << 15
3306 case AXVDIVHU:
3307 return 0xe9c9 << 15
3308 case AXVDIVWU:
3309 return 0xe9ca << 15
3310 case AXVDIVVU:
3311 return 0xe9cb << 15
3312 case AXVMODBU:
3313 return 0xe9cc << 15
3314 case AXVMODHU:
3315 return 0xe9cd << 15
3316 case AXVMODWU:
3317 return 0xe9ce << 15
3318 case AXVMODVU:
3319 return 0xe9cf << 15
3320 case AVMULWEVHB:
3321 return 0xe120 << 15
3322 case AVMULWEVWH:
3323 return 0xe121 << 15
3324 case AVMULWEVVW:
3325 return 0xe122 << 15
3326 case AVMULWEVQV:
3327 return 0xe123 << 15
3328 case AVMULWODHB:
3329 return 0xe124 << 15
3330 case AVMULWODWH:
3331 return 0xe125 << 15
3332 case AVMULWODVW:
3333 return 0xe126 << 15
3334 case AVMULWODQV:
3335 return 0xe127 << 15
3336 case AVMULWEVHBU:
3337 return 0xe130 << 15
3338 case AVMULWEVWHU:
3339 return 0xe131 << 15
3340 case AVMULWEVVWU:
3341 return 0xe132 << 15
3342 case AVMULWEVQVU:
3343 return 0xe133 << 15
3344 case AVMULWODHBU:
3345 return 0xe134 << 15
3346 case AVMULWODWHU:
3347 return 0xe135 << 15
3348 case AVMULWODVWU:
3349 return 0xe136 << 15
3350 case AVMULWODQVU:
3351 return 0xe137 << 15
3352 case AVMULWEVHBUB:
3353 return 0xe140 << 15
3354 case AVMULWEVWHUH:
3355 return 0xe141 << 15
3356 case AVMULWEVVWUW:
3357 return 0xe142 << 15
3358 case AVMULWEVQVUV:
3359 return 0xe143 << 15
3360 case AVMULWODHBUB:
3361 return 0xe144 << 15
3362 case AVMULWODWHUH:
3363 return 0xe145 << 15
3364 case AVMULWODVWUW:
3365 return 0xe146 << 15
3366 case AVMULWODQVUV:
3367 return 0xe147 << 15
3368 case AXVMULWEVHB:
3369 return 0xe920 << 15
3370 case AXVMULWEVWH:
3371 return 0xe921 << 15
3372 case AXVMULWEVVW:
3373 return 0xe922 << 15
3374 case AXVMULWEVQV:
3375 return 0xe923 << 15
3376 case AXVMULWODHB:
3377 return 0xe924 << 15
3378 case AXVMULWODWH:
3379 return 0xe925 << 15
3380 case AXVMULWODVW:
3381 return 0xe926 << 15
3382 case AXVMULWODQV:
3383 return 0xe927 << 15
3384 case AXVMULWEVHBU:
3385 return 0xe930 << 15
3386 case AXVMULWEVWHU:
3387 return 0xe931 << 15
3388 case AXVMULWEVVWU:
3389 return 0xe932 << 15
3390 case AXVMULWEVQVU:
3391 return 0xe933 << 15
3392 case AXVMULWODHBU:
3393 return 0xe934 << 15
3394 case AXVMULWODWHU:
3395 return 0xe935 << 15
3396 case AXVMULWODVWU:
3397 return 0xe936 << 15
3398 case AXVMULWODQVU:
3399 return 0xe937 << 15
3400 case AXVMULWEVHBUB:
3401 return 0xe940 << 15
3402 case AXVMULWEVWHUH:
3403 return 0xe941 << 15
3404 case AXVMULWEVVWUW:
3405 return 0xe942 << 15
3406 case AXVMULWEVQVUV:
3407 return 0xe943 << 15
3408 case AXVMULWODHBUB:
3409 return 0xe944 << 15
3410 case AXVMULWODWHUH:
3411 return 0xe945 << 15
3412 case AXVMULWODVWUW:
3413 return 0xe946 << 15
3414 case AXVMULWODQVUV:
3415 return 0xe947 << 15
3416 case AVSLLB:
3417 return 0xe1d0 << 15
3418 case AVSLLH:
3419 return 0xe1d1 << 15
3420 case AVSLLW:
3421 return 0xe1d2 << 15
3422 case AVSLLV:
3423 return 0xe1d3 << 15
3424 case AVSRLB:
3425 return 0xe1d4 << 15
3426 case AVSRLH:
3427 return 0xe1d5 << 15
3428 case AVSRLW:
3429 return 0xe1d6 << 15
3430 case AVSRLV:
3431 return 0xe1d7 << 15
3432 case AVSRAB:
3433 return 0xe1d8 << 15
3434 case AVSRAH:
3435 return 0xe1d9 << 15
3436 case AVSRAW:
3437 return 0xe1da << 15
3438 case AVSRAV:
3439 return 0xe1db << 15
3440 case AVROTRB:
3441 return 0xe1dc << 15
3442 case AVROTRH:
3443 return 0xe1dd << 15
3444 case AVROTRW:
3445 return 0xe1de << 15
3446 case AVROTRV:
3447 return 0xe1df << 15
3448 case AXVSLLB:
3449 return 0xe9d0 << 15
3450 case AXVSLLH:
3451 return 0xe9d1 << 15
3452 case AXVSLLW:
3453 return 0xe9d2 << 15
3454 case AXVSLLV:
3455 return 0xe9d3 << 15
3456 case AXVSRLB:
3457 return 0xe9d4 << 15
3458 case AXVSRLH:
3459 return 0xe9d5 << 15
3460 case AXVSRLW:
3461 return 0xe9d6 << 15
3462 case AXVSRLV:
3463 return 0xe9d7 << 15
3464 case AXVSRAB:
3465 return 0xe9d8 << 15
3466 case AXVSRAH:
3467 return 0xe9d9 << 15
3468 case AXVSRAW:
3469 return 0xe9da << 15
3470 case AXVSRAV:
3471 return 0xe9db << 15
3472 case AXVROTRB:
3473 return 0xe9dc << 15
3474 case AXVROTRH:
3475 return 0xe9dd << 15
3476 case AXVROTRW:
3477 return 0xe9de << 15
3478 case AXVROTRV:
3479 return 0xe9df << 15
3480 case AVADDB:
3481 return 0xe014 << 15
3482 case AVADDH:
3483 return 0xe015 << 15
3484 case AVADDW:
3485 return 0xe016 << 15
3486 case AVADDV:
3487 return 0xe017 << 15
3488 case AVADDQ:
3489 return 0xe25a << 15
3490 case AVSUBB:
3491 return 0xe018 << 15
3492 case AVSUBH:
3493 return 0xe019 << 15
3494 case AVSUBW:
3495 return 0xe01a << 15
3496 case AVSUBV:
3497 return 0xe01b << 15
3498 case AVSUBQ:
3499 return 0xe25b << 15
3500 case AXVADDB:
3501 return 0xe814 << 15
3502 case AXVADDH:
3503 return 0xe815 << 15
3504 case AXVADDW:
3505 return 0xe816 << 15
3506 case AXVADDV:
3507 return 0xe817 << 15
3508 case AXVADDQ:
3509 return 0xea5a << 15
3510 case AXVSUBB:
3511 return 0xe818 << 15
3512 case AXVSUBH:
3513 return 0xe819 << 15
3514 case AXVSUBW:
3515 return 0xe81a << 15
3516 case AXVSUBV:
3517 return 0xe81b << 15
3518 case AXVSUBQ:
3519 return 0xea5b << 15
3520 case AVILVLB:
3521 return 0xe234 << 15
3522 case AVILVLH:
3523 return 0xe235 << 15
3524 case AVILVLW:
3525 return 0xe236 << 15
3526 case AVILVLV:
3527 return 0xe237 << 15
3528 case AVILVHB:
3529 return 0xe238 << 15
3530 case AVILVHH:
3531 return 0xe239 << 15
3532 case AVILVHW:
3533 return 0xe23a << 15
3534 case AVILVHV:
3535 return 0xe23b << 15
3536 case AXVILVLB:
3537 return 0xea34 << 15
3538 case AXVILVLH:
3539 return 0xea35 << 15
3540 case AXVILVLW:
3541 return 0xea36 << 15
3542 case AXVILVLV:
3543 return 0xea37 << 15
3544 case AXVILVHB:
3545 return 0xea38 << 15
3546 case AXVILVHH:
3547 return 0xea39 << 15
3548 case AXVILVHW:
3549 return 0xea3a << 15
3550 case AXVILVHV:
3551 return 0xea3b << 15
3552 case AVMULB:
3553 return 0xe108 << 15
3554 case AVMULH:
3555 return 0xe109 << 15
3556 case AVMULW:
3557 return 0xe10a << 15
3558 case AVMULV:
3559 return 0xe10b << 15
3560 case AVMUHB:
3561 return 0xe10c << 15
3562 case AVMUHH:
3563 return 0xe10d << 15
3564 case AVMUHW:
3565 return 0xe10e << 15
3566 case AVMUHV:
3567 return 0xe10f << 15
3568 case AVMUHBU:
3569 return 0xe110 << 15
3570 case AVMUHHU:
3571 return 0xe111 << 15
3572 case AVMUHWU:
3573 return 0xe112 << 15
3574 case AVMUHVU:
3575 return 0xe113 << 15
3576 case AXVMULB:
3577 return 0xe908 << 15
3578 case AXVMULH:
3579 return 0xe909 << 15
3580 case AXVMULW:
3581 return 0xe90a << 15
3582 case AXVMULV:
3583 return 0xe90b << 15
3584 case AXVMUHB:
3585 return 0xe90c << 15
3586 case AXVMUHH:
3587 return 0xe90d << 15
3588 case AXVMUHW:
3589 return 0xe90e << 15
3590 case AXVMUHV:
3591 return 0xe90f << 15
3592 case AXVMUHBU:
3593 return 0xe910 << 15
3594 case AXVMUHHU:
3595 return 0xe911 << 15
3596 case AXVMUHWU:
3597 return 0xe912 << 15
3598 case AXVMUHVU:
3599 return 0xe913 << 15
3600 case AVADDF:
3601 return 0xe261 << 15
3602 case AVADDD:
3603 return 0xe262 << 15
3604 case AVSUBF:
3605 return 0xe265 << 15
3606 case AVSUBD:
3607 return 0xe266 << 15
3608 case AVMULF:
3609 return 0xe271 << 15
3610 case AVMULD:
3611 return 0xe272 << 15
3612 case AVDIVF:
3613 return 0xe275 << 15
3614 case AVDIVD:
3615 return 0xe276 << 15
3616 case AXVADDF:
3617 return 0xea61 << 15
3618 case AXVADDD:
3619 return 0xea62 << 15
3620 case AXVSUBF:
3621 return 0xea65 << 15
3622 case AXVSUBD:
3623 return 0xea66 << 15
3624 case AXVMULF:
3625 return 0xea71 << 15
3626 case AXVMULD:
3627 return 0xea72 << 15
3628 case AXVDIVF:
3629 return 0xea75 << 15
3630 case AXVDIVD:
3631 return 0xea76 << 15
3632 case AVBITCLRB:
3633 return 0xe218 << 15
3634 case AVBITCLRH:
3635 return 0xe219 << 15
3636 case AVBITCLRW:
3637 return 0xe21a << 15
3638 case AVBITCLRV:
3639 return 0xe21b << 15
3640 case AVBITSETB:
3641 return 0xe21c << 15
3642 case AVBITSETH:
3643 return 0xe21d << 15
3644 case AVBITSETW:
3645 return 0xe21e << 15
3646 case AVBITSETV:
3647 return 0xe21f << 15
3648 case AVBITREVB:
3649 return 0xe220 << 15
3650 case AVBITREVH:
3651 return 0xe221 << 15
3652 case AVBITREVW:
3653 return 0xe222 << 15
3654 case AVBITREVV:
3655 return 0xe223 << 15
3656 case AXVBITCLRB:
3657 return 0xea18 << 15
3658 case AXVBITCLRH:
3659 return 0xea19 << 15
3660 case AXVBITCLRW:
3661 return 0xea1a << 15
3662 case AXVBITCLRV:
3663 return 0xea1b << 15
3664 case AXVBITSETB:
3665 return 0xea1c << 15
3666 case AXVBITSETH:
3667 return 0xea1d << 15
3668 case AXVBITSETW:
3669 return 0xea1e << 15
3670 case AXVBITSETV:
3671 return 0xea1f << 15
3672 case AXVBITREVB:
3673 return 0xea20 << 15
3674 case AXVBITREVH:
3675 return 0xea21 << 15
3676 case AXVBITREVW:
3677 return 0xea22 << 15
3678 case AXVBITREVV:
3679 return 0xea23 << 15
3680 }
3681
3682 if a < 0 {
3683 c.ctxt.Diag("bad rrr opcode -%v", -a)
3684 } else {
3685 c.ctxt.Diag("bad rrr opcode %v", a)
3686 }
3687 return 0
3688 }
3689
3690 func (c *ctxt0) oprr(a obj.As) uint32 {
3691 switch a {
3692 case ACLOW:
3693 return 0x4 << 10
3694 case ACLZW:
3695 return 0x5 << 10
3696 case ACTOW:
3697 return 0x6 << 10
3698 case ACTZW:
3699 return 0x7 << 10
3700 case ACLOV:
3701 return 0x8 << 10
3702 case ACLZV:
3703 return 0x9 << 10
3704 case ACTOV:
3705 return 0xa << 10
3706 case ACTZV:
3707 return 0xb << 10
3708 case AREVB2H:
3709 return 0xc << 10
3710 case AREVB4H:
3711 return 0xd << 10
3712 case AREVB2W:
3713 return 0xe << 10
3714 case AREVBV:
3715 return 0xf << 10
3716 case AREVH2W:
3717 return 0x10 << 10
3718 case AREVHV:
3719 return 0x11 << 10
3720 case ABITREV4B:
3721 return 0x12 << 10
3722 case ABITREV8B:
3723 return 0x13 << 10
3724 case ABITREVW:
3725 return 0x14 << 10
3726 case ABITREVV:
3727 return 0x15 << 10
3728 case AEXTWH:
3729 return 0x16 << 10
3730 case AEXTWB:
3731 return 0x17 << 10
3732 case ACPUCFG:
3733 return 0x1b << 10
3734 case ARDTIMELW:
3735 return 0x18 << 10
3736 case ARDTIMEHW:
3737 return 0x19 << 10
3738 case ARDTIMED:
3739 return 0x1a << 10
3740 case ATRUNCFV:
3741 return 0x46a9 << 10
3742 case ATRUNCDV:
3743 return 0x46aa << 10
3744 case ATRUNCFW:
3745 return 0x46a1 << 10
3746 case ATRUNCDW:
3747 return 0x46a2 << 10
3748 case AMOVFV:
3749 return 0x46c9 << 10
3750 case AMOVDV:
3751 return 0x46ca << 10
3752 case AMOVVF:
3753 return 0x4746 << 10
3754 case AMOVVD:
3755 return 0x474a << 10
3756 case AMOVFW:
3757 return 0x46c1 << 10
3758 case AMOVDW:
3759 return 0x46c2 << 10
3760 case AMOVWF:
3761 return 0x4744 << 10
3762 case AMOVDF:
3763 return 0x4646 << 10
3764 case AMOVWD:
3765 return 0x4748 << 10
3766 case AMOVFD:
3767 return 0x4649 << 10
3768 case AABSF:
3769 return 0x4501 << 10
3770 case AABSD:
3771 return 0x4502 << 10
3772 case AMOVF:
3773 return 0x4525 << 10
3774 case AMOVD:
3775 return 0x4526 << 10
3776 case ANEGF:
3777 return 0x4505 << 10
3778 case ANEGD:
3779 return 0x4506 << 10
3780 case ASQRTF:
3781 return 0x4511 << 10
3782 case ASQRTD:
3783 return 0x4512 << 10
3784 case AFLOGBF:
3785 return 0x4509 << 10
3786 case AFLOGBD:
3787 return 0x450a << 10
3788 case AFCLASSF:
3789 return 0x450d << 10
3790 case AFCLASSD:
3791 return 0x450e << 10
3792 case AFFINTFW:
3793 return 0x4744 << 10
3794 case AFFINTFV:
3795 return 0x4746 << 10
3796 case AFFINTDW:
3797 return 0x4748 << 10
3798 case AFFINTDV:
3799 return 0x474a << 10
3800 case AFTINTWF:
3801 return 0x46c1 << 10
3802 case AFTINTWD:
3803 return 0x46c2 << 10
3804 case AFTINTVF:
3805 return 0x46c9 << 10
3806 case AFTINTVD:
3807 return 0x46ca << 10
3808 case AFTINTRMWF:
3809 return 0x4681 << 10
3810 case AFTINTRMWD:
3811 return 0x4682 << 10
3812 case AFTINTRMVF:
3813 return 0x4689 << 10
3814 case AFTINTRMVD:
3815 return 0x468a << 10
3816 case AFTINTRPWF:
3817 return 0x4691 << 10
3818 case AFTINTRPWD:
3819 return 0x4692 << 10
3820 case AFTINTRPVF:
3821 return 0x4699 << 10
3822 case AFTINTRPVD:
3823 return 0x469a << 10
3824 case AFTINTRZWF:
3825 return 0x46a1 << 10
3826 case AFTINTRZWD:
3827 return 0x46a2 << 10
3828 case AFTINTRZVF:
3829 return 0x46a9 << 10
3830 case AFTINTRZVD:
3831 return 0x46aa << 10
3832 case AFTINTRNEWF:
3833 return 0x46b1 << 10
3834 case AFTINTRNEWD:
3835 return 0x46b2 << 10
3836 case AFTINTRNEVF:
3837 return 0x46b9 << 10
3838 case AFTINTRNEVD:
3839 return 0x46ba << 10
3840 case AVPCNTB:
3841 return 0x1ca708 << 10
3842 case AVPCNTH:
3843 return 0x1ca709 << 10
3844 case AVPCNTW:
3845 return 0x1ca70a << 10
3846 case AVPCNTV:
3847 return 0x1ca70b << 10
3848 case AXVPCNTB:
3849 return 0x1da708 << 10
3850 case AXVPCNTH:
3851 return 0x1da709 << 10
3852 case AXVPCNTW:
3853 return 0x1da70a << 10
3854 case AXVPCNTV:
3855 return 0x1da70b << 10
3856 case AVFSQRTF:
3857 return 0x1ca739 << 10
3858 case AVFSQRTD:
3859 return 0x1ca73a << 10
3860 case AVFRECIPF:
3861 return 0x1ca73d << 10
3862 case AVFRECIPD:
3863 return 0x1ca73e << 10
3864 case AVFRSQRTF:
3865 return 0x1ca741 << 10
3866 case AVFRSQRTD:
3867 return 0x1ca742 << 10
3868 case AXVFSQRTF:
3869 return 0x1da739 << 10
3870 case AXVFSQRTD:
3871 return 0x1da73a << 10
3872 case AXVFRECIPF:
3873 return 0x1da73d << 10
3874 case AXVFRECIPD:
3875 return 0x1da73e << 10
3876 case AXVFRSQRTF:
3877 return 0x1da741 << 10
3878 case AXVFRSQRTD:
3879 return 0x1da742 << 10
3880 case AVNEGB:
3881 return 0x1ca70c << 10
3882 case AVNEGH:
3883 return 0x1ca70d << 10
3884 case AVNEGW:
3885 return 0x1ca70e << 10
3886 case AVNEGV:
3887 return 0x1ca70f << 10
3888 case AXVNEGB:
3889 return 0x1da70c << 10
3890 case AXVNEGH:
3891 return 0x1da70d << 10
3892 case AXVNEGW:
3893 return 0x1da70e << 10
3894 case AXVNEGV:
3895 return 0x1da70f << 10
3896 case AVFRINTRNEF:
3897 return 0x1ca75d << 10
3898 case AVFRINTRNED:
3899 return 0x1ca75e << 10
3900 case AVFRINTRZF:
3901 return 0x1ca759 << 10
3902 case AVFRINTRZD:
3903 return 0x1ca75a << 10
3904 case AVFRINTRPF:
3905 return 0x1ca755 << 10
3906 case AVFRINTRPD:
3907 return 0x1ca756 << 10
3908 case AVFRINTRMF:
3909 return 0x1ca751 << 10
3910 case AVFRINTRMD:
3911 return 0x1ca752 << 10
3912 case AVFRINTF:
3913 return 0x1ca74d << 10
3914 case AVFRINTD:
3915 return 0x1ca74e << 10
3916 case AXVFRINTRNEF:
3917 return 0x1da75d << 10
3918 case AXVFRINTRNED:
3919 return 0x1da75e << 10
3920 case AXVFRINTRZF:
3921 return 0x1da759 << 10
3922 case AXVFRINTRZD:
3923 return 0x1da75a << 10
3924 case AXVFRINTRPF:
3925 return 0x1da755 << 10
3926 case AXVFRINTRPD:
3927 return 0x1da756 << 10
3928 case AXVFRINTRMF:
3929 return 0x1da751 << 10
3930 case AXVFRINTRMD:
3931 return 0x1da752 << 10
3932 case AXVFRINTF:
3933 return 0x1da74d << 10
3934 case AXVFRINTD:
3935 return 0x1da74e << 10
3936 case AVFCLASSF:
3937 return 0x1ca735 << 10
3938 case AVFCLASSD:
3939 return 0x1ca736 << 10
3940 case AXVFCLASSF:
3941 return 0x1da735 << 10
3942 case AXVFCLASSD:
3943 return 0x1da736 << 10
3944 case AVSETEQV:
3945 return 0x1ca726<<10 | 0x0<<3
3946 case AVSETNEV:
3947 return 0x1ca727<<10 | 0x0<<3
3948 case AVSETANYEQB:
3949 return 0x1ca728<<10 | 0x0<<3
3950 case AVSETANYEQH:
3951 return 0x1ca729<<10 | 0x0<<3
3952 case AVSETANYEQW:
3953 return 0x1ca72a<<10 | 0x0<<3
3954 case AVSETANYEQV:
3955 return 0x1ca72b<<10 | 0x0<<3
3956 case AVSETALLNEB:
3957 return 0x1ca72c<<10 | 0x0<<3
3958 case AVSETALLNEH:
3959 return 0x1ca72d<<10 | 0x0<<3
3960 case AVSETALLNEW:
3961 return 0x1ca72e<<10 | 0x0<<3
3962 case AVSETALLNEV:
3963 return 0x1ca72f<<10 | 0x0<<3
3964 case AXVSETEQV:
3965 return 0x1da726<<10 | 0x0<<3
3966 case AXVSETNEV:
3967 return 0x1da727<<10 | 0x0<<3
3968 case AXVSETANYEQB:
3969 return 0x1da728<<10 | 0x0<<3
3970 case AXVSETANYEQH:
3971 return 0x1da729<<10 | 0x0<<3
3972 case AXVSETANYEQW:
3973 return 0x1da72a<<10 | 0x0<<3
3974 case AXVSETANYEQV:
3975 return 0x1da72b<<10 | 0x0<<3
3976 case AXVSETALLNEB:
3977 return 0x1da72c<<10 | 0x0<<3
3978 case AXVSETALLNEH:
3979 return 0x1da72d<<10 | 0x0<<3
3980 case AXVSETALLNEW:
3981 return 0x1da72e<<10 | 0x0<<3
3982 case AXVSETALLNEV:
3983 return 0x1da72f<<10 | 0x0<<3
3984 }
3985
3986 c.ctxt.Diag("bad rr opcode %v", a)
3987 return 0
3988 }
3989
3990 func (c *ctxt0) opi(a obj.As) uint32 {
3991 switch a {
3992 case ASYSCALL:
3993 return 0x56 << 15
3994 case ABREAK:
3995 return 0x54 << 15
3996 case ADBAR:
3997 return 0x70e4 << 15
3998 }
3999
4000 c.ctxt.Diag("bad ic opcode %v", a)
4001
4002 return 0
4003 }
4004
4005 func (c *ctxt0) opir(a obj.As) uint32 {
4006 switch a {
4007 case ALU12IW:
4008 return 0x0a << 25
4009 case ALU32ID:
4010 return 0x0b << 25
4011 case APCALAU12I:
4012 return 0x0d << 25
4013 case APCADDU12I:
4014 return 0x0e << 25
4015 }
4016 return 0
4017 }
4018
4019 func (c *ctxt0) opirr(a obj.As) uint32 {
4020 switch a {
4021 case AADD, AADDU:
4022 return 0x00a << 22
4023 case ASGT:
4024 return 0x008 << 22
4025 case ASGTU:
4026 return 0x009 << 22
4027 case AAND:
4028 return 0x00d << 22
4029 case AOR:
4030 return 0x00e << 22
4031 case ALU52ID:
4032 return 0x00c << 22
4033 case AXOR:
4034 return 0x00f << 22
4035 case ASLL:
4036 return 0x00081 << 15
4037 case ASRL:
4038 return 0x00089 << 15
4039 case ASRA:
4040 return 0x00091 << 15
4041 case AROTR:
4042 return 0x00099 << 15
4043 case AADDV:
4044 return 0x00b << 22
4045 case AADDVU:
4046 return 0x00b << 22
4047 case AADDV16:
4048 return 0x4 << 26
4049
4050 case AJMP:
4051 return 0x14 << 26
4052 case AJAL:
4053 return 0x15 << 26
4054
4055 case AJIRL:
4056 return 0x13 << 26
4057 case ABLTU:
4058 return 0x1a << 26
4059 case ABLT, ABLTZ, ABGTZ:
4060 return 0x18 << 26
4061 case ABGEU:
4062 return 0x1b << 26
4063 case ABGE, ABGEZ, ABLEZ:
4064 return 0x19 << 26
4065 case -ABEQ:
4066 return 0x10 << 26
4067 case -ABNE:
4068 return 0x11 << 26
4069 case ABEQ:
4070 return 0x16 << 26
4071 case ABNE:
4072 return 0x17 << 26
4073 case ABFPT:
4074 return 0x12<<26 | 0x1<<8
4075 case ABFPF:
4076 return 0x12<<26 | 0x0<<8
4077 case APRELDX:
4078 return 0x07058 << 15
4079 case AMOVB,
4080 AMOVBU:
4081 return 0x0a4 << 22
4082 case AMOVH,
4083 AMOVHU:
4084 return 0x0a5 << 22
4085 case AMOVW,
4086 AMOVWU:
4087 return 0x0a6 << 22
4088 case AMOVV:
4089 return 0x0a7 << 22
4090 case AMOVF:
4091 return 0x0ad << 22
4092 case AMOVD:
4093 return 0x0af << 22
4094 case AMOVVP:
4095 return 0x27 << 24
4096 case AMOVWP:
4097 return 0x25 << 24
4098 case -AMOVB:
4099 return 0x0a0 << 22
4100 case -AMOVBU:
4101 return 0x0a8 << 22
4102 case -AMOVH:
4103 return 0x0a1 << 22
4104 case -AMOVHU:
4105 return 0x0a9 << 22
4106 case -AMOVW:
4107 return 0x0a2 << 22
4108 case -AMOVWU:
4109 return 0x0aa << 22
4110 case -AMOVV:
4111 return 0x0a3 << 22
4112 case -AMOVF:
4113 return 0x0ac << 22
4114 case -AMOVD:
4115 return 0x0ae << 22
4116 case -AMOVVP:
4117 return 0x26 << 24
4118 case -AMOVWP:
4119 return 0x24 << 24
4120 case -AVMOVQ:
4121 return 0x0b0 << 22
4122 case -AXVMOVQ:
4123 return 0x0b2 << 22
4124 case AVMOVQ:
4125 return 0x0b1 << 22
4126 case AXVMOVQ:
4127 return 0x0b3 << 22
4128 case ASLLV:
4129 return 0x0041 << 16
4130 case ASRLV:
4131 return 0x0045 << 16
4132 case ASRAV:
4133 return 0x0049 << 16
4134 case AROTRV:
4135 return 0x004d << 16
4136 case -ALL:
4137 return 0x020 << 24
4138 case -ALLV:
4139 return 0x022 << 24
4140 case ASC:
4141 return 0x021 << 24
4142 case ASCV:
4143 return 0x023 << 24
4144 case AVANDB:
4145 return 0x1CF4 << 18
4146 case AVORB:
4147 return 0x1CF5 << 18
4148 case AVXORB:
4149 return 0x1CF6 << 18
4150 case AVNORB:
4151 return 0x1CF7 << 18
4152 case AXVANDB:
4153 return 0x1DF4 << 18
4154 case AXVORB:
4155 return 0x1DF5 << 18
4156 case AXVXORB:
4157 return 0x1DF6 << 18
4158 case AXVNORB:
4159 return 0x1DF7 << 18
4160 case AVSEQB:
4161 return 0x0E500 << 15
4162 case AVSEQH:
4163 return 0x0E501 << 15
4164 case AVSEQW:
4165 return 0x0E502 << 15
4166 case AVSEQV:
4167 return 0x0E503 << 15
4168 case AXVSEQB:
4169 return 0x0ED00 << 15
4170 case AXVSEQH:
4171 return 0x0ED01 << 15
4172 case AXVSEQW:
4173 return 0x0ED02 << 15
4174 case AXVSEQV:
4175 return 0x0ED03 << 15
4176 case AVROTRB:
4177 return 0x1ca8<<18 | 0x1<<13
4178 case AVROTRH:
4179 return 0x1ca8<<18 | 0x1<<14
4180 case AVROTRW:
4181 return 0x1ca8<<18 | 0x1<<15
4182 case AVROTRV:
4183 return 0x1ca8<<18 | 0x1<<16
4184 case AXVROTRB:
4185 return 0x1da8<<18 | 0x1<<13
4186 case AXVROTRH:
4187 return 0x1da8<<18 | 0x1<<14
4188 case AXVROTRW:
4189 return 0x1da8<<18 | 0x1<<15
4190 case AXVROTRV:
4191 return 0x1da8<<18 | 0x1<<16
4192 case AVSLLB:
4193 return 0x1ccb<<18 | 0x1<<13
4194 case AVSLLH:
4195 return 0x1ccb<<18 | 0x1<<14
4196 case AVSLLW:
4197 return 0x1ccb<<18 | 0x1<<15
4198 case AVSLLV:
4199 return 0x1ccb<<18 | 0x1<<16
4200 case AVSRLB:
4201 return 0x1ccc<<18 | 0x1<<13
4202 case AVSRLH:
4203 return 0x1ccc<<18 | 0x1<<14
4204 case AVSRLW:
4205 return 0x1ccc<<18 | 0x1<<15
4206 case AVSRLV:
4207 return 0x1ccc<<18 | 0x1<<16
4208 case AVSRAB:
4209 return 0x1ccd<<18 | 0x1<<13
4210 case AVSRAH:
4211 return 0x1ccd<<18 | 0x1<<14
4212 case AVSRAW:
4213 return 0x1ccd<<18 | 0x1<<15
4214 case AVSRAV:
4215 return 0x1ccd<<18 | 0x1<<16
4216 case AXVSLLB:
4217 return 0x1dcb<<18 | 0x1<<13
4218 case AXVSLLH:
4219 return 0x1dcb<<18 | 0x1<<14
4220 case AXVSLLW:
4221 return 0x1dcb<<18 | 0x1<<15
4222 case AXVSLLV:
4223 return 0x1dcb<<18 | 0x1<<16
4224 case AXVSRLB:
4225 return 0x1dcc<<18 | 0x1<<13
4226 case AXVSRLH:
4227 return 0x1dcc<<18 | 0x1<<14
4228 case AXVSRLW:
4229 return 0x1dcc<<18 | 0x1<<15
4230 case AXVSRLV:
4231 return 0x1dcc<<18 | 0x1<<16
4232 case AXVSRAB:
4233 return 0x1dcd<<18 | 0x1<<13
4234 case AXVSRAH:
4235 return 0x1dcd<<18 | 0x1<<14
4236 case AXVSRAW:
4237 return 0x1dcd<<18 | 0x1<<15
4238 case AXVSRAV:
4239 return 0x1dcd<<18 | 0x1<<16
4240 case AVADDBU:
4241 return 0xe514 << 15
4242 case AVADDHU:
4243 return 0xe515 << 15
4244 case AVADDWU:
4245 return 0xe516 << 15
4246 case AVADDVU:
4247 return 0xe517 << 15
4248 case AVSUBBU:
4249 return 0xe518 << 15
4250 case AVSUBHU:
4251 return 0xe519 << 15
4252 case AVSUBWU:
4253 return 0xe51a << 15
4254 case AVSUBVU:
4255 return 0xe51b << 15
4256 case AXVADDBU:
4257 return 0xed14 << 15
4258 case AXVADDHU:
4259 return 0xed15 << 15
4260 case AXVADDWU:
4261 return 0xed16 << 15
4262 case AXVADDVU:
4263 return 0xed17 << 15
4264 case AXVSUBBU:
4265 return 0xed18 << 15
4266 case AXVSUBHU:
4267 return 0xed19 << 15
4268 case AXVSUBWU:
4269 return 0xed1a << 15
4270 case AXVSUBVU:
4271 return 0xed1b << 15
4272 case AVSHUF4IB:
4273 return 0x1ce4 << 18
4274 case AVSHUF4IH:
4275 return 0x1ce5 << 18
4276 case AVSHUF4IW:
4277 return 0x1ce6 << 18
4278 case AVSHUF4IV:
4279 return 0x1ce7 << 18
4280 case AXVSHUF4IB:
4281 return 0x1de4 << 18
4282 case AXVSHUF4IH:
4283 return 0x1de5 << 18
4284 case AXVSHUF4IW:
4285 return 0x1de6 << 18
4286 case AXVSHUF4IV:
4287 return 0x1de7 << 18
4288 case AVBITCLRB:
4289 return 0x1CC4<<18 | 0x1<<13
4290 case AVBITCLRH:
4291 return 0x1CC4<<18 | 0x1<<14
4292 case AVBITCLRW:
4293 return 0x1CC4<<18 | 0x1<<15
4294 case AVBITCLRV:
4295 return 0x1CC4<<18 | 0x1<<16
4296 case AVBITSETB:
4297 return 0x1CC5<<18 | 0x1<<13
4298 case AVBITSETH:
4299 return 0x1CC5<<18 | 0x1<<14
4300 case AVBITSETW:
4301 return 0x1CC5<<18 | 0x1<<15
4302 case AVBITSETV:
4303 return 0x1CC5<<18 | 0x1<<16
4304 case AVBITREVB:
4305 return 0x1CC6<<18 | 0x1<<13
4306 case AVBITREVH:
4307 return 0x1CC6<<18 | 0x1<<14
4308 case AVBITREVW:
4309 return 0x1CC6<<18 | 0x1<<15
4310 case AVBITREVV:
4311 return 0x1CC6<<18 | 0x1<<16
4312 case AXVBITCLRB:
4313 return 0x1DC4<<18 | 0x1<<13
4314 case AXVBITCLRH:
4315 return 0x1DC4<<18 | 0x1<<14
4316 case AXVBITCLRW:
4317 return 0x1DC4<<18 | 0x1<<15
4318 case AXVBITCLRV:
4319 return 0x1DC4<<18 | 0x1<<16
4320 case AXVBITSETB:
4321 return 0x1DC5<<18 | 0x1<<13
4322 case AXVBITSETH:
4323 return 0x1DC5<<18 | 0x1<<14
4324 case AXVBITSETW:
4325 return 0x1DC5<<18 | 0x1<<15
4326 case AXVBITSETV:
4327 return 0x1DC5<<18 | 0x1<<16
4328 case AXVBITREVB:
4329 return 0x1DC6<<18 | 0x1<<13
4330 case AXVBITREVH:
4331 return 0x1DC6<<18 | 0x1<<14
4332 case AXVBITREVW:
4333 return 0x1DC6<<18 | 0x1<<15
4334 case AXVBITREVV:
4335 return 0x1DC6<<18 | 0x1<<16
4336 }
4337
4338 if a < 0 {
4339 c.ctxt.Diag("bad irr opcode -%v", -a)
4340 } else {
4341 c.ctxt.Diag("bad irr opcode %v", a)
4342 }
4343 return 0
4344 }
4345
4346 func (c *ctxt0) opirrr(a obj.As) uint32 {
4347 switch a {
4348 case AALSLW:
4349 return 0x2 << 17
4350 case AALSLWU:
4351 return 0x3 << 17
4352 case AALSLV:
4353 return 0x16 << 17
4354 }
4355
4356 return 0
4357 }
4358
4359 func (c *ctxt0) opirir(a obj.As) uint32 {
4360 switch a {
4361 case ABSTRINSW:
4362 return 0x3<<21 | 0x0<<15
4363 case ABSTRINSV:
4364 return 0x2 << 22
4365 case ABSTRPICKW:
4366 return 0x3<<21 | 0x1<<15
4367 case ABSTRPICKV:
4368 return 0x3 << 22
4369 }
4370
4371 return 0
4372 }
4373
4374 func (c *ctxt0) opiir(a obj.As) uint32 {
4375 switch a {
4376 case APRELD:
4377 return 0x0AB << 22
4378 }
4379
4380 return 0
4381 }
4382
4383 func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 {
4384 switch a {
4385 case AMOVV:
4386 switch fclass {
4387 case C_REG:
4388 switch tclass {
4389 case C_FREG:
4390 return 0x452a << 10
4391 case C_FCCREG:
4392 return 0x4536 << 10
4393 case C_FCSRREG:
4394 return 0x4530 << 10
4395 }
4396 case C_FREG:
4397 switch tclass {
4398 case C_REG:
4399 return 0x452e << 10
4400 case C_FCCREG:
4401 return 0x4534 << 10
4402 }
4403 case C_FCCREG:
4404 switch tclass {
4405 case C_REG:
4406 return 0x4537 << 10
4407 case C_FREG:
4408 return 0x4535 << 10
4409 }
4410 case C_FCSRREG:
4411 switch tclass {
4412 case C_REG:
4413 return 0x4532 << 10
4414 }
4415 }
4416
4417 case AMOVW:
4418 switch fclass {
4419 case C_REG:
4420 switch tclass {
4421 case C_FREG:
4422 return 0x4529 << 10
4423 }
4424 case C_FREG:
4425 switch tclass {
4426 case C_REG:
4427 return 0x452d << 10
4428 }
4429 }
4430 }
4431
4432 c.ctxt.Diag("bad class combination: %s %s,%s\n", a, fclass, tclass)
4433
4434 return 0
4435 }
4436
4437 func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) {
4438 farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
4439 tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
4440 fclass := c.rclass(fReg)
4441 tclass := c.rclass(tReg)
4442
4443 switch fclass | (tclass << 16) {
4444 case C_REG | (C_ELEM << 16):
4445
4446 switch a {
4447 case AVMOVQ:
4448 switch tarng {
4449 case ARNG_B:
4450 return (0x01CBAE << 14), 0xf
4451 case ARNG_H:
4452 return (0x03975E << 13), 0x7
4453 case ARNG_W:
4454 return (0x072EBE << 12), 0x3
4455 case ARNG_V:
4456 return (0x0E5D7E << 11), 0x1
4457 }
4458 case AXVMOVQ:
4459 switch tarng {
4460 case ARNG_W:
4461 return (0x03B75E << 13), 0x7
4462 case ARNG_V:
4463 return (0x076EBE << 12), 0x3
4464 }
4465 }
4466
4467 case C_ELEM | (C_REG << 16):
4468
4469 switch a {
4470 case AVMOVQ:
4471 switch farng {
4472 case ARNG_B:
4473 return (0x01CBBE << 14), 0xf
4474 case ARNG_H:
4475 return (0x03977E << 13), 0x7
4476 case ARNG_W:
4477 return (0x072EFE << 12), 0x3
4478 case ARNG_V:
4479 return (0x0E5DFE << 11), 0x1
4480 case ARNG_BU:
4481 return (0x01CBCE << 14), 0xf
4482 case ARNG_HU:
4483 return (0x03979E << 13), 0x7
4484 case ARNG_WU:
4485 return (0x072F3E << 12), 0x3
4486 case ARNG_VU:
4487 return (0x0E5E7E << 11), 0x1
4488 }
4489 case AXVMOVQ:
4490 switch farng {
4491 case ARNG_W:
4492 return (0x03B77E << 13), 0x7
4493 case ARNG_V:
4494 return (0x076EFE << 12), 0x3
4495 case ARNG_WU:
4496 return (0x03B79E << 13), 0x7
4497 case ARNG_VU:
4498 return (0x076F3E << 12), 0x3
4499 }
4500 }
4501
4502 case C_REG | (C_ARNG << 16):
4503 switch {
4504 case offset_flag:
4505
4506 switch a {
4507 case AVMOVQ:
4508 switch tarng {
4509 case ARNG_16B:
4510 return (0xC2 << 22), 0x0
4511 case ARNG_8H:
4512 return (0x182 << 21), 0x0
4513 case ARNG_4W:
4514 return (0x302 << 20), 0x0
4515 case ARNG_2V:
4516 return (0x602 << 19), 0x0
4517 }
4518 case AXVMOVQ:
4519 switch tarng {
4520 case ARNG_32B:
4521 return (0xCA << 22), 0x0
4522 case ARNG_16H:
4523 return (0x192 << 21), 0x0
4524 case ARNG_8W:
4525 return (0x322 << 20), 0x0
4526 case ARNG_4V:
4527 return (0x642 << 19), 0x0
4528 }
4529 }
4530 default:
4531
4532 switch a {
4533 case AVMOVQ:
4534 switch tarng {
4535 case ARNG_16B:
4536 return (0x1CA7C0 << 10), 0x0
4537 case ARNG_8H:
4538 return (0x1CA7C1 << 10), 0x0
4539 case ARNG_4W:
4540 return (0x1CA7C2 << 10), 0x0
4541 case ARNG_2V:
4542 return (0x1CA7C3 << 10), 0x0
4543 }
4544 case AXVMOVQ:
4545 switch tarng {
4546 case ARNG_32B:
4547 return (0x1DA7C0 << 10), 0x0
4548 case ARNG_16H:
4549 return (0x1DA7C1 << 10), 0x0
4550 case ARNG_8W:
4551 return (0x1DA7C2 << 10), 0x0
4552 case ARNG_4V:
4553 return (0x1DA7C3 << 10), 0x0
4554 }
4555 }
4556 }
4557
4558 case C_XREG | (C_ARNG << 16):
4559
4560 switch a {
4561 case AVMOVQ:
4562 return 0, 0
4563 case AXVMOVQ:
4564 switch tarng {
4565 case ARNG_32B:
4566 return (0x1DC1C0 << 10), 0x0
4567 case ARNG_16H:
4568 return (0x1DC1E0 << 10), 0x0
4569 case ARNG_8W:
4570 return (0x1DC1F0 << 10), 0x0
4571 case ARNG_4V:
4572 return (0x1DC1F8 << 10), 0x0
4573 case ARNG_2Q:
4574 return (0x1DC1FC << 10), 0x0
4575 }
4576 }
4577
4578 case C_XREG | (C_ELEM << 16):
4579
4580 switch a {
4581 case AVMOVQ:
4582 return 0, 0
4583 case AXVMOVQ:
4584 switch tarng {
4585 case ARNG_W:
4586 return (0x03B7FE << 13), 0x7
4587 case ARNG_V:
4588 return (0x076FFE << 12), 0x3
4589 }
4590 }
4591
4592 case C_ELEM | (C_XREG << 16):
4593
4594 switch a {
4595 case AVMOVQ:
4596 return 0, 0
4597 case AXVMOVQ:
4598 switch farng {
4599 case ARNG_W:
4600 return (0x03B81E << 13), 0x7
4601 case ARNG_V:
4602 return (0x07703E << 12), 0x3
4603 }
4604 }
4605
4606 case C_ELEM | (C_ARNG << 16):
4607
4608 switch a {
4609 case AVMOVQ:
4610 switch int32(farng) | (int32(tarng) << 16) {
4611 case int32(ARNG_B) | (int32(ARNG_16B) << 16):
4612 return (0x01CBDE << 14), 0xf
4613 case int32(ARNG_H) | (int32(ARNG_8H) << 16):
4614 return (0x0397BE << 13), 0x7
4615 case int32(ARNG_W) | (int32(ARNG_4W) << 16):
4616 return (0x072F7E << 12), 0x3
4617 case int32(ARNG_V) | (int32(ARNG_2V) << 16):
4618 return (0x0E5EFE << 11), 0x1
4619 }
4620 case AXVMOVQ:
4621 return 0, 0
4622 }
4623 }
4624
4625 return 0, 0
4626 }
4627
4628 func vshift(a obj.As) bool {
4629 switch a {
4630 case ASLLV,
4631 ASRLV,
4632 ASRAV,
4633 AROTRV:
4634 return true
4635 }
4636 return false
4637 }
4638
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