Source file src/cmd/internal/obj/loong64/asm.go

     1  // Copyright 2022 The Go Authors. All rights reserved.
     2  // Use of this source code is governed by a BSD-style
     3  // license that can be found in the LICENSE file.
     4  
     5  package loong64
     6  
     7  import (
     8  	"cmd/internal/obj"
     9  	"cmd/internal/objabi"
    10  	"fmt"
    11  	"log"
    12  	"math/bits"
    13  	"slices"
    14  )
    15  
    16  // ctxt0 holds state while assembling a single function.
    17  // Each function gets a fresh ctxt0.
    18  // This allows for multiple functions to be safely concurrently assembled.
    19  type ctxt0 struct {
    20  	ctxt       *obj.Link
    21  	newprog    obj.ProgAlloc
    22  	cursym     *obj.LSym
    23  	autosize   int32
    24  	instoffset int64
    25  	pc         int64
    26  }
    27  
    28  // Instruction layout.
    29  
    30  const (
    31  	FuncAlign = 4
    32  	loopAlign = 16
    33  )
    34  
    35  type Optab struct {
    36  	as    obj.As
    37  	from1 uint8
    38  	reg   uint8
    39  	from3 uint8
    40  	to1   uint8
    41  	to2   uint8
    42  	type_ int8
    43  	size  int8
    44  	param int16
    45  	flag  uint8
    46  }
    47  
    48  const (
    49  	NOTUSETMP = 1 << iota // p expands to multiple instructions, but does NOT use REGTMP
    50  
    51  	// branchLoopHead marks loop entry.
    52  	// Used to insert padding for under-aligned loops.
    53  	branchLoopHead
    54  )
    55  
    56  var optab = []Optab{
    57  	{obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, C_NONE, 0, 0, 0, 0},
    58  
    59  	{AMOVW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
    60  	{AMOVV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 1, 4, 0, 0},
    61  	{AMOVB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
    62  	{AMOVBU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
    63  	{AMOVWU, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 12, 4, 0, 0},
    64  
    65  	{ASUB, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    66  	{ASUBV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    67  	{AADD, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    68  	{AADDV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    69  	{AAND, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    70  	{ASUB, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    71  	{ASUBV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    72  	{AADD, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    73  	{AADDV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    74  	{AAND, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    75  	{ANEGW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    76  	{ANEGV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    77  	{AMASKEQZ, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    78  	{ASLL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    79  	{ASLL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    80  	{ASLLV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    81  	{ASLLV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    82  	{AMUL, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    83  	{AMUL, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    84  	{AMULV, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    85  	{AMULV, C_REG, C_REG, C_NONE, C_REG, C_NONE, 2, 4, 0, 0},
    86  	{AADDF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
    87  	{AADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 2, 4, 0, 0},
    88  	{ACMPEQF, C_FREG, C_FREG, C_NONE, C_FCCREG, C_NONE, 2, 4, 0, 0},
    89  
    90  	{AVSEQB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
    91  	{AXVSEQB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
    92  	{AVSEQB, C_S5CON, C_VREG, C_NONE, C_VREG, C_NONE, 22, 4, 0, 0},
    93  	{AXVSEQB, C_S5CON, C_XREG, C_NONE, C_XREG, C_NONE, 22, 4, 0, 0},
    94  	{AVANDV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
    95  	{AVANDV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
    96  	{AXVANDV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
    97  	{AXVANDV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
    98  	{AVANDB, C_U8CON, C_VREG, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
    99  	{AVANDB, C_U8CON, C_NONE, C_NONE, C_VREG, C_NONE, 23, 4, 0, 0},
   100  	{AXVANDB, C_U8CON, C_XREG, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
   101  	{AXVANDB, C_U8CON, C_NONE, C_NONE, C_XREG, C_NONE, 23, 4, 0, 0},
   102  
   103  	{AVADDB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   104  	{AVADDB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   105  	{AXVADDB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   106  	{AXVADDB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   107  
   108  	{AVSLLB, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   109  	{AVSLLB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   110  	{AXVSLLB, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   111  	{AXVSLLB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   112  	{AVSLLB, C_U3CON, C_VREG, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
   113  	{AXVSLLB, C_U3CON, C_XREG, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
   114  	{AVSLLB, C_U3CON, C_NONE, C_NONE, C_VREG, C_NONE, 13, 4, 0, 0},
   115  	{AXVSLLB, C_U3CON, C_NONE, C_NONE, C_XREG, C_NONE, 13, 4, 0, 0},
   116  
   117  	{AVSLLH, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   118  	{AVSLLH, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   119  	{AXVSLLH, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   120  	{AXVSLLH, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   121  	{AVSLLH, C_U4CON, C_VREG, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
   122  	{AXVSLLH, C_U4CON, C_XREG, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
   123  	{AVSLLH, C_U4CON, C_NONE, C_NONE, C_VREG, C_NONE, 14, 4, 0, 0},
   124  	{AXVSLLH, C_U4CON, C_NONE, C_NONE, C_XREG, C_NONE, 14, 4, 0, 0},
   125  
   126  	{AVSLLW, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   127  	{AVSLLW, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   128  	{AXVSLLW, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   129  	{AXVSLLW, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   130  	{AVSLLW, C_U5CON, C_VREG, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
   131  	{AXVSLLW, C_U5CON, C_XREG, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
   132  	{AVSLLW, C_U5CON, C_NONE, C_NONE, C_VREG, C_NONE, 31, 4, 0, 0},
   133  	{AXVSLLW, C_U5CON, C_NONE, C_NONE, C_XREG, C_NONE, 31, 4, 0, 0},
   134  
   135  	{AVSLLV, C_VREG, C_VREG, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   136  	{AVSLLV, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 2, 4, 0, 0},
   137  	{AXVSLLV, C_XREG, C_XREG, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   138  	{AXVSLLV, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 2, 4, 0, 0},
   139  	{AVSLLV, C_U6CON, C_VREG, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
   140  	{AXVSLLV, C_U6CON, C_XREG, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
   141  	{AVSLLV, C_U6CON, C_NONE, C_NONE, C_VREG, C_NONE, 32, 4, 0, 0},
   142  	{AXVSLLV, C_U6CON, C_NONE, C_NONE, C_XREG, C_NONE, 32, 4, 0, 0},
   143  
   144  	{ACLOW, C_REG, C_NONE, C_NONE, C_REG, C_NONE, 9, 4, 0, 0},
   145  	{AABSF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
   146  	{AMOVVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
   147  	{AMOVF, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
   148  	{AMOVD, C_FREG, C_NONE, C_NONE, C_FREG, C_NONE, 9, 4, 0, 0},
   149  	{AVPCNTB, C_VREG, C_NONE, C_NONE, C_VREG, C_NONE, 9, 4, 0, 0},
   150  	{AXVPCNTB, C_XREG, C_NONE, C_NONE, C_XREG, C_NONE, 9, 4, 0, 0},
   151  	{AVSETEQV, C_VREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
   152  	{AXVSETEQV, C_XREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 9, 4, 0, 0},
   153  
   154  	{AFMADDF, C_FREG, C_FREG, C_NONE, C_FREG, C_NONE, 37, 4, 0, 0},
   155  	{AFMADDF, C_FREG, C_FREG, C_FREG, C_FREG, C_NONE, 37, 4, 0, 0},
   156  
   157  	{AFSEL, C_FCCREG, C_FREG, C_FREG, C_FREG, C_NONE, 33, 4, 0, 0},
   158  	{AFSEL, C_FCCREG, C_FREG, C_NONE, C_FREG, C_NONE, 33, 4, 0, 0},
   159  
   160  	{AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   161  	{AMOVWU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   162  	{AMOVV, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   163  	{AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   164  	{AMOVBU, C_REG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGSP, 0},
   165  	{AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   166  	{AMOVWU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   167  	{AMOVV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   168  	{AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   169  	{AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   170  	{AVMOVQ, C_VREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   171  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   172  	{AVMOVQ, C_VREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
   173  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 7, 4, REGZERO, 0},
   174  	{ASC, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   175  	{ASCV, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 7, 4, REGZERO, 0},
   176  
   177  	{AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   178  	{AMOVWU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   179  	{AMOVV, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   180  	{AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   181  	{AMOVBU, C_SAUTO, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGSP, 0},
   182  	{AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   183  	{AMOVWU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   184  	{AMOVV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   185  	{AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   186  	{AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   187  	{AVMOVQ, C_SOREG, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
   188  	{AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
   189  	{AVMOVQ, C_SAUTO, C_NONE, C_NONE, C_VREG, C_NONE, 8, 4, REGZERO, 0},
   190  	{AXVMOVQ, C_SAUTO, C_NONE, C_NONE, C_XREG, C_NONE, 8, 4, REGZERO, 0},
   191  	{ALL, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   192  	{ALLV, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 8, 4, REGZERO, 0},
   193  
   194  	{AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   195  	{AMOVWU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   196  	{AMOVV, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   197  	{AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   198  	{AMOVBU, C_REG, C_NONE, C_NONE, C_LAUTO, C_NONE, 35, 12, REGSP, 0},
   199  	{AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   200  	{AMOVWU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   201  	{AMOVV, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   202  	{AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   203  	{AMOVBU, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   204  	{ASC, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 35, 12, REGZERO, 0},
   205  	{AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   206  	{AMOVWU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   207  	{AMOVV, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   208  	{AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   209  	{AMOVBU, C_REG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   210  	{AMOVW, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   211  	{AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   212  	{AMOVV, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   213  	{AMOVB, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   214  	{AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_LE, C_NONE, 53, 16, 0, 0},
   215  	{AMOVWP, C_REG, C_NONE, C_NONE, C_SOREG, C_NONE, 73, 4, 0, 0},
   216  	{AMOVWP, C_REG, C_NONE, C_NONE, C_LOREG, C_NONE, 73, 4, 0, 0},
   217  
   218  	{AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   219  	{AMOVWU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   220  	{AMOVV, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   221  	{AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   222  	{AMOVBU, C_LAUTO, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGSP, 0},
   223  	{AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   224  	{AMOVWU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   225  	{AMOVV, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   226  	{AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   227  	{AMOVBU, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 36, 12, REGZERO, 0},
   228  	{AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   229  	{AMOVWU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   230  	{AMOVV, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   231  	{AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   232  	{AMOVBU, C_ADDR, C_NONE, C_NONE, C_REG, C_NONE, 51, 8, 0, 0},
   233  	{AMOVW, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   234  	{AMOVWU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   235  	{AMOVV, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   236  	{AMOVB, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   237  	{AMOVBU, C_TLS_LE, C_NONE, C_NONE, C_REG, C_NONE, 54, 16, 0, 0},
   238  	{AMOVWP, C_SOREG, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0},
   239  	{AMOVWP, C_LOREG, C_NONE, C_NONE, C_REG, C_NONE, 74, 4, 0, 0},
   240  
   241  	{AMOVW, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
   242  	{AMOVV, C_SACON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGSP, 0},
   243  	{AMOVW, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
   244  	{AMOVV, C_EXTADDR, C_NONE, C_NONE, C_REG, C_NONE, 52, 8, 0, NOTUSETMP},
   245  
   246  	{AMOVW, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
   247  	{AMOVV, C_LACON, C_NONE, C_NONE, C_REG, C_NONE, 27, 12, REGSP, 0},
   248  	{AMOVW, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
   249  	{AMOVV, C_12CON, C_NONE, C_NONE, C_REG, C_NONE, 3, 4, REGZERO, 0},
   250  
   251  	{AMOVW, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
   252  	{AMOVV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 25, 4, 0, 0},
   253  	{AMOVW, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
   254  	{AMOVV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 19, 8, 0, NOTUSETMP},
   255  	{AMOVV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 67, 4, 0, NOTUSETMP},
   256  	{AMOVV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 68, 8, 0, NOTUSETMP},
   257  	{AMOVV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 69, 12, 0, NOTUSETMP},
   258  	{AMOVV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 59, 16, 0, NOTUSETMP},
   259  
   260  	{AADD, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   261  	{AADD, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   262  	{AADD, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   263  	{AADD, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   264  
   265  	{AADDV, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   266  	{AADDV, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   267  	{AADDV, C_U12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   268  	{AADDV, C_U12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   269  
   270  	{AADDV16, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   271  	{AADDV16, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   272  
   273  	{AAND, C_UU12CON, C_REG, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   274  	{AAND, C_UU12CON, C_NONE, C_NONE, C_REG, C_NONE, 4, 4, 0, 0},
   275  	{AAND, C_S12CON, C_REG, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   276  	{AAND, C_S12CON, C_NONE, C_NONE, C_REG, C_NONE, 10, 8, 0, 0},
   277  
   278  	{AADD, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   279  	{AADD, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   280  	{AADDV, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   281  	{AADDV, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   282  	{AAND, C_32CON20_0, C_REG, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   283  	{AAND, C_32CON20_0, C_NONE, C_NONE, C_REG, C_NONE, 26, 8, 0, 0},
   284  
   285  	{AADD, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   286  	{AADDV, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   287  	{AAND, C_32CON, C_NONE, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   288  	{AADD, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   289  	{AADDV, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   290  	{AAND, C_32CON, C_REG, C_NONE, C_REG, C_NONE, 24, 12, 0, 0},
   291  
   292  	{AADDV, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
   293  	{AADDV, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
   294  	{AAND, C_DCON, C_NONE, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
   295  	{AAND, C_DCON, C_REG, C_NONE, C_REG, C_NONE, 60, 20, 0, 0},
   296  	{AADDV, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
   297  	{AADDV, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
   298  	{AAND, C_DCON12_0, C_NONE, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
   299  	{AAND, C_DCON12_0, C_REG, C_NONE, C_REG, C_NONE, 70, 8, 0, 0},
   300  	{AADDV, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
   301  	{AADDV, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
   302  	{AAND, C_DCON12_20S, C_NONE, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
   303  	{AAND, C_DCON12_20S, C_REG, C_NONE, C_REG, C_NONE, 71, 12, 0, 0},
   304  	{AADDV, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
   305  	{AADDV, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
   306  	{AAND, C_DCON32_12S, C_NONE, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
   307  	{AAND, C_DCON32_12S, C_REG, C_NONE, C_REG, C_NONE, 72, 16, 0, 0},
   308  
   309  	{ASLL, C_U5CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
   310  	{ASLL, C_U5CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
   311  
   312  	{ASLLV, C_U6CON, C_REG, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
   313  	{ASLLV, C_U6CON, C_NONE, C_NONE, C_REG, C_NONE, 16, 4, 0, 0},
   314  
   315  	{ABSTRPICKW, C_U6CON, C_REG, C_U6CON, C_REG, C_NONE, 17, 4, 0, 0},
   316  	{ABSTRPICKW, C_U6CON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
   317  	{ABSTRPICKW, C_ZCON, C_REG, C_ZCON, C_REG, C_NONE, 17, 4, 0, 0},
   318  
   319  	{ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
   320  	{ASYSCALL, C_U15CON, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0, 0},
   321  
   322  	{ABEQ, C_REG, C_REG, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   323  	{ABEQ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   324  	{ABLEZ, C_REG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   325  	{ABFPT, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   326  	{ABFPT, C_FCCREG, C_NONE, C_NONE, C_BRAN, C_NONE, 6, 4, 0, 0},
   327  
   328  	{AJMP, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // b
   329  	{AJAL, C_NONE, C_NONE, C_NONE, C_BRAN, C_NONE, 11, 4, 0, 0}, // bl
   330  
   331  	{AJMP, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGZERO, 0}, // jirl r0, rj, 0
   332  	{AJAL, C_NONE, C_NONE, C_NONE, C_ZOREG, C_NONE, 18, 4, REGLINK, 0}, // jirl r1, rj, 0
   333  
   334  	{AMOVF, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
   335  	{AMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGSP, 0},
   336  	{AMOVF, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
   337  	{AMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 4, REGZERO, 0},
   338  
   339  	{AMOVF, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
   340  	{AMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGSP, 0},
   341  	{AMOVF, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
   342  	{AMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, C_NONE, 28, 12, REGZERO, 0},
   343  	{AMOVF, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
   344  	{AMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, C_NONE, 51, 8, 0, 0},
   345  
   346  	{AMOVF, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
   347  	{AMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, C_NONE, 29, 4, REGSP, 0},
   348  	{AMOVF, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0},
   349  	{AMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, C_NONE, 29, 4, REGZERO, 0},
   350  
   351  	{AMOVF, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
   352  	{AMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, C_NONE, 29, 12, REGSP, 0},
   353  	{AMOVF, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0},
   354  	{AMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, C_NONE, 29, 12, REGZERO, 0},
   355  	{AMOVF, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   356  	{AMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, C_NONE, 50, 8, 0, 0},
   357  
   358  	{AMOVW, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
   359  	{AMOVV, C_REG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
   360  	{AMOVW, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
   361  	{AMOVV, C_FREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
   362  	{AMOVV, C_FCCREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
   363  	{AMOVV, C_FCSRREG, C_NONE, C_NONE, C_REG, C_NONE, 30, 4, 0, 0},
   364  	{AMOVV, C_REG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
   365  	{AMOVV, C_REG, C_NONE, C_NONE, C_FCSRREG, C_NONE, 30, 4, 0, 0},
   366  	{AMOVV, C_FREG, C_NONE, C_NONE, C_FCCREG, C_NONE, 30, 4, 0, 0},
   367  	{AMOVV, C_FCCREG, C_NONE, C_NONE, C_FREG, C_NONE, 30, 4, 0, 0},
   368  
   369  	{AMOVW, C_12CON, C_NONE, C_NONE, C_FREG, C_NONE, 34, 8, 0, 0},
   370  
   371  	{AMOVB, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   372  	{AMOVW, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   373  	{AMOVV, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   374  	{AMOVBU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   375  	{AMOVWU, C_REG, C_NONE, C_NONE, C_TLS_IE, C_NONE, 56, 16, 0, 0},
   376  
   377  	{AMOVB, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   378  	{AMOVW, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   379  	{AMOVV, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   380  	{AMOVBU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   381  	{AMOVWU, C_TLS_IE, C_NONE, C_NONE, C_REG, C_NONE, 57, 16, 0, 0},
   382  
   383  	{AWORD, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 38, 4, 0, 0},
   384  	{AWORD, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 61, 4, 0, 0},
   385  
   386  	{AMOVV, C_GOTADDR, C_NONE, C_NONE, C_REG, C_NONE, 65, 8, 0, 0},
   387  
   388  	{ATEQ, C_US12CON, C_REG, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
   389  	{ATEQ, C_US12CON, C_NONE, C_NONE, C_REG, C_NONE, 15, 8, 0, 0},
   390  
   391  	{ARDTIMELW, C_NONE, C_NONE, C_NONE, C_REG, C_REG, 62, 4, 0, 0},
   392  	{AAMSWAPW, C_REG, C_NONE, C_NONE, C_ZOREG, C_REG, 66, 4, 0, 0},
   393  	{ANOOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0},
   394  
   395  	/* store with extended register offset */
   396  	{AMOVB, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   397  	{AMOVW, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   398  	{AMOVV, C_REG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   399  	{AMOVF, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   400  	{AMOVD, C_FREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   401  	{AVMOVQ, C_VREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   402  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ROFF, C_NONE, 20, 4, 0, 0},
   403  
   404  	/* load with extended register offset */
   405  	{AMOVB, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   406  	{AMOVBU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   407  	{AMOVW, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   408  	{AMOVWU, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   409  	{AMOVV, C_ROFF, C_NONE, C_NONE, C_REG, C_NONE, 21, 4, 0, 0},
   410  	{AMOVF, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
   411  	{AMOVD, C_ROFF, C_NONE, C_NONE, C_FREG, C_NONE, 21, 4, 0, 0},
   412  	{AVMOVQ, C_ROFF, C_NONE, C_NONE, C_VREG, C_NONE, 21, 4, 0, 0},
   413  	{AXVMOVQ, C_ROFF, C_NONE, C_NONE, C_XREG, C_NONE, 21, 4, 0, 0},
   414  
   415  	{AVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
   416  	{AVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
   417  	{AXVMOVQ, C_REG, C_NONE, C_NONE, C_ELEM, C_NONE, 39, 4, 0, 0},
   418  	{AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_REG, C_NONE, 40, 4, 0, 0},
   419  
   420  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ELEM, C_NONE, 43, 4, 0, 0},
   421  	{AXVMOVQ, C_ELEM, C_NONE, C_NONE, C_XREG, C_NONE, 44, 4, 0, 0},
   422  
   423  	{AVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
   424  	{AXVMOVQ, C_REG, C_NONE, C_NONE, C_ARNG, C_NONE, 41, 4, 0, 0},
   425  	{AXVMOVQ, C_XREG, C_NONE, C_NONE, C_ARNG, C_NONE, 42, 4, 0, 0},
   426  
   427  	{AVMOVQ, C_ELEM, C_NONE, C_NONE, C_ARNG, C_NONE, 45, 4, 0, 0},
   428  
   429  	{AVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
   430  	{AXVMOVQ, C_SOREG, C_NONE, C_NONE, C_ARNG, C_NONE, 46, 4, 0, 0},
   431  
   432  	{APRELD, C_SOREG, C_U5CON, C_NONE, C_NONE, C_NONE, 47, 4, 0, 0},
   433  	{APRELDX, C_SOREG, C_DCON, C_U5CON, C_NONE, C_NONE, 48, 20, 0, 0},
   434  
   435  	{AALSLV, C_U3CON, C_REG, C_REG, C_REG, C_NONE, 64, 4, 0, 0},
   436  
   437  	{obj.APCALIGN, C_U12CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
   438  	{obj.APCDATA, C_32CON, C_NONE, C_NONE, C_32CON, C_NONE, 0, 0, 0, 0},
   439  	{obj.APCDATA, C_DCON, C_NONE, C_NONE, C_DCON, C_NONE, 0, 0, 0, 0},
   440  	{obj.AFUNCDATA, C_U12CON, C_NONE, C_NONE, C_ADDR, C_NONE, 0, 0, 0, 0},
   441  	{obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
   442  	{obj.ANOP, C_32CON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0}, // nop variants, see #40689
   443  	{obj.ANOP, C_DCON, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},  // nop variants, see #40689
   444  	{obj.ANOP, C_REG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
   445  	{obj.ANOP, C_FREG, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0, 0},
   446  }
   447  
   448  var atomicInst = map[obj.As]uint32{
   449  	AAMSWAPB:   0x070B8 << 15, // amswap.b
   450  	AAMSWAPH:   0x070B9 << 15, // amswap.h
   451  	AAMSWAPW:   0x070C0 << 15, // amswap.w
   452  	AAMSWAPV:   0x070C1 << 15, // amswap.d
   453  	AAMCASB:    0x070B0 << 15, // amcas.b
   454  	AAMCASH:    0x070B1 << 15, // amcas.h
   455  	AAMCASW:    0x070B2 << 15, // amcas.w
   456  	AAMCASV:    0x070B3 << 15, // amcas.d
   457  	AAMADDW:    0x070C2 << 15, // amadd.w
   458  	AAMADDV:    0x070C3 << 15, // amadd.d
   459  	AAMANDW:    0x070C4 << 15, // amand.w
   460  	AAMANDV:    0x070C5 << 15, // amand.d
   461  	AAMORW:     0x070C6 << 15, // amor.w
   462  	AAMORV:     0x070C7 << 15, // amor.d
   463  	AAMXORW:    0x070C8 << 15, // amxor.w
   464  	AAMXORV:    0x070C9 << 15, // amxor.d
   465  	AAMMAXW:    0x070CA << 15, // ammax.w
   466  	AAMMAXV:    0x070CB << 15, // ammax.d
   467  	AAMMINW:    0x070CC << 15, // ammin.w
   468  	AAMMINV:    0x070CD << 15, // ammin.d
   469  	AAMMAXWU:   0x070CE << 15, // ammax.wu
   470  	AAMMAXVU:   0x070CF << 15, // ammax.du
   471  	AAMMINWU:   0x070D0 << 15, // ammin.wu
   472  	AAMMINVU:   0x070D1 << 15, // ammin.du
   473  	AAMSWAPDBB: 0x070BC << 15, // amswap_db.b
   474  	AAMSWAPDBH: 0x070BD << 15, // amswap_db.h
   475  	AAMSWAPDBW: 0x070D2 << 15, // amswap_db.w
   476  	AAMSWAPDBV: 0x070D3 << 15, // amswap_db.d
   477  	AAMCASDBB:  0x070B4 << 15, // amcas_db.b
   478  	AAMCASDBH:  0x070B5 << 15, // amcas_db.h
   479  	AAMCASDBW:  0x070B6 << 15, // amcas_db.w
   480  	AAMCASDBV:  0x070B7 << 15, // amcas_db.d
   481  	AAMADDDBW:  0x070D4 << 15, // amadd_db.w
   482  	AAMADDDBV:  0x070D5 << 15, // amadd_db.d
   483  	AAMANDDBW:  0x070D6 << 15, // amand_db.w
   484  	AAMANDDBV:  0x070D7 << 15, // amand_db.d
   485  	AAMORDBW:   0x070D8 << 15, // amor_db.w
   486  	AAMORDBV:   0x070D9 << 15, // amor_db.d
   487  	AAMXORDBW:  0x070DA << 15, // amxor_db.w
   488  	AAMXORDBV:  0x070DB << 15, // amxor_db.d
   489  	AAMMAXDBW:  0x070DC << 15, // ammax_db.w
   490  	AAMMAXDBV:  0x070DD << 15, // ammax_db.d
   491  	AAMMINDBW:  0x070DE << 15, // ammin_db.w
   492  	AAMMINDBV:  0x070DF << 15, // ammin_db.d
   493  	AAMMAXDBWU: 0x070E0 << 15, // ammax_db.wu
   494  	AAMMAXDBVU: 0x070E1 << 15, // ammax_db.du
   495  	AAMMINDBWU: 0x070E2 << 15, // ammin_db.wu
   496  	AAMMINDBVU: 0x070E3 << 15, // ammin_db.du
   497  }
   498  
   499  func IsAtomicInst(as obj.As) bool {
   500  	_, ok := atomicInst[as]
   501  
   502  	return ok
   503  }
   504  
   505  // pcAlignPadLength returns the number of bytes required to align pc to alignedValue,
   506  // reporting an error if alignedValue is not a power of two or is out of range.
   507  func pcAlignPadLength(ctxt *obj.Link, pc int64, alignedValue int64) int {
   508  	if !((alignedValue&(alignedValue-1) == 0) && 8 <= alignedValue && alignedValue <= 2048) {
   509  		ctxt.Diag("alignment value of an instruction must be a power of two and in the range [8, 2048], got %d\n", alignedValue)
   510  	}
   511  	return int(-pc & (alignedValue - 1))
   512  }
   513  
   514  var oprange [ALAST & obj.AMask][]Optab
   515  
   516  var xcmp [C_NCLASS][C_NCLASS]bool
   517  
   518  func span0(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
   519  	if ctxt.Retpoline {
   520  		ctxt.Diag("-spectre=ret not supported on loong64")
   521  		ctxt.Retpoline = false // don't keep printing
   522  	}
   523  
   524  	p := cursym.Func().Text
   525  	if p == nil || p.Link == nil { // handle external functions and ELF section symbols
   526  		return
   527  	}
   528  
   529  	c := ctxt0{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset + ctxt.Arch.FixedFrameSize)}
   530  
   531  	if oprange[AOR&obj.AMask] == nil {
   532  		c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
   533  	}
   534  
   535  	pc := int64(0)
   536  	p.Pc = pc
   537  
   538  	var m int
   539  	var o *Optab
   540  	for p = p.Link; p != nil; p = p.Link {
   541  		p.Pc = pc
   542  		o = c.oplook(p)
   543  		m = int(o.size)
   544  		if m == 0 {
   545  			switch p.As {
   546  			case obj.APCALIGN:
   547  				alignedValue := p.From.Offset
   548  				m = pcAlignPadLength(ctxt, pc, alignedValue)
   549  				// Update the current text symbol alignment value.
   550  				if int32(alignedValue) > cursym.Func().Align {
   551  					cursym.Func().Align = int32(alignedValue)
   552  				}
   553  				break
   554  			case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
   555  				continue
   556  			default:
   557  				c.ctxt.Diag("zero-width instruction\n%v", p)
   558  			}
   559  		}
   560  
   561  		pc += int64(m)
   562  	}
   563  
   564  	c.cursym.Size = pc
   565  
   566  	// mark loop entry instructions for padding
   567  	// loop entrances are defined as targets of backward branches
   568  	for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
   569  		if q := p.To.Target(); q != nil && q.Pc < p.Pc {
   570  			q.Mark |= branchLoopHead
   571  		}
   572  	}
   573  
   574  	// Run these passes until convergence.
   575  	for {
   576  		rescan := false
   577  		pc = 0
   578  		prev := c.cursym.Func().Text
   579  		for p = prev.Link; p != nil; prev, p = p, p.Link {
   580  			p.Pc = pc
   581  			o = c.oplook(p)
   582  
   583  			// Prepend a PCALIGN $loopAlign to each of the loop heads
   584  			// that need padding, if not already done so (because this
   585  			// pass may execute more than once).
   586  			//
   587  			// This needs to come before any pass that look at pc,
   588  			// because pc will be adjusted if padding happens.
   589  			if p.Mark&branchLoopHead != 0 && pc&(loopAlign-1) != 0 &&
   590  				!(prev.As == obj.APCALIGN && prev.From.Offset >= loopAlign) {
   591  				q := c.newprog()
   592  				prev.Link = q
   593  				q.Link = p
   594  				q.Pc = pc
   595  				q.As = obj.APCALIGN
   596  				q.From.Type = obj.TYPE_CONST
   597  				q.From.Offset = loopAlign
   598  				// Don't associate the synthesized PCALIGN with
   599  				// the original source position, for deterministic
   600  				// mapping between source and corresponding asm.
   601  				// q.Pos = p.Pos
   602  
   603  				// Manually make the PCALIGN come into effect,
   604  				// since this loop iteration is for p.
   605  				pc += int64(pcAlignPadLength(ctxt, pc, loopAlign))
   606  				p.Pc = pc
   607  				rescan = true
   608  			}
   609  
   610  			// very large conditional branches
   611  			//
   612  			// if any procedure is large enough to generate a large SBRA branch, then
   613  			// generate extra passes putting branches around jmps to fix. this is rare.
   614  			if o.type_ == 6 && p.To.Target() != nil {
   615  				otxt := p.To.Target().Pc - pc
   616  
   617  				// On loong64, the immediate value field of the conditional branch instructions
   618  				// BFPT and BFPT is 21 bits, and the others are 16 bits. The jump target address
   619  				// is to logically shift the immediate value in the instruction code to the left
   620  				// by 2 bits and then sign extend.
   621  				bound := int64(1 << (18 - 1))
   622  
   623  				switch p.As {
   624  				case ABFPT, ABFPF:
   625  					bound = int64(1 << (23 - 1))
   626  				}
   627  
   628  				if otxt < -bound || otxt >= bound {
   629  					q := c.newprog()
   630  					q.Link = p.Link
   631  					p.Link = q
   632  					q.As = AJMP
   633  					q.Pos = p.Pos
   634  					q.To.Type = obj.TYPE_BRANCH
   635  					q.To.SetTarget(p.To.Target())
   636  					p.To.SetTarget(q)
   637  					q = c.newprog()
   638  					q.Link = p.Link
   639  					p.Link = q
   640  					q.As = AJMP
   641  					q.Pos = p.Pos
   642  					q.To.Type = obj.TYPE_BRANCH
   643  					q.To.SetTarget(q.Link.Link)
   644  					rescan = true
   645  				}
   646  			}
   647  
   648  			m = int(o.size)
   649  			if m == 0 {
   650  				switch p.As {
   651  				case obj.APCALIGN:
   652  					alignedValue := p.From.Offset
   653  					m = pcAlignPadLength(ctxt, pc, alignedValue)
   654  					break
   655  				case obj.ANOP, obj.AFUNCDATA, obj.APCDATA:
   656  					continue
   657  				default:
   658  					c.ctxt.Diag("zero-width instruction\n%v", p)
   659  				}
   660  			}
   661  
   662  			pc += int64(m)
   663  		}
   664  
   665  		c.cursym.Size = pc
   666  
   667  		if !rescan {
   668  			break
   669  		}
   670  	}
   671  
   672  	pc += -pc & (FuncAlign - 1)
   673  	c.cursym.Size = pc
   674  
   675  	// lay out the code, emitting code and data relocations.
   676  
   677  	c.cursym.Grow(c.cursym.Size)
   678  
   679  	bp := c.cursym.P
   680  	var i int32
   681  	var out [5]uint32
   682  	for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
   683  		c.pc = p.Pc
   684  		o = c.oplook(p)
   685  		if int(o.size) > 4*len(out) {
   686  			log.Fatalf("out array in span0 is too small, need at least %d for %v", o.size/4, p)
   687  		}
   688  		if p.As == obj.APCALIGN {
   689  			alignedValue := p.From.Offset
   690  			v := pcAlignPadLength(c.ctxt, p.Pc, alignedValue)
   691  			for i = 0; i < int32(v/4); i++ {
   692  				// emit ANOOP instruction by the padding size
   693  				c.ctxt.Arch.ByteOrder.PutUint32(bp, OP_12IRR(c.opirr(AAND), 0, 0, 0))
   694  				bp = bp[4:]
   695  			}
   696  			continue
   697  		}
   698  		c.asmout(p, o, out[:])
   699  		for i = 0; i < int32(o.size/4); i++ {
   700  			c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
   701  			bp = bp[4:]
   702  		}
   703  	}
   704  
   705  	// Mark nonpreemptible instruction sequences.
   706  	// We use REGTMP as a scratch register during call injection,
   707  	// so instruction sequences that use REGTMP are unsafe to
   708  	// preempt asynchronously.
   709  	obj.MarkUnsafePoints(c.ctxt, c.cursym.Func().Text, c.newprog, c.isUnsafePoint, c.isRestartable)
   710  
   711  	// Now that we know byte offsets, we can generate jump table entries.
   712  	for _, jt := range cursym.Func().JumpTables {
   713  		for i, p := range jt.Targets {
   714  			// The ith jumptable entry points to the p.Pc'th
   715  			// byte in the function symbol s.
   716  			jt.Sym.WriteAddr(ctxt, int64(i)*8, 8, cursym, p.Pc)
   717  		}
   718  	}
   719  }
   720  
   721  // isUnsafePoint returns whether p is an unsafe point.
   722  func (c *ctxt0) isUnsafePoint(p *obj.Prog) bool {
   723  	// If p explicitly uses REGTMP, it's unsafe to preempt, because the
   724  	// preemption sequence clobbers REGTMP.
   725  	return p.From.Reg == REGTMP || p.To.Reg == REGTMP || p.Reg == REGTMP
   726  }
   727  
   728  // isRestartable returns whether p is a multi-instruction sequence that,
   729  // if preempted, can be restarted.
   730  func (c *ctxt0) isRestartable(p *obj.Prog) bool {
   731  	if c.isUnsafePoint(p) {
   732  		return false
   733  	}
   734  	// If p is a multi-instruction sequence with uses REGTMP inserted by
   735  	// the assembler in order to materialize a large constant/offset, we
   736  	// can restart p (at the start of the instruction sequence), recompute
   737  	// the content of REGTMP, upon async preemption. Currently, all cases
   738  	// of assembler-inserted REGTMP fall into this category.
   739  	// If p doesn't use REGTMP, it can be simply preempted, so we don't
   740  	// mark it.
   741  	o := c.oplook(p)
   742  	return o.size > 4 && o.flag&NOTUSETMP == 0
   743  }
   744  
   745  func isint32(v int64) bool {
   746  	return int64(int32(v)) == v
   747  }
   748  
   749  func (c *ctxt0) aclass(a *obj.Addr) int {
   750  	switch a.Type {
   751  	case obj.TYPE_NONE:
   752  		return C_NONE
   753  
   754  	case obj.TYPE_REG:
   755  		return c.rclass(a.Reg)
   756  
   757  	case obj.TYPE_MEM:
   758  		switch a.Name {
   759  		case obj.NAME_EXTERN,
   760  			obj.NAME_STATIC:
   761  			if a.Sym == nil {
   762  				break
   763  			}
   764  			c.instoffset = a.Offset
   765  			if a.Sym.Type == objabi.STLSBSS {
   766  				if c.ctxt.Flag_shared {
   767  					return C_TLS_IE
   768  				} else {
   769  					return C_TLS_LE
   770  				}
   771  			}
   772  			return C_ADDR
   773  
   774  		case obj.NAME_AUTO:
   775  			if a.Reg == REGSP {
   776  				// unset base register for better printing, since
   777  				// a.Offset is still relative to pseudo-SP.
   778  				a.Reg = obj.REG_NONE
   779  			}
   780  			c.instoffset = int64(c.autosize) + a.Offset
   781  			if c.instoffset >= -BIG && c.instoffset < BIG {
   782  				return C_SAUTO
   783  			}
   784  			return C_LAUTO
   785  
   786  		case obj.NAME_PARAM:
   787  			if a.Reg == REGSP {
   788  				// unset base register for better printing, since
   789  				// a.Offset is still relative to pseudo-FP.
   790  				a.Reg = obj.REG_NONE
   791  			}
   792  			c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
   793  			if c.instoffset >= -BIG && c.instoffset < BIG {
   794  				return C_SAUTO
   795  			}
   796  			return C_LAUTO
   797  
   798  		case obj.NAME_NONE:
   799  			if a.Index != 0 {
   800  				if a.Offset != 0 {
   801  					return C_GOK
   802  				}
   803  				// register offset
   804  				return C_ROFF
   805  			}
   806  
   807  			c.instoffset = a.Offset
   808  			if c.instoffset == 0 {
   809  				return C_ZOREG
   810  			}
   811  			if c.instoffset >= -BIG && c.instoffset < BIG {
   812  				return C_SOREG
   813  			}
   814  			return C_LOREG
   815  
   816  		case obj.NAME_GOTREF:
   817  			return C_GOTADDR
   818  		}
   819  
   820  		return C_GOK
   821  
   822  	case obj.TYPE_TEXTSIZE:
   823  		return C_TEXTSIZE
   824  
   825  	case obj.TYPE_CONST,
   826  		obj.TYPE_ADDR:
   827  		switch a.Name {
   828  		case obj.NAME_NONE:
   829  			c.instoffset = a.Offset
   830  			if a.Reg != 0 {
   831  				if -BIG <= c.instoffset && c.instoffset <= BIG {
   832  					return C_SACON
   833  				}
   834  				if isint32(c.instoffset) {
   835  					return C_LACON
   836  				}
   837  				return C_DACON
   838  			}
   839  
   840  		case obj.NAME_EXTERN,
   841  			obj.NAME_STATIC:
   842  			s := a.Sym
   843  			if s == nil {
   844  				return C_GOK
   845  			}
   846  
   847  			c.instoffset = a.Offset
   848  			if s.Type == objabi.STLSBSS {
   849  				c.ctxt.Diag("taking address of TLS variable is not supported")
   850  			}
   851  			return C_EXTADDR
   852  
   853  		case obj.NAME_AUTO:
   854  			if a.Reg == REGSP {
   855  				// unset base register for better printing, since
   856  				// a.Offset is still relative to pseudo-SP.
   857  				a.Reg = obj.REG_NONE
   858  			}
   859  			c.instoffset = int64(c.autosize) + a.Offset
   860  			if c.instoffset >= -BIG && c.instoffset < BIG {
   861  				return C_SACON
   862  			}
   863  			return C_LACON
   864  
   865  		case obj.NAME_PARAM:
   866  			if a.Reg == REGSP {
   867  				// unset base register for better printing, since
   868  				// a.Offset is still relative to pseudo-FP.
   869  				a.Reg = obj.REG_NONE
   870  			}
   871  			c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
   872  			if c.instoffset >= -BIG && c.instoffset < BIG {
   873  				return C_SACON
   874  			}
   875  			return C_LACON
   876  
   877  		default:
   878  			return C_GOK
   879  		}
   880  
   881  		if c.instoffset != int64(int32(c.instoffset)) {
   882  			return dconClass(c.instoffset)
   883  		}
   884  
   885  		if c.instoffset >= 0 {
   886  			sbits := bits.Len64(uint64(c.instoffset))
   887  			switch {
   888  			case sbits <= 8:
   889  				return C_ZCON + sbits
   890  			case sbits <= 12:
   891  				if c.instoffset <= 0x7ff {
   892  					return C_US12CON
   893  				}
   894  				return C_U12CON
   895  			case sbits <= 13:
   896  				if c.instoffset&0xfff == 0 {
   897  					return C_U13CON20_0
   898  				}
   899  				return C_U13CON
   900  			case sbits <= 15:
   901  				if c.instoffset&0xfff == 0 {
   902  					return C_U15CON20_0
   903  				}
   904  				return C_U15CON
   905  			}
   906  		} else {
   907  			sbits := bits.Len64(uint64(^c.instoffset))
   908  			switch {
   909  			case sbits < 5:
   910  				return C_S5CON
   911  			case sbits < 12:
   912  				return C_S12CON
   913  			case sbits < 13:
   914  				if c.instoffset&0xfff == 0 {
   915  					return C_S13CON20_0
   916  				}
   917  				return C_S13CON
   918  			}
   919  		}
   920  
   921  		if c.instoffset&0xfff == 0 {
   922  			return C_32CON20_0
   923  		}
   924  		return C_32CON
   925  
   926  	case obj.TYPE_BRANCH:
   927  		return C_BRAN
   928  	}
   929  
   930  	return C_GOK
   931  }
   932  
   933  // The constants here define the data characteristics within the bit field range.
   934  //
   935  //	ALL1: The data in the bit field is all 1
   936  //	ALL0: The data in the bit field is all 0
   937  //	ST1: The data in the bit field starts with 1, but not all 1
   938  //	ST0: The data in the bit field starts with 0, but not all 0
   939  const (
   940  	ALL1 = iota
   941  	ALL0
   942  	ST1
   943  	ST0
   944  )
   945  
   946  // mask returns the mask of the specified bit field, which is used to help determine
   947  // the data characteristics of the immediate value at the specified bit.
   948  func mask(suf int8, len int8) (uint64, uint64) {
   949  	if len == 12 {
   950  		if suf == 0 {
   951  			return 0xfff, 0x800
   952  		} else { // suf == 52
   953  			return 0xfff0000000000000, 0x8000000000000000
   954  		}
   955  	} else { // len == 20
   956  		if suf == 12 {
   957  			return 0xfffff000, 0x80000000
   958  		} else { // suf == 32
   959  			return 0xfffff00000000, 0x8000000000000
   960  		}
   961  	}
   962  }
   963  
   964  // bitField return a number represent status of val in bit field
   965  //
   966  //	suf: The starting bit of the bit field
   967  //	len: The length of the bit field
   968  func bitField(val int64, suf int8, len int8) int8 {
   969  	mask1, mask2 := mask(suf, len)
   970  	if uint64(val)&mask1 == mask1 {
   971  		return ALL1
   972  	} else if uint64(val)&mask1 == 0x0 {
   973  		return ALL0
   974  	} else if uint64(val)&mask2 == mask2 {
   975  		return ST1
   976  	} else {
   977  		return ST0
   978  	}
   979  }
   980  
   981  // Loading an immediate value larger than 32 bits requires four instructions
   982  // on loong64 (lu12i.w + ori + lu32i.d + lu52i.d), but in some special cases,
   983  // we can use the sign extension and zero extension features of the instruction
   984  // to fill in the high-order data (all 0 or all 1), which can save one to
   985  // three instructions.
   986  //
   987  //	| 63 ~ 52 | 51 ~ 32 | 31 ~ 12 | 11 ~ 0 |
   988  //	| lu52i.d | lu32i.d | lu12i.w |   ori  |
   989  func dconClass(offset int64) int {
   990  	tzb := bits.TrailingZeros64(uint64(offset))
   991  	hi12 := bitField(offset, 52, 12)
   992  	hi20 := bitField(offset, 32, 20)
   993  	lo20 := bitField(offset, 12, 20)
   994  	lo12 := bitField(offset, 0, 12)
   995  	if tzb >= 52 {
   996  		return C_DCON12_0 // lu52i.d
   997  	}
   998  	if tzb >= 32 {
   999  		if ((hi20 == ALL1 || hi20 == ST1) && hi12 == ALL1) || ((hi20 == ALL0 || hi20 == ST0) && hi12 == ALL0) {
  1000  			return C_DCON20S_0 // addi.w + lu32i.d
  1001  		}
  1002  		return C_DCON32_0 // addi.w + lu32i.d + lu52i.d
  1003  	}
  1004  	if tzb >= 12 {
  1005  		if lo20 == ST1 || lo20 == ALL1 {
  1006  			if hi20 == ALL1 {
  1007  				return C_DCON12_20S // lu12i.w + lu52i.d
  1008  			}
  1009  			if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
  1010  				return C_DCON20S_20 // lu12i.w + lu32i.d
  1011  			}
  1012  			return C_DCON32_20 // lu12i.w + lu32i.d + lu52i.d
  1013  		}
  1014  		if hi20 == ALL0 {
  1015  			return C_DCON12_20S // lu12i.w + lu52i.d
  1016  		}
  1017  		if (hi20 == ST0 && hi12 == ALL0) || ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) {
  1018  			return C_DCON20S_20 // lu12i.w + lu32i.d
  1019  		}
  1020  		return C_DCON32_20 // lu12i.w + lu32i.d + lu52i.d
  1021  	}
  1022  	if lo12 == ST1 || lo12 == ALL1 {
  1023  		if lo20 == ALL1 {
  1024  			if hi20 == ALL1 {
  1025  				return C_DCON12_12S // addi.d + lu52i.d
  1026  			}
  1027  			if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
  1028  				return C_DCON20S_12S // addi.w + lu32i.d
  1029  			}
  1030  			return C_DCON32_12S // addi.w + lu32i.d + lu52i.d
  1031  		}
  1032  		if lo20 == ST1 {
  1033  			if hi20 == ALL1 {
  1034  
  1035  				return C_DCON12_32S // lu12i.w + ori + lu52i.d
  1036  			}
  1037  			if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
  1038  				return C_DCON20S_32 // lu12i.w + ori + lu32i.d
  1039  			}
  1040  			return C_DCON // lu12i.w + ori + lu32i.d + lu52i.d
  1041  		}
  1042  		if lo20 == ALL0 {
  1043  			if hi20 == ALL0 {
  1044  				return C_DCON12_12U // ori + lu52i.d
  1045  			}
  1046  			if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
  1047  				return C_DCON20S_12U // ori + lu32i.d
  1048  			}
  1049  			return C_DCON32_12U // ori + lu32i.d + lu52i.d
  1050  		}
  1051  		if hi20 == ALL0 {
  1052  			return C_DCON12_32S // lu12i.w + ori + lu52i.d
  1053  		}
  1054  		if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
  1055  			return C_DCON20S_32 // lu12i.w + ori + lu32i.d
  1056  		}
  1057  		return C_DCON // lu12i.w + ori + lu32i.d + lu52i.d
  1058  	}
  1059  	if lo20 == ALL0 {
  1060  		if hi20 == ALL0 {
  1061  			return C_DCON12_12U // ori + lu52i.d
  1062  		}
  1063  		if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
  1064  			return C_DCON20S_12U // ori + lu32i.d
  1065  		}
  1066  		return C_DCON32_12U // ori + lu32i.d + lu52i.d
  1067  	}
  1068  	if lo20 == ST1 || lo20 == ALL1 {
  1069  		if hi20 == ALL1 {
  1070  			return C_DCON12_32S // lu12i.w + ori + lu52i.d
  1071  		}
  1072  		if (hi20 == ST1 && hi12 == ALL1) || ((hi20 == ST0 || hi20 == ALL0) && hi12 == ALL0) {
  1073  			return C_DCON20S_32 // lu12i.w + ori + lu32i.d
  1074  		}
  1075  		return C_DCON
  1076  	}
  1077  	if hi20 == ALL0 {
  1078  		return C_DCON12_32S // lu12i.w + ori + lu52i.d
  1079  	}
  1080  	if ((hi20 == ST1 || hi20 == ALL1) && hi12 == ALL1) || (hi20 == ST0 && hi12 == ALL0) {
  1081  		return C_DCON20S_32 // lu12i.w + ori + lu32i.d
  1082  	}
  1083  	return C_DCON
  1084  }
  1085  
  1086  // In Loong64，there are 8 CFRs, denoted as fcc0-fcc7.
  1087  // There are 4 FCSRs, denoted as fcsr0-fcsr3.
  1088  func (c *ctxt0) rclass(r int16) int {
  1089  	switch {
  1090  	case REG_R0 <= r && r <= REG_R31:
  1091  		return C_REG
  1092  	case REG_F0 <= r && r <= REG_F31:
  1093  		return C_FREG
  1094  	case REG_FCC0 <= r && r <= REG_FCC7:
  1095  		return C_FCCREG
  1096  	case REG_FCSR0 <= r && r <= REG_FCSR3:
  1097  		return C_FCSRREG
  1098  	case REG_V0 <= r && r <= REG_V31:
  1099  		return C_VREG
  1100  	case REG_X0 <= r && r <= REG_X31:
  1101  		return C_XREG
  1102  	case r >= REG_ARNG && r < REG_ELEM:
  1103  		return C_ARNG
  1104  	case r >= REG_ELEM && r < REG_ELEM_END:
  1105  		return C_ELEM
  1106  	}
  1107  
  1108  	return C_GOK
  1109  }
  1110  
  1111  func oclass(a *obj.Addr) int {
  1112  	return int(a.Class) - 1
  1113  }
  1114  
  1115  func prasm(p *obj.Prog) {
  1116  	fmt.Printf("%v\n", p)
  1117  }
  1118  
  1119  func (c *ctxt0) oplook(p *obj.Prog) *Optab {
  1120  	if oprange[AOR&obj.AMask] == nil {
  1121  		c.ctxt.Diag("loong64 ops not initialized, call loong64.buildop first")
  1122  	}
  1123  
  1124  	restArgsIndex := 0
  1125  	restArgsLen := len(p.RestArgs)
  1126  	if restArgsLen > 2 {
  1127  		c.ctxt.Diag("too many RestArgs: got %v, maximum is 2\n", restArgsLen)
  1128  		return nil
  1129  	}
  1130  
  1131  	restArgsv := [2]int{C_NONE + 1, C_NONE + 1}
  1132  	for i, ap := range p.RestArgs {
  1133  		restArgsv[i] = int(ap.Addr.Class)
  1134  		if restArgsv[i] == 0 {
  1135  			restArgsv[i] = c.aclass(&ap.Addr) + 1
  1136  			ap.Addr.Class = int8(restArgsv[i])
  1137  		}
  1138  	}
  1139  
  1140  	a1 := int(p.Optab)
  1141  	if a1 != 0 {
  1142  		return &optab[a1-1]
  1143  	}
  1144  
  1145  	// first source operand
  1146  	a1 = int(p.From.Class)
  1147  	if a1 == 0 {
  1148  		a1 = c.aclass(&p.From) + 1
  1149  		p.From.Class = int8(a1)
  1150  	}
  1151  	a1--
  1152  
  1153  	// first destination operand
  1154  	a4 := int(p.To.Class)
  1155  	if a4 == 0 {
  1156  		a4 = c.aclass(&p.To) + 1
  1157  		p.To.Class = int8(a4)
  1158  	}
  1159  	a4--
  1160  
  1161  	// 2nd source operand
  1162  	a2 := C_NONE
  1163  	if p.Reg != 0 {
  1164  		a2 = c.rclass(p.Reg)
  1165  	} else if restArgsLen > 0 {
  1166  		a2 = restArgsv[restArgsIndex] - 1
  1167  		restArgsIndex++
  1168  	}
  1169  
  1170  	// 2nd destination operand
  1171  	a5 := C_NONE
  1172  	if p.RegTo2 != 0 {
  1173  		a5 = C_REG
  1174  	}
  1175  
  1176  	// 3rd source operand
  1177  	a3 := C_NONE
  1178  	if restArgsLen > 0 && restArgsIndex < restArgsLen {
  1179  		a3 = restArgsv[restArgsIndex] - 1
  1180  		restArgsIndex++
  1181  	}
  1182  
  1183  	ops := oprange[p.As&obj.AMask]
  1184  	c1 := &xcmp[a1]
  1185  	c2 := &xcmp[a2]
  1186  	c3 := &xcmp[a3]
  1187  	c4 := &xcmp[a4]
  1188  	c5 := &xcmp[a5]
  1189  	for i := range ops {
  1190  		op := &ops[i]
  1191  		if c1[op.from1] && c2[op.reg] && c3[op.from3] && c4[op.to1] && c5[op.to2] {
  1192  			p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
  1193  			return op
  1194  		}
  1195  	}
  1196  
  1197  	c.ctxt.Diag("illegal combination %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5))
  1198  	prasm(p)
  1199  	// Turn illegal instruction into an UNDEF, avoid crashing in asmout.
  1200  	return &Optab{obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, C_NONE, 49, 4, 0, 0}
  1201  }
  1202  
  1203  func cmp(a int, b int) bool {
  1204  	if a == b {
  1205  		return true
  1206  	}
  1207  	switch a {
  1208  	case C_DCON:
  1209  		return cmp(C_32CON, b) || cmp(C_DCON12_20S, b) || cmp(C_DCON32_12S, b) || b == C_DCON12_0
  1210  	case C_32CON:
  1211  		return cmp(C_32CON20_0, b) || cmp(C_U15CON, b) || cmp(C_13CON, b) || cmp(C_12CON, b)
  1212  	case C_32CON20_0:
  1213  		return b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_S13CON20_0 || b == C_ZCON
  1214  	case C_U15CON:
  1215  		return cmp(C_U12CON, b) || b == C_U15CON20_0 || b == C_U13CON20_0 || b == C_U13CON
  1216  	case C_13CON:
  1217  		return cmp(C_U13CON, b) || cmp(C_S13CON, b)
  1218  	case C_U13CON:
  1219  		return cmp(C_12CON, b) || b == C_U13CON20_0
  1220  	case C_S13CON:
  1221  		return cmp(C_12CON, b) || b == C_S13CON20_0
  1222  	case C_12CON:
  1223  		return cmp(C_U12CON, b) || cmp(C_S12CON, b)
  1224  	case C_UU12CON:
  1225  		return cmp(C_U12CON, b)
  1226  	case C_U12CON:
  1227  		return cmp(C_U8CON, b) || b == C_US12CON
  1228  	case C_U8CON:
  1229  		return cmp(C_U7CON, b)
  1230  	case C_U7CON:
  1231  		return cmp(C_U6CON, b)
  1232  	case C_U6CON:
  1233  		return cmp(C_U5CON, b)
  1234  	case C_U5CON:
  1235  		return cmp(C_U4CON, b)
  1236  	case C_U4CON:
  1237  		return cmp(C_U3CON, b)
  1238  	case C_U3CON:
  1239  		return cmp(C_U2CON, b)
  1240  	case C_U2CON:
  1241  		return cmp(C_U1CON, b)
  1242  	case C_U1CON:
  1243  		return cmp(C_ZCON, b)
  1244  	case C_US12CON:
  1245  		return cmp(C_S12CON, b)
  1246  	case C_S12CON:
  1247  		return cmp(C_S5CON, b) || cmp(C_U8CON, b) || b == C_US12CON
  1248  	case C_S5CON:
  1249  		return cmp(C_ZCON, b) || cmp(C_U4CON, b)
  1250  
  1251  	case C_DCON12_20S:
  1252  		if b == C_DCON20S_20 || b == C_DCON12_12S ||
  1253  			b == C_DCON20S_12S || b == C_DCON12_12U ||
  1254  			b == C_DCON20S_12U || b == C_DCON20S_0 {
  1255  			return true
  1256  		}
  1257  
  1258  	case C_DCON32_12S:
  1259  		if b == C_DCON32_20 || b == C_DCON12_32S ||
  1260  			b == C_DCON20S_32 || b == C_DCON32_12U ||
  1261  			b == C_DCON32_0 {
  1262  			return true
  1263  		}
  1264  
  1265  	case C_LACON:
  1266  		return b == C_SACON
  1267  
  1268  	case C_LAUTO:
  1269  		return b == C_SAUTO
  1270  
  1271  	case C_REG:
  1272  		return b == C_ZCON
  1273  
  1274  	case C_LOREG:
  1275  		return b == C_ZOREG || b == C_SOREG
  1276  
  1277  	case C_SOREG:
  1278  		return b == C_ZOREG
  1279  	}
  1280  
  1281  	return false
  1282  }
  1283  
  1284  func ocmp(p1, p2 Optab) int {
  1285  	if p1.as != p2.as {
  1286  		return int(p1.as) - int(p2.as)
  1287  	}
  1288  	if p1.from1 != p2.from1 {
  1289  		return int(p1.from1) - int(p2.from1)
  1290  	}
  1291  	if p1.reg != p2.reg {
  1292  		return int(p1.reg) - int(p2.reg)
  1293  	}
  1294  	if p1.to1 != p2.to1 {
  1295  		return int(p1.to1) - int(p2.to1)
  1296  	}
  1297  	return 0
  1298  }
  1299  
  1300  func opset(a, b0 obj.As) {
  1301  	oprange[a&obj.AMask] = oprange[b0]
  1302  }
  1303  
  1304  func buildop(ctxt *obj.Link) {
  1305  	if ctxt.DiagFunc == nil {
  1306  		ctxt.DiagFunc = func(format string, args ...interface{}) {
  1307  			log.Printf(format, args...)
  1308  		}
  1309  	}
  1310  
  1311  	if oprange[AOR&obj.AMask] != nil {
  1312  		// Already initialized; stop now.
  1313  		// This happens in the cmd/asm tests,
  1314  		// each of which re-initializes the arch.
  1315  		return
  1316  	}
  1317  
  1318  	for i := range C_NCLASS {
  1319  		for j := range C_NCLASS {
  1320  			if cmp(j, i) {
  1321  				xcmp[i][j] = true
  1322  			}
  1323  		}
  1324  	}
  1325  
  1326  	slices.SortFunc(optab, ocmp)
  1327  	for i := 0; i < len(optab); i++ {
  1328  		as, start := optab[i].as, i
  1329  		for ; i < len(optab)-1; i++ {
  1330  			if optab[i+1].as != as {
  1331  				break
  1332  			}
  1333  		}
  1334  		r0 := as & obj.AMask
  1335  		oprange[r0] = optab[start : i+1]
  1336  		switch as {
  1337  		default:
  1338  			ctxt.Diag("unknown op in build: %v", as)
  1339  			ctxt.DiagFlush()
  1340  			log.Fatalf("bad code")
  1341  
  1342  		case AABSF:
  1343  			opset(AMOVFD, r0)
  1344  			opset(AMOVDF, r0)
  1345  			opset(AMOVWF, r0)
  1346  			opset(AMOVFW, r0)
  1347  			opset(AMOVWD, r0)
  1348  			opset(AMOVDW, r0)
  1349  			opset(ANEGF, r0)
  1350  			opset(ANEGD, r0)
  1351  			opset(AABSD, r0)
  1352  			opset(ATRUNCDW, r0)
  1353  			opset(ATRUNCFW, r0)
  1354  			opset(ASQRTF, r0)
  1355  			opset(ASQRTD, r0)
  1356  			opset(AFCLASSF, r0)
  1357  			opset(AFCLASSD, r0)
  1358  			opset(AFLOGBF, r0)
  1359  			opset(AFLOGBD, r0)
  1360  
  1361  		case AMOVVF:
  1362  			opset(AMOVVD, r0)
  1363  			opset(AMOVFV, r0)
  1364  			opset(AMOVDV, r0)
  1365  			opset(ATRUNCDV, r0)
  1366  			opset(ATRUNCFV, r0)
  1367  			opset(AFFINTFW, r0)
  1368  			opset(AFFINTFV, r0)
  1369  			opset(AFFINTDW, r0)
  1370  			opset(AFFINTDV, r0)
  1371  			opset(AFTINTWF, r0)
  1372  			opset(AFTINTWD, r0)
  1373  			opset(AFTINTVF, r0)
  1374  			opset(AFTINTVD, r0)
  1375  			opset(AFTINTRPWF, r0)
  1376  			opset(AFTINTRPWD, r0)
  1377  			opset(AFTINTRPVF, r0)
  1378  			opset(AFTINTRPVD, r0)
  1379  			opset(AFTINTRMWF, r0)
  1380  			opset(AFTINTRMWD, r0)
  1381  			opset(AFTINTRMVF, r0)
  1382  			opset(AFTINTRMVD, r0)
  1383  			opset(AFTINTRZWF, r0)
  1384  			opset(AFTINTRZWD, r0)
  1385  			opset(AFTINTRZVF, r0)
  1386  			opset(AFTINTRZVD, r0)
  1387  			opset(AFTINTRNEWF, r0)
  1388  			opset(AFTINTRNEWD, r0)
  1389  			opset(AFTINTRNEVF, r0)
  1390  			opset(AFTINTRNEVD, r0)
  1391  
  1392  		case AADD:
  1393  			opset(ASGT, r0)
  1394  			opset(ASGTU, r0)
  1395  			opset(AADDU, r0)
  1396  
  1397  		case AADDV:
  1398  			opset(AADDVU, r0)
  1399  
  1400  		case AADDF:
  1401  			opset(ADIVF, r0)
  1402  			opset(ADIVD, r0)
  1403  			opset(AMULF, r0)
  1404  			opset(AMULD, r0)
  1405  			opset(ASUBF, r0)
  1406  			opset(ASUBD, r0)
  1407  			opset(AADDD, r0)
  1408  			opset(AFMINF, r0)
  1409  			opset(AFMIND, r0)
  1410  			opset(AFMAXF, r0)
  1411  			opset(AFMAXD, r0)
  1412  			opset(AFCOPYSGF, r0)
  1413  			opset(AFCOPYSGD, r0)
  1414  			opset(AFSCALEBF, r0)
  1415  			opset(AFSCALEBD, r0)
  1416  			opset(AFMAXAF, r0)
  1417  			opset(AFMAXAD, r0)
  1418  			opset(AFMINAF, r0)
  1419  			opset(AFMINAD, r0)
  1420  
  1421  		case AFMADDF:
  1422  			opset(AFMADDD, r0)
  1423  			opset(AFMSUBF, r0)
  1424  			opset(AFMSUBD, r0)
  1425  			opset(AFNMADDF, r0)
  1426  			opset(AFNMADDD, r0)
  1427  			opset(AFNMSUBF, r0)
  1428  			opset(AFNMSUBD, r0)
  1429  
  1430  		case AAND:
  1431  			opset(AOR, r0)
  1432  			opset(AXOR, r0)
  1433  			opset(AORN, r0)
  1434  			opset(AANDN, r0)
  1435  
  1436  		case ABEQ:
  1437  			opset(ABNE, r0)
  1438  			opset(ABLT, r0)
  1439  			opset(ABGE, r0)
  1440  			opset(ABGEU, r0)
  1441  			opset(ABLTU, r0)
  1442  
  1443  		case ABLEZ:
  1444  			opset(ABGEZ, r0)
  1445  			opset(ABLTZ, r0)
  1446  			opset(ABGTZ, r0)
  1447  
  1448  		case AMOVB:
  1449  			opset(AMOVH, r0)
  1450  
  1451  		case AMOVBU:
  1452  			opset(AMOVHU, r0)
  1453  
  1454  		case AMOVWP:
  1455  			opset(AMOVVP, r0)
  1456  
  1457  		case AMUL:
  1458  			opset(AMULU, r0)
  1459  			opset(AMULH, r0)
  1460  			opset(AMULHU, r0)
  1461  			opset(AREM, r0)
  1462  			opset(AREMU, r0)
  1463  			opset(ADIV, r0)
  1464  			opset(ADIVU, r0)
  1465  
  1466  		case AMULV:
  1467  			opset(AMULVU, r0)
  1468  			opset(AMULHV, r0)
  1469  			opset(AMULHVU, r0)
  1470  			opset(AREMV, r0)
  1471  			opset(AREMVU, r0)
  1472  			opset(ADIVV, r0)
  1473  			opset(ADIVVU, r0)
  1474  
  1475  		case ASLL:
  1476  			opset(ASRL, r0)
  1477  			opset(ASRA, r0)
  1478  			opset(AROTR, r0)
  1479  
  1480  		case ASLLV:
  1481  			opset(ASRAV, r0)
  1482  			opset(ASRLV, r0)
  1483  			opset(AROTRV, r0)
  1484  
  1485  		case ABSTRPICKW:
  1486  			opset(ABSTRPICKV, r0)
  1487  			opset(ABSTRINSW, r0)
  1488  			opset(ABSTRINSV, r0)
  1489  
  1490  		case ASUB:
  1491  			opset(ASUBU, r0)
  1492  			opset(ANOR, r0)
  1493  
  1494  		case ASUBV:
  1495  			opset(ASUBVU, r0)
  1496  
  1497  		case ASYSCALL:
  1498  			opset(ADBAR, r0)
  1499  			opset(ABREAK, r0)
  1500  
  1501  		case ACMPEQF:
  1502  			opset(ACMPGTF, r0)
  1503  			opset(ACMPGTD, r0)
  1504  			opset(ACMPGEF, r0)
  1505  			opset(ACMPGED, r0)
  1506  			opset(ACMPEQD, r0)
  1507  
  1508  		case ABFPT:
  1509  			opset(ABFPF, r0)
  1510  
  1511  		case AALSLV:
  1512  			opset(AALSLW, r0)
  1513  			opset(AALSLWU, r0)
  1514  
  1515  		case AMOVW,
  1516  			AMOVD,
  1517  			AMOVF,
  1518  			AMOVV,
  1519  			ARFE,
  1520  			AJAL,
  1521  			AJMP,
  1522  			AMOVWU,
  1523  			AVMOVQ,
  1524  			AXVMOVQ,
  1525  			ALL,
  1526  			ALLV,
  1527  			ASC,
  1528  			ASCV,
  1529  			ANEGW,
  1530  			ANEGV,
  1531  			AWORD,
  1532  			APRELD,
  1533  			APRELDX,
  1534  			AFSEL,
  1535  			AADDV16,
  1536  			obj.ANOP,
  1537  			obj.ATEXT,
  1538  			obj.AFUNCDATA,
  1539  			obj.APCALIGN,
  1540  			obj.APCDATA:
  1541  			break
  1542  
  1543  		case ARDTIMELW:
  1544  			opset(ARDTIMEHW, r0)
  1545  			opset(ARDTIMED, r0)
  1546  
  1547  		case ACLOW:
  1548  			opset(ACLZW, r0)
  1549  			opset(ACTOW, r0)
  1550  			opset(ACTZW, r0)
  1551  			opset(ACLOV, r0)
  1552  			opset(ACLZV, r0)
  1553  			opset(ACTOV, r0)
  1554  			opset(ACTZV, r0)
  1555  			opset(AREVB2H, r0)
  1556  			opset(AREVB4H, r0)
  1557  			opset(AREVB2W, r0)
  1558  			opset(AREVBV, r0)
  1559  			opset(AREVH2W, r0)
  1560  			opset(AREVHV, r0)
  1561  			opset(ABITREV4B, r0)
  1562  			opset(ABITREV8B, r0)
  1563  			opset(ABITREVW, r0)
  1564  			opset(ABITREVV, r0)
  1565  			opset(AEXTWB, r0)
  1566  			opset(AEXTWH, r0)
  1567  			opset(ACPUCFG, r0)
  1568  
  1569  		case ATEQ:
  1570  			opset(ATNE, r0)
  1571  
  1572  		case AMASKEQZ:
  1573  			opset(AMASKNEZ, r0)
  1574  			opset(ACRCWBW, r0)
  1575  			opset(ACRCWHW, r0)
  1576  			opset(ACRCWWW, r0)
  1577  			opset(ACRCWVW, r0)
  1578  			opset(ACRCCWBW, r0)
  1579  			opset(ACRCCWHW, r0)
  1580  			opset(ACRCCWWW, r0)
  1581  			opset(ACRCCWVW, r0)
  1582  
  1583  		case ANOOP:
  1584  			opset(obj.AUNDEF, r0)
  1585  
  1586  		case AAMSWAPW:
  1587  			for i := range atomicInst {
  1588  				if i == AAMSWAPW {
  1589  					continue
  1590  				}
  1591  				opset(i, r0)
  1592  			}
  1593  
  1594  		case AVSEQB:
  1595  			opset(AVSEQH, r0)
  1596  			opset(AVSEQW, r0)
  1597  			opset(AVSEQV, r0)
  1598  			opset(AVILVLB, r0)
  1599  			opset(AVILVLH, r0)
  1600  			opset(AVILVLW, r0)
  1601  			opset(AVILVLV, r0)
  1602  			opset(AVILVHB, r0)
  1603  			opset(AVILVHH, r0)
  1604  			opset(AVILVHW, r0)
  1605  			opset(AVILVHV, r0)
  1606  			opset(AVMULB, r0)
  1607  			opset(AVMULH, r0)
  1608  			opset(AVMULW, r0)
  1609  			opset(AVMULV, r0)
  1610  			opset(AVMUHB, r0)
  1611  			opset(AVMUHH, r0)
  1612  			opset(AVMUHW, r0)
  1613  			opset(AVMUHV, r0)
  1614  			opset(AVMUHBU, r0)
  1615  			opset(AVMUHHU, r0)
  1616  			opset(AVMUHWU, r0)
  1617  			opset(AVMUHVU, r0)
  1618  			opset(AVDIVB, r0)
  1619  			opset(AVDIVH, r0)
  1620  			opset(AVDIVW, r0)
  1621  			opset(AVDIVV, r0)
  1622  			opset(AVMODB, r0)
  1623  			opset(AVMODH, r0)
  1624  			opset(AVMODW, r0)
  1625  			opset(AVMODV, r0)
  1626  			opset(AVDIVBU, r0)
  1627  			opset(AVDIVHU, r0)
  1628  			opset(AVDIVWU, r0)
  1629  			opset(AVDIVVU, r0)
  1630  			opset(AVMODBU, r0)
  1631  			opset(AVMODHU, r0)
  1632  			opset(AVMODWU, r0)
  1633  			opset(AVMODVU, r0)
  1634  			opset(AVMULWEVHB, r0)
  1635  			opset(AVMULWEVWH, r0)
  1636  			opset(AVMULWEVVW, r0)
  1637  			opset(AVMULWEVQV, r0)
  1638  			opset(AVMULWODHB, r0)
  1639  			opset(AVMULWODWH, r0)
  1640  			opset(AVMULWODVW, r0)
  1641  			opset(AVMULWODQV, r0)
  1642  			opset(AVMULWEVHBU, r0)
  1643  			opset(AVMULWEVWHU, r0)
  1644  			opset(AVMULWEVVWU, r0)
  1645  			opset(AVMULWEVQVU, r0)
  1646  			opset(AVMULWODHBU, r0)
  1647  			opset(AVMULWODWHU, r0)
  1648  			opset(AVMULWODVWU, r0)
  1649  			opset(AVMULWODQVU, r0)
  1650  			opset(AVMULWEVHBUB, r0)
  1651  			opset(AVMULWEVWHUH, r0)
  1652  			opset(AVMULWEVVWUW, r0)
  1653  			opset(AVMULWEVQVUV, r0)
  1654  			opset(AVMULWODHBUB, r0)
  1655  			opset(AVMULWODWHUH, r0)
  1656  			opset(AVMULWODVWUW, r0)
  1657  			opset(AVMULWODQVUV, r0)
  1658  			opset(AVADDF, r0)
  1659  			opset(AVADDD, r0)
  1660  			opset(AVSUBF, r0)
  1661  			opset(AVSUBD, r0)
  1662  			opset(AVMULF, r0)
  1663  			opset(AVMULD, r0)
  1664  			opset(AVDIVF, r0)
  1665  			opset(AVDIVD, r0)
  1666  
  1667  		case AXVSEQB:
  1668  			opset(AXVSEQH, r0)
  1669  			opset(AXVSEQW, r0)
  1670  			opset(AXVSEQV, r0)
  1671  			opset(AXVILVLB, r0)
  1672  			opset(AXVILVLH, r0)
  1673  			opset(AXVILVLW, r0)
  1674  			opset(AXVILVLV, r0)
  1675  			opset(AXVILVHB, r0)
  1676  			opset(AXVILVHH, r0)
  1677  			opset(AXVILVHW, r0)
  1678  			opset(AXVILVHV, r0)
  1679  			opset(AXVMULB, r0)
  1680  			opset(AXVMULH, r0)
  1681  			opset(AXVMULW, r0)
  1682  			opset(AXVMULV, r0)
  1683  			opset(AXVMUHB, r0)
  1684  			opset(AXVMUHH, r0)
  1685  			opset(AXVMUHW, r0)
  1686  			opset(AXVMUHV, r0)
  1687  			opset(AXVMUHBU, r0)
  1688  			opset(AXVMUHHU, r0)
  1689  			opset(AXVMUHWU, r0)
  1690  			opset(AXVMUHVU, r0)
  1691  			opset(AXVDIVB, r0)
  1692  			opset(AXVDIVH, r0)
  1693  			opset(AXVDIVW, r0)
  1694  			opset(AXVDIVV, r0)
  1695  			opset(AXVMODB, r0)
  1696  			opset(AXVMODH, r0)
  1697  			opset(AXVMODW, r0)
  1698  			opset(AXVMODV, r0)
  1699  			opset(AXVDIVBU, r0)
  1700  			opset(AXVDIVHU, r0)
  1701  			opset(AXVDIVWU, r0)
  1702  			opset(AXVDIVVU, r0)
  1703  			opset(AXVMODBU, r0)
  1704  			opset(AXVMODHU, r0)
  1705  			opset(AXVMODWU, r0)
  1706  			opset(AXVMODVU, r0)
  1707  			opset(AXVMULWEVHB, r0)
  1708  			opset(AXVMULWEVWH, r0)
  1709  			opset(AXVMULWEVVW, r0)
  1710  			opset(AXVMULWEVQV, r0)
  1711  			opset(AXVMULWODHB, r0)
  1712  			opset(AXVMULWODWH, r0)
  1713  			opset(AXVMULWODVW, r0)
  1714  			opset(AXVMULWODQV, r0)
  1715  			opset(AXVMULWEVHBU, r0)
  1716  			opset(AXVMULWEVWHU, r0)
  1717  			opset(AXVMULWEVVWU, r0)
  1718  			opset(AXVMULWEVQVU, r0)
  1719  			opset(AXVMULWODHBU, r0)
  1720  			opset(AXVMULWODWHU, r0)
  1721  			opset(AXVMULWODVWU, r0)
  1722  			opset(AXVMULWODQVU, r0)
  1723  			opset(AXVMULWEVHBUB, r0)
  1724  			opset(AXVMULWEVWHUH, r0)
  1725  			opset(AXVMULWEVVWUW, r0)
  1726  			opset(AXVMULWEVQVUV, r0)
  1727  			opset(AXVMULWODHBUB, r0)
  1728  			opset(AXVMULWODWHUH, r0)
  1729  			opset(AXVMULWODVWUW, r0)
  1730  			opset(AXVMULWODQVUV, r0)
  1731  			opset(AXVADDF, r0)
  1732  			opset(AXVADDD, r0)
  1733  			opset(AXVSUBF, r0)
  1734  			opset(AXVSUBD, r0)
  1735  			opset(AXVMULF, r0)
  1736  			opset(AXVMULD, r0)
  1737  			opset(AXVDIVF, r0)
  1738  			opset(AXVDIVD, r0)
  1739  
  1740  		case AVANDB:
  1741  			opset(AVORB, r0)
  1742  			opset(AVXORB, r0)
  1743  			opset(AVNORB, r0)
  1744  			opset(AVSHUF4IB, r0)
  1745  			opset(AVSHUF4IH, r0)
  1746  			opset(AVSHUF4IW, r0)
  1747  			opset(AVSHUF4IV, r0)
  1748  
  1749  		case AXVANDB:
  1750  			opset(AXVORB, r0)
  1751  			opset(AXVXORB, r0)
  1752  			opset(AXVNORB, r0)
  1753  			opset(AXVSHUF4IB, r0)
  1754  			opset(AXVSHUF4IH, r0)
  1755  			opset(AXVSHUF4IW, r0)
  1756  			opset(AXVSHUF4IV, r0)
  1757  
  1758  		case AVANDV:
  1759  			opset(AVORV, r0)
  1760  			opset(AVXORV, r0)
  1761  			opset(AVNORV, r0)
  1762  			opset(AVANDNV, r0)
  1763  			opset(AVORNV, r0)
  1764  
  1765  		case AXVANDV:
  1766  			opset(AXVORV, r0)
  1767  			opset(AXVXORV, r0)
  1768  			opset(AXVNORV, r0)
  1769  			opset(AXVANDNV, r0)
  1770  			opset(AXVORNV, r0)
  1771  
  1772  		case AVPCNTB:
  1773  			opset(AVPCNTH, r0)
  1774  			opset(AVPCNTW, r0)
  1775  			opset(AVPCNTV, r0)
  1776  			opset(AVFSQRTF, r0)
  1777  			opset(AVFSQRTD, r0)
  1778  			opset(AVFRECIPF, r0)
  1779  			opset(AVFRECIPD, r0)
  1780  			opset(AVFRSQRTF, r0)
  1781  			opset(AVFRSQRTD, r0)
  1782  			opset(AVNEGB, r0)
  1783  			opset(AVNEGH, r0)
  1784  			opset(AVNEGW, r0)
  1785  			opset(AVNEGV, r0)
  1786  			opset(AVFRINTRNEF, r0)
  1787  			opset(AVFRINTRNED, r0)
  1788  			opset(AVFRINTRZF, r0)
  1789  			opset(AVFRINTRZD, r0)
  1790  			opset(AVFRINTRPF, r0)
  1791  			opset(AVFRINTRPD, r0)
  1792  			opset(AVFRINTRMF, r0)
  1793  			opset(AVFRINTRMD, r0)
  1794  			opset(AVFRINTF, r0)
  1795  			opset(AVFRINTD, r0)
  1796  			opset(AVFCLASSF, r0)
  1797  			opset(AVFCLASSD, r0)
  1798  
  1799  		case AXVPCNTB:
  1800  			opset(AXVPCNTH, r0)
  1801  			opset(AXVPCNTW, r0)
  1802  			opset(AXVPCNTV, r0)
  1803  			opset(AXVFSQRTF, r0)
  1804  			opset(AXVFSQRTD, r0)
  1805  			opset(AXVFRECIPF, r0)
  1806  			opset(AXVFRECIPD, r0)
  1807  			opset(AXVFRSQRTF, r0)
  1808  			opset(AXVFRSQRTD, r0)
  1809  			opset(AXVNEGB, r0)
  1810  			opset(AXVNEGH, r0)
  1811  			opset(AXVNEGW, r0)
  1812  			opset(AXVNEGV, r0)
  1813  			opset(AXVFRINTRNEF, r0)
  1814  			opset(AXVFRINTRNED, r0)
  1815  			opset(AXVFRINTRZF, r0)
  1816  			opset(AXVFRINTRZD, r0)
  1817  			opset(AXVFRINTRPF, r0)
  1818  			opset(AXVFRINTRPD, r0)
  1819  			opset(AXVFRINTRMF, r0)
  1820  			opset(AXVFRINTRMD, r0)
  1821  			opset(AXVFRINTF, r0)
  1822  			opset(AXVFRINTD, r0)
  1823  			opset(AXVFCLASSF, r0)
  1824  			opset(AXVFCLASSD, r0)
  1825  
  1826  		case AVADDB:
  1827  			opset(AVADDH, r0)
  1828  			opset(AVADDW, r0)
  1829  			opset(AVADDV, r0)
  1830  			opset(AVADDQ, r0)
  1831  			opset(AVSUBB, r0)
  1832  			opset(AVSUBH, r0)
  1833  			opset(AVSUBW, r0)
  1834  			opset(AVSUBV, r0)
  1835  			opset(AVSUBQ, r0)
  1836  
  1837  		case AXVADDB:
  1838  			opset(AXVADDH, r0)
  1839  			opset(AXVADDW, r0)
  1840  			opset(AXVADDV, r0)
  1841  			opset(AXVADDQ, r0)
  1842  			opset(AXVSUBB, r0)
  1843  			opset(AXVSUBH, r0)
  1844  			opset(AXVSUBW, r0)
  1845  			opset(AXVSUBV, r0)
  1846  			opset(AXVSUBQ, r0)
  1847  
  1848  		case AVSLLB:
  1849  			opset(AVSRLB, r0)
  1850  			opset(AVSRAB, r0)
  1851  			opset(AVROTRB, r0)
  1852  			opset(AVBITCLRB, r0)
  1853  			opset(AVBITSETB, r0)
  1854  			opset(AVBITREVB, r0)
  1855  
  1856  		case AXVSLLB:
  1857  			opset(AXVSRLB, r0)
  1858  			opset(AXVSRAB, r0)
  1859  			opset(AXVROTRB, r0)
  1860  			opset(AXVBITCLRB, r0)
  1861  			opset(AXVBITSETB, r0)
  1862  			opset(AXVBITREVB, r0)
  1863  
  1864  		case AVSLLH:
  1865  			opset(AVSRLH, r0)
  1866  			opset(AVSRAH, r0)
  1867  			opset(AVROTRH, r0)
  1868  			opset(AVBITCLRH, r0)
  1869  			opset(AVBITSETH, r0)
  1870  			opset(AVBITREVH, r0)
  1871  
  1872  		case AXVSLLH:
  1873  			opset(AXVSRLH, r0)
  1874  			opset(AXVSRAH, r0)
  1875  			opset(AXVROTRH, r0)
  1876  			opset(AXVBITCLRH, r0)
  1877  			opset(AXVBITSETH, r0)
  1878  			opset(AXVBITREVH, r0)
  1879  
  1880  		case AVSLLW:
  1881  			opset(AVSRLW, r0)
  1882  			opset(AVSRAW, r0)
  1883  			opset(AVROTRW, r0)
  1884  			opset(AVADDBU, r0)
  1885  			opset(AVADDHU, r0)
  1886  			opset(AVADDWU, r0)
  1887  			opset(AVADDVU, r0)
  1888  			opset(AVSUBBU, r0)
  1889  			opset(AVSUBHU, r0)
  1890  			opset(AVSUBWU, r0)
  1891  			opset(AVSUBVU, r0)
  1892  			opset(AVBITCLRW, r0)
  1893  			opset(AVBITSETW, r0)
  1894  			opset(AVBITREVW, r0)
  1895  
  1896  		case AXVSLLW:
  1897  			opset(AXVSRLW, r0)
  1898  			opset(AXVSRAW, r0)
  1899  			opset(AXVROTRW, r0)
  1900  			opset(AXVADDBU, r0)
  1901  			opset(AXVADDHU, r0)
  1902  			opset(AXVADDWU, r0)
  1903  			opset(AXVADDVU, r0)
  1904  			opset(AXVSUBBU, r0)
  1905  			opset(AXVSUBHU, r0)
  1906  			opset(AXVSUBWU, r0)
  1907  			opset(AXVSUBVU, r0)
  1908  			opset(AXVBITCLRW, r0)
  1909  			opset(AXVBITSETW, r0)
  1910  			opset(AXVBITREVW, r0)
  1911  
  1912  		case AVSLLV:
  1913  			opset(AVSRLV, r0)
  1914  			opset(AVSRAV, r0)
  1915  			opset(AVROTRV, r0)
  1916  			opset(AVBITCLRV, r0)
  1917  			opset(AVBITSETV, r0)
  1918  			opset(AVBITREVV, r0)
  1919  
  1920  		case AXVSLLV:
  1921  			opset(AXVSRLV, r0)
  1922  			opset(AXVSRAV, r0)
  1923  			opset(AXVROTRV, r0)
  1924  			opset(AXVBITCLRV, r0)
  1925  			opset(AXVBITSETV, r0)
  1926  			opset(AXVBITREVV, r0)
  1927  
  1928  		case AVSETEQV:
  1929  			opset(AVSETNEV, r0)
  1930  			opset(AVSETANYEQB, r0)
  1931  			opset(AVSETANYEQH, r0)
  1932  			opset(AVSETANYEQW, r0)
  1933  			opset(AVSETANYEQV, r0)
  1934  			opset(AVSETALLNEB, r0)
  1935  			opset(AVSETALLNEH, r0)
  1936  			opset(AVSETALLNEW, r0)
  1937  			opset(AVSETALLNEV, r0)
  1938  
  1939  		case AXVSETEQV:
  1940  			opset(AXVSETNEV, r0)
  1941  			opset(AXVSETANYEQB, r0)
  1942  			opset(AXVSETANYEQH, r0)
  1943  			opset(AXVSETANYEQW, r0)
  1944  			opset(AXVSETANYEQV, r0)
  1945  			opset(AXVSETALLNEB, r0)
  1946  			opset(AXVSETALLNEH, r0)
  1947  			opset(AXVSETALLNEW, r0)
  1948  			opset(AXVSETALLNEV, r0)
  1949  
  1950  		}
  1951  	}
  1952  }
  1953  
  1954  func OP_RRRR(op uint32, r1 uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
  1955  	return op | (r1&0x1F)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4 & 0x1F)
  1956  }
  1957  
  1958  // r1 -> rk
  1959  // r2 -> rj
  1960  // r3 -> rd
  1961  func OP_RRR(op uint32, r1 uint32, r2 uint32, r3 uint32) uint32 {
  1962  	return op | (r1&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1963  }
  1964  
  1965  // r2 -> rj
  1966  // r3 -> rd
  1967  func OP_RR(op uint32, r2 uint32, r3 uint32) uint32 {
  1968  	return op | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1969  }
  1970  
  1971  func OP_2IRRR(op uint32, i uint32, r2 uint32, r3 uint32, r4 uint32) uint32 {
  1972  	return op | (i&0x3)<<15 | (r2&0x1F)<<10 | (r3&0x1F)<<5 | (r4&0x1F)<<0
  1973  }
  1974  
  1975  func OP_16IR_5I(op uint32, i uint32, r2 uint32) uint32 {
  1976  	return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | ((i >> 16) & 0x1F)
  1977  }
  1978  
  1979  func OP_16IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1980  	return op | (i&0xFFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1981  }
  1982  
  1983  func OP_14IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1984  	return op | (i&0x3FFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1985  }
  1986  
  1987  func OP_12IR_5I(op uint32, i1 uint32, r2 uint32, i2 uint32) uint32 {
  1988  	return op | (i1&0xFFF)<<10 | (r2&0x1F)<<5 | (i2&0x1F)<<0
  1989  }
  1990  
  1991  func OP_12IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1992  	return op | (i&0xFFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1993  }
  1994  
  1995  func OP_11IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  1996  	return op | (i&0x7FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  1997  }
  1998  
  1999  func OP_10IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  2000  	return op | (i&0x3FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  2001  }
  2002  
  2003  func OP_9IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  2004  	return op | (i&0x1FF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  2005  }
  2006  
  2007  func OP_8IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  2008  	return op | (i&0xFF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  2009  }
  2010  
  2011  func OP_6IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  2012  	return op | (i&0x3F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  2013  }
  2014  
  2015  func OP_5IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  2016  	return op | (i&0x1F)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  2017  }
  2018  
  2019  func OP_4IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  2020  	return op | (i&0xF)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  2021  }
  2022  
  2023  func OP_3IRR(op uint32, i uint32, r2 uint32, r3 uint32) uint32 {
  2024  	return op | (i&0x7)<<10 | (r2&0x1F)<<5 | (r3&0x1F)<<0
  2025  }
  2026  
  2027  func OP_IR(op uint32, i uint32, r2 uint32) uint32 {
  2028  	return op | (i&0xFFFFF)<<5 | (r2&0x1F)<<0 // ui20, rd5
  2029  }
  2030  
  2031  func OP_15I(op uint32, i uint32) uint32 {
  2032  	return op | (i&0x7FFF)<<0
  2033  }
  2034  
  2035  // i1 -> msb
  2036  // r2 -> rj
  2037  // i3 -> lsb
  2038  // r4 -> rd
  2039  func OP_IRIR(op uint32, i1 uint32, r2 uint32, i3 uint32, r4 uint32) uint32 {
  2040  	return op | (i1 << 16) | (r2&0x1F)<<5 | (i3 << 10) | (r4&0x1F)<<0
  2041  }
  2042  
  2043  // Encoding for the 'b' or 'bl' instruction.
  2044  func OP_B_BL(op uint32, i uint32) uint32 {
  2045  	return op | ((i & 0xFFFF) << 10) | ((i >> 16) & 0x3FF)
  2046  }
  2047  
  2048  func (c *ctxt0) asmout(p *obj.Prog, o *Optab, out []uint32) {
  2049  	o1 := uint32(0)
  2050  	o2 := uint32(0)
  2051  	o3 := uint32(0)
  2052  	o4 := uint32(0)
  2053  	o5 := uint32(0)
  2054  
  2055  	add := AADDU
  2056  	add = AADDVU
  2057  
  2058  	switch o.type_ {
  2059  	default:
  2060  		c.ctxt.Diag("unknown type %d", o.type_)
  2061  		prasm(p)
  2062  
  2063  	case 0: // pseudo ops
  2064  		break
  2065  
  2066  	case 1: // mov r1,r2 ==> OR r1,r0,r2
  2067  		a := AOR
  2068  		if p.As == AMOVW {
  2069  			a = ASLL
  2070  		}
  2071  		o1 = OP_RRR(c.oprrr(a), uint32(REGZERO), uint32(p.From.Reg), uint32(p.To.Reg))
  2072  
  2073  	case 2: // add/sub r1,[r2],r3
  2074  		r := int(p.Reg)
  2075  		if p.As == ANEGW || p.As == ANEGV {
  2076  			r = REGZERO
  2077  		}
  2078  		if r == 0 {
  2079  			r = int(p.To.Reg)
  2080  		}
  2081  		o1 = OP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(r), uint32(p.To.Reg))
  2082  
  2083  	case 3: // mov $soreg, r ==> or/add $i,o,r
  2084  		v := c.regoff(&p.From)
  2085  
  2086  		r := int(p.From.Reg)
  2087  		if r == 0 {
  2088  			r = int(o.param)
  2089  		}
  2090  		a := add
  2091  		if o.from1 == C_12CON && v > 0 {
  2092  			a = AOR
  2093  		}
  2094  
  2095  		o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(r), uint32(p.To.Reg))
  2096  
  2097  	case 4: // add $scon,[r1],r2
  2098  		v := c.regoff(&p.From)
  2099  		r := int(p.Reg)
  2100  		if r == 0 {
  2101  			r = int(p.To.Reg)
  2102  		}
  2103  		if p.As == AADDV16 {
  2104  			if v&65535 != 0 {
  2105  				c.ctxt.Diag("%v: the constant must be a multiple of 65536.\n", p)
  2106  			}
  2107  			o1 = OP_16IRR(c.opirr(p.As), uint32(v>>16), uint32(r), uint32(p.To.Reg))
  2108  		} else {
  2109  			o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2110  		}
  2111  
  2112  	case 5: // syscall
  2113  		v := c.regoff(&p.From)
  2114  		o1 = OP_15I(c.opi(p.As), uint32(v))
  2115  
  2116  	case 6: // beq r1,[r2],sbra
  2117  		v := int32(0)
  2118  		if p.To.Target() != nil {
  2119  			v = int32(p.To.Target().Pc-p.Pc) >> 2
  2120  		}
  2121  		as, rd, rj, width := p.As, p.Reg, p.From.Reg, 16
  2122  		switch as {
  2123  		case ABGTZ, ABLEZ:
  2124  			rd, rj = rj, rd
  2125  		case ABFPT, ABFPF:
  2126  			width = 21
  2127  			// FCC0 is the implicit source operand, now that we
  2128  			// don't register-allocate from the FCC bank.
  2129  			if rj == 0 {
  2130  				rj = REG_FCC0
  2131  			}
  2132  		case ABEQ, ABNE:
  2133  			if rd == 0 || rd == REGZERO || rj == REGZERO {
  2134  				// BEQZ/BNEZ can be encoded with 21-bit offsets.
  2135  				width = 21
  2136  				as = -as
  2137  				if rj == 0 || rj == REGZERO {
  2138  					rj = rd
  2139  				}
  2140  			}
  2141  		}
  2142  		switch width {
  2143  		case 21:
  2144  			if (v<<11)>>11 != v {
  2145  				c.ctxt.Diag("21 bit-width, short branch too far\n%v", p)
  2146  			}
  2147  			o1 = OP_16IR_5I(c.opirr(as), uint32(v), uint32(rj))
  2148  		case 16:
  2149  			if (v<<16)>>16 != v {
  2150  				c.ctxt.Diag("16 bit-width, short branch too far\n%v", p)
  2151  			}
  2152  			o1 = OP_16IRR(c.opirr(as), uint32(v), uint32(rj), uint32(rd))
  2153  		default:
  2154  			c.ctxt.Diag("unexpected branch encoding\n%v", p)
  2155  		}
  2156  
  2157  	case 7: // mov r, soreg
  2158  		r := int(p.To.Reg)
  2159  		if r == 0 {
  2160  			r = int(o.param)
  2161  		}
  2162  		v := c.regoff(&p.To)
  2163  		o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
  2164  
  2165  	case 8: // mov soreg, r
  2166  		r := int(p.From.Reg)
  2167  		if r == 0 {
  2168  			r = int(o.param)
  2169  		}
  2170  		v := c.regoff(&p.From)
  2171  		o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2172  
  2173  	case 9: // sll r1,[r2],r3
  2174  		o1 = OP_RR(c.oprr(p.As), uint32(p.From.Reg), uint32(p.To.Reg))
  2175  
  2176  	case 10: // add $con,[r1],r2 ==> mov $con, t; add t,[r1],r2
  2177  		v := c.regoff(&p.From)
  2178  		a := AOR
  2179  		if v < 0 {
  2180  			a = AADDU
  2181  		}
  2182  		o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
  2183  		r := int(p.Reg)
  2184  		if r == 0 {
  2185  			r = int(p.To.Reg)
  2186  		}
  2187  		o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2188  
  2189  	case 11: // jmp lbra
  2190  		v := int32(0)
  2191  		if p.To.Target() != nil {
  2192  			v = int32(p.To.Target().Pc-p.Pc) >> 2
  2193  		}
  2194  		o1 = OP_B_BL(c.opirr(p.As), uint32(v))
  2195  		if p.To.Sym != nil {
  2196  			c.cursym.AddRel(c.ctxt, obj.Reloc{
  2197  				Type: objabi.R_CALLLOONG64,
  2198  				Off:  int32(c.pc),
  2199  				Siz:  4,
  2200  				Sym:  p.To.Sym,
  2201  				Add:  p.To.Offset,
  2202  			})
  2203  		}
  2204  
  2205  	case 12: // movbs r,r
  2206  		switch p.As {
  2207  		case AMOVB:
  2208  			o1 = OP_RR(c.oprr(AEXTWB), uint32(p.From.Reg), uint32(p.To.Reg))
  2209  		case AMOVH:
  2210  			o1 = OP_RR(c.oprr(AEXTWH), uint32(p.From.Reg), uint32(p.To.Reg))
  2211  		case AMOVBU:
  2212  			o1 = OP_12IRR(c.opirr(AAND), uint32(0xff), uint32(p.From.Reg), uint32(p.To.Reg))
  2213  		case AMOVHU:
  2214  			o1 = OP_IRIR(c.opirir(ABSTRPICKV), 15, uint32(p.From.Reg), 0, uint32(p.To.Reg))
  2215  		case AMOVWU:
  2216  			o1 = OP_IRIR(c.opirir(ABSTRPICKV), 31, uint32(p.From.Reg), 0, uint32(p.To.Reg))
  2217  		default:
  2218  			c.ctxt.Diag("unexpected encoding\n%v", p)
  2219  		}
  2220  
  2221  	case 13: // vsll $ui3, [vr1], vr2
  2222  		v := c.regoff(&p.From)
  2223  		r := int(p.Reg)
  2224  		if r == 0 {
  2225  			r = int(p.To.Reg)
  2226  		}
  2227  		o1 = OP_3IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2228  
  2229  	case 14: // vsll $ui4, [vr1], vr2
  2230  		v := c.regoff(&p.From)
  2231  		r := int(p.Reg)
  2232  		if r == 0 {
  2233  			r = int(p.To.Reg)
  2234  		}
  2235  		o1 = OP_4IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2236  
  2237  	case 15: // teq $c r,r
  2238  		v := c.regoff(&p.From)
  2239  		r := int(p.Reg)
  2240  		if r == 0 {
  2241  			r = REGZERO
  2242  		}
  2243  		/*
  2244  			teq c, r1, r2
  2245  			fallthrough
  2246  			==>
  2247  			bne r1, r2, 2
  2248  			break c
  2249  			fallthrough
  2250  		*/
  2251  		if p.As == ATEQ {
  2252  			o1 = OP_16IRR(c.opirr(ABNE), uint32(2), uint32(r), uint32(p.To.Reg))
  2253  		} else { // ATNE
  2254  			o1 = OP_16IRR(c.opirr(ABEQ), uint32(2), uint32(r), uint32(p.To.Reg))
  2255  		}
  2256  		o2 = OP_15I(c.opi(ABREAK), uint32(v))
  2257  
  2258  	case 16: // sll $c,[r1],r2
  2259  		v := c.regoff(&p.From)
  2260  		r := int(p.Reg)
  2261  		if r == 0 {
  2262  			r = int(p.To.Reg)
  2263  		}
  2264  
  2265  		// instruction ending with V:6-digit immediate, others:5-digit immediate
  2266  		if v >= 32 && vshift(p.As) {
  2267  			o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x3f, uint32(r), uint32(p.To.Reg))
  2268  		} else {
  2269  			o1 = OP_16IRR(c.opirr(p.As), uint32(v)&0x1f, uint32(r), uint32(p.To.Reg))
  2270  		}
  2271  
  2272  	case 17: // bstrpickw $msbw, r1, $lsbw, r2
  2273  		rd, rj := p.To.Reg, p.Reg
  2274  		if rj == obj.REG_NONE {
  2275  			rj = rd
  2276  		}
  2277  		msb, lsb := p.From.Offset, p.GetFrom3().Offset
  2278  
  2279  		// check the range of msb and lsb
  2280  		var b uint32
  2281  		if p.As == ABSTRPICKW || p.As == ABSTRINSW {
  2282  			b = 32
  2283  		} else {
  2284  			b = 64
  2285  		}
  2286  		if lsb < 0 || uint32(lsb) >= b || msb < 0 || uint32(msb) >= b || uint32(lsb) > uint32(msb) {
  2287  			c.ctxt.Diag("illegal bit number\n%v", p)
  2288  		}
  2289  
  2290  		o1 = OP_IRIR(c.opirir(p.As), uint32(msb), uint32(rj), uint32(lsb), uint32(rd))
  2291  
  2292  	case 18: // jmp [r1],0(r2)
  2293  		r := int(p.Reg)
  2294  		if r == 0 {
  2295  			r = int(o.param)
  2296  		}
  2297  		o1 = OP_RRR(c.oprrr(p.As), uint32(0), uint32(p.To.Reg), uint32(r))
  2298  		if p.As == obj.ACALL {
  2299  			c.cursym.AddRel(c.ctxt, obj.Reloc{
  2300  				Type: objabi.R_CALLIND,
  2301  				Off:  int32(c.pc),
  2302  			})
  2303  		}
  2304  
  2305  	case 19: // mov $lcon,r
  2306  		// NOTE: this case does not use REGTMP. If it ever does,
  2307  		// remove the NOTUSETMP flag in optab.
  2308  		v := c.regoff(&p.From)
  2309  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2310  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
  2311  
  2312  	case 20: // mov Rsrc, (Rbase)(Roff)
  2313  		o1 = OP_RRR(c.oprrr(p.As), uint32(p.To.Index), uint32(p.To.Reg), uint32(p.From.Reg))
  2314  
  2315  	case 21: // mov (Rbase)(Roff), Rdst
  2316  		o1 = OP_RRR(c.oprrr(-p.As), uint32(p.From.Index), uint32(p.From.Reg), uint32(p.To.Reg))
  2317  
  2318  	case 22: // add $si5,[r1],r2
  2319  		v := c.regoff(&p.From)
  2320  		r := int(p.Reg)
  2321  		if r == 0 {
  2322  			r = int(p.To.Reg)
  2323  		}
  2324  
  2325  		o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2326  
  2327  	case 23: // add $ui8,[r1],r2
  2328  		v := c.regoff(&p.From)
  2329  		r := int(p.Reg)
  2330  		if r == 0 {
  2331  			r = int(p.To.Reg)
  2332  		}
  2333  
  2334  		// the operand range available for instructions VSHUF4IV and XVSHUF4IV is [0, 15]
  2335  		if p.As == AVSHUF4IV || p.As == AXVSHUF4IV {
  2336  			operand := uint32(v)
  2337  			c.checkoperand(p, operand, 15)
  2338  		}
  2339  
  2340  		o1 = OP_8IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2341  
  2342  	case 24: // add $lcon,r1,r2
  2343  		v := c.regoff(&p.From)
  2344  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2345  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2346  		r := int(p.Reg)
  2347  		if r == 0 {
  2348  			r = int(p.To.Reg)
  2349  		}
  2350  		o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2351  
  2352  	case 25: // mov $ucon,r
  2353  		v := c.regoff(&p.From)
  2354  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2355  
  2356  	case 26: // add/and $ucon,[r1],r2
  2357  		v := c.regoff(&p.From)
  2358  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2359  		r := int(p.Reg)
  2360  		if r == 0 {
  2361  			r = int(p.To.Reg)
  2362  		}
  2363  		o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2364  
  2365  	case 27: // mov $lsext/auto/oreg,r
  2366  		v := c.regoff(&p.From)
  2367  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2368  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2369  		r := int(p.From.Reg)
  2370  		if r == 0 {
  2371  			r = int(o.param)
  2372  		}
  2373  		o3 = OP_RRR(c.oprrr(add), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2374  
  2375  	case 28: // mov [sl]ext/auto/oreg,fr
  2376  		v := c.regoff(&p.From)
  2377  		r := int(p.From.Reg)
  2378  		if r == 0 {
  2379  			r = int(o.param)
  2380  		}
  2381  		switch o.size {
  2382  		case 12:
  2383  			o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
  2384  			o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
  2385  			o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
  2386  
  2387  		case 4:
  2388  			o1 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2389  		}
  2390  
  2391  	case 29: // mov fr,[sl]ext/auto/oreg
  2392  		v := c.regoff(&p.To)
  2393  		r := int(p.To.Reg)
  2394  		if r == 0 {
  2395  			r = int(o.param)
  2396  		}
  2397  		switch o.size {
  2398  		case 12:
  2399  			o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
  2400  			o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
  2401  			o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
  2402  
  2403  		case 4:
  2404  			o1 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.From.Reg))
  2405  		}
  2406  
  2407  	case 30: // mov gr/fr/fcc/fcsr, fr/fcc/fcsr/gr
  2408  		a := c.specialFpMovInst(p.As, oclass(&p.From), oclass(&p.To))
  2409  		o1 = OP_RR(a, uint32(p.From.Reg), uint32(p.To.Reg))
  2410  
  2411  	case 31: // vsll $ui5, [vr1], vr2
  2412  		v := c.regoff(&p.From)
  2413  		r := int(p.Reg)
  2414  		if r == 0 {
  2415  			r = int(p.To.Reg)
  2416  		}
  2417  		o1 = OP_5IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2418  
  2419  	case 32: // vsll $ui6, [vr1], vr2
  2420  		v := c.regoff(&p.From)
  2421  		r := int(p.Reg)
  2422  		if r == 0 {
  2423  			r = int(p.To.Reg)
  2424  		}
  2425  		o1 = OP_6IRR(c.opirr(p.As), uint32(v), uint32(r), uint32(p.To.Reg))
  2426  
  2427  	case 33: // fsel ca, fk, [fj], fd
  2428  		ca := uint32(p.From.Reg)
  2429  		fk := uint32(p.Reg)
  2430  		fd := uint32(p.To.Reg)
  2431  		fj := fd
  2432  		if len(p.RestArgs) > 0 {
  2433  			fj = uint32(p.GetFrom3().Reg)
  2434  		}
  2435  		o1 = 0x340<<18 | (ca&0x7)<<15 | (fk&0x1F)<<10 | (fj&0x1F)<<5 | (fd & 0x1F)
  2436  
  2437  	case 34: // mov $con,fr
  2438  		v := c.regoff(&p.From)
  2439  		a := AADDU
  2440  		if v > 0 {
  2441  			a = AOR
  2442  		}
  2443  		a2 := c.specialFpMovInst(p.As, C_REG, oclass(&p.To))
  2444  		o1 = OP_12IRR(c.opirr(a), uint32(v), uint32(0), uint32(REGTMP))
  2445  		o2 = OP_RR(a2, uint32(REGTMP), uint32(p.To.Reg))
  2446  
  2447  	case 35: // mov r,lext/auto/oreg
  2448  		v := c.regoff(&p.To)
  2449  		r := int(p.To.Reg)
  2450  		if r == 0 {
  2451  			r = int(o.param)
  2452  		}
  2453  		o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
  2454  		o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
  2455  		o3 = OP_12IRR(c.opirr(p.As), uint32(v), uint32(REGTMP), uint32(p.From.Reg))
  2456  
  2457  	case 36: // mov lext/auto/oreg,r
  2458  		v := c.regoff(&p.From)
  2459  		r := int(p.From.Reg)
  2460  		if r == 0 {
  2461  			r = int(o.param)
  2462  		}
  2463  		o1 = OP_IR(c.opir(ALU12IW), uint32((v+1<<11)>>12), uint32(REGTMP))
  2464  		o2 = OP_RRR(c.oprrr(add), uint32(r), uint32(REGTMP), uint32(REGTMP))
  2465  		o3 = OP_12IRR(c.opirr(-p.As), uint32(v), uint32(REGTMP), uint32(p.To.Reg))
  2466  
  2467  	case 37: // fmadd r1, r2, [r3], r4
  2468  		r := int(p.To.Reg)
  2469  		if len(p.RestArgs) > 0 {
  2470  			r = int(p.GetFrom3().Reg)
  2471  		}
  2472  		o1 = OP_RRRR(c.oprrrr(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(r), uint32(p.To.Reg))
  2473  
  2474  	case 38: // word
  2475  		o1 = uint32(c.regoff(&p.From))
  2476  
  2477  	case 39: // vmov Rn, Vd.<T>[index]
  2478  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
  2479  		if v == 0 {
  2480  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2481  		}
  2482  
  2483  		Rj := uint32(p.From.Reg & EXT_REG_MASK)
  2484  		Vd := uint32(p.To.Reg & EXT_REG_MASK)
  2485  		index := uint32(p.To.Index)
  2486  		c.checkindex(p, index, m)
  2487  		o1 = v | (index << 10) | (Rj << 5) | Vd
  2488  
  2489  	case 40: // vmov Vd.<T>[index], Rn
  2490  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
  2491  		if v == 0 {
  2492  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2493  		}
  2494  
  2495  		Vj := uint32(p.From.Reg & EXT_REG_MASK)
  2496  		Rd := uint32(p.To.Reg & EXT_REG_MASK)
  2497  		index := uint32(p.From.Index)
  2498  		c.checkindex(p, index, m)
  2499  		o1 = v | (index << 10) | (Vj << 5) | Rd
  2500  
  2501  	case 41: // vmov Rn, Vd.<T>
  2502  		v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
  2503  		if v == 0 {
  2504  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2505  		}
  2506  
  2507  		Rj := uint32(p.From.Reg & EXT_REG_MASK)
  2508  		Vd := uint32(p.To.Reg & EXT_REG_MASK)
  2509  		o1 = v | (Rj << 5) | Vd
  2510  
  2511  	case 42: // vmov  xj, xd.<T>
  2512  		v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
  2513  		if v == 0 {
  2514  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2515  		}
  2516  
  2517  		Xj := uint32(p.From.Reg & EXT_REG_MASK)
  2518  		Xd := uint32(p.To.Reg & EXT_REG_MASK)
  2519  		o1 = v | (Xj << 5) | Xd
  2520  
  2521  	case 43: // vmov  xj, xd.<T>[index]
  2522  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
  2523  		if v == 0 {
  2524  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2525  		}
  2526  
  2527  		Xj := uint32(p.From.Reg & EXT_REG_MASK)
  2528  		Xd := uint32(p.To.Reg & EXT_REG_MASK)
  2529  		index := uint32(p.To.Index)
  2530  		c.checkindex(p, index, m)
  2531  		o1 = v | (index << 10) | (Xj << 5) | Xd
  2532  
  2533  	case 44: // vmov  xj.<T>[index], xd
  2534  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
  2535  		if v == 0 {
  2536  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2537  		}
  2538  
  2539  		Xj := uint32(p.From.Reg & EXT_REG_MASK)
  2540  		Xd := uint32(p.To.Reg & EXT_REG_MASK)
  2541  		index := uint32(p.From.Index)
  2542  		c.checkindex(p, index, m)
  2543  		o1 = v | (index << 10) | (Xj << 5) | Xd
  2544  
  2545  	case 45: // vmov  vj.<T>[index], vd.<T>
  2546  		v, m := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, false)
  2547  		if v == 0 {
  2548  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2549  		}
  2550  
  2551  		vj := uint32(p.From.Reg & EXT_REG_MASK)
  2552  		vd := uint32(p.To.Reg & EXT_REG_MASK)
  2553  		index := uint32(p.From.Index)
  2554  		c.checkindex(p, index, m)
  2555  		o1 = v | (index << 10) | (vj << 5) | vd
  2556  
  2557  	case 46: // vmov offset(vj), vd.<T>
  2558  		v, _ := c.specialLsxMovInst(p.As, p.From.Reg, p.To.Reg, true)
  2559  		if v == 0 {
  2560  			c.ctxt.Diag("illegal arng type combination: %v\n", p)
  2561  		}
  2562  
  2563  		si := c.regoff(&p.From)
  2564  		Rj := uint32(p.From.Reg & EXT_REG_MASK)
  2565  		Vd := uint32(p.To.Reg & EXT_REG_MASK)
  2566  		switch v & 0xc00000 {
  2567  		case 0x800000: // [x]vldrepl.b
  2568  			o1 = OP_12IRR(v, uint32(si), Rj, Vd)
  2569  		case 0x400000: // [x]vldrepl.h
  2570  			if si&1 != 0 {
  2571  				c.ctxt.Diag("%v: offset must be a multiple of 2.\n", p)
  2572  			}
  2573  			o1 = OP_11IRR(v, uint32(si>>1), Rj, Vd)
  2574  		case 0x0:
  2575  			switch v & 0x300000 {
  2576  			case 0x200000: // [x]vldrepl.w
  2577  				if si&3 != 0 {
  2578  					c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
  2579  				}
  2580  				o1 = OP_10IRR(v, uint32(si>>2), Rj, Vd)
  2581  			case 0x100000: // [x]vldrepl.d
  2582  				if si&7 != 0 {
  2583  					c.ctxt.Diag("%v: offset must be a multiple of 8.\n", p)
  2584  				}
  2585  				o1 = OP_9IRR(v, uint32(si>>3), Rj, Vd)
  2586  			}
  2587  		}
  2588  
  2589  	case 47: // preld  offset(Rbase), $hint
  2590  		offs := c.regoff(&p.From)
  2591  		hint := p.GetFrom3().Offset
  2592  		o1 = OP_12IR_5I(c.opiir(p.As), uint32(offs), uint32(p.From.Reg), uint32(hint))
  2593  
  2594  	case 48: // preldx offset(Rbase), $n, $hint
  2595  		offs := c.regoff(&p.From)
  2596  		hint := p.RestArgs[1].Offset
  2597  		n := uint64(p.GetFrom3().Offset)
  2598  
  2599  		addrSeq := (n >> 0) & 0x1
  2600  		blkSize := (n >> 1) & 0x7ff
  2601  		blkNums := (n >> 12) & 0x1ff
  2602  		stride := (n >> 21) & 0xffff
  2603  
  2604  		if blkSize > 1024 {
  2605  			c.ctxt.Diag("%v: block_size amount out of range[16, 1024]: %v\n", p, blkSize)
  2606  		}
  2607  
  2608  		if blkNums > 256 {
  2609  			c.ctxt.Diag("%v: block_nums amount out of range[1, 256]: %v\n", p, blkSize)
  2610  		}
  2611  
  2612  		v := (uint64(offs) & 0xffff)
  2613  		v += addrSeq << 16
  2614  		v += ((blkSize / 16) - 1) << 20
  2615  		v += (blkNums - 1) << 32
  2616  		v += stride << 44
  2617  
  2618  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2619  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2620  		o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2621  		o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2622  		o5 = OP_5IRR(c.opirr(p.As), uint32(REGTMP), uint32(p.From.Reg), uint32(hint))
  2623  
  2624  	case 49:
  2625  		if p.As == ANOOP {
  2626  			// andi r0, r0, 0
  2627  			o1 = OP_12IRR(c.opirr(AAND), 0, 0, 0)
  2628  		} else {
  2629  			// undef
  2630  			o1 = OP_15I(c.opi(ABREAK), 0)
  2631  		}
  2632  
  2633  	// relocation operations
  2634  	case 50: // mov r,addr ==> pcalau12i + sw
  2635  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
  2636  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2637  			Type: objabi.R_LOONG64_ADDR_HI,
  2638  			Off:  int32(c.pc),
  2639  			Siz:  4,
  2640  			Sym:  p.To.Sym,
  2641  			Add:  p.To.Offset,
  2642  		})
  2643  		o2 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
  2644  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2645  			Type: objabi.R_LOONG64_ADDR_LO,
  2646  			Off:  int32(c.pc + 4),
  2647  			Siz:  4,
  2648  			Sym:  p.To.Sym,
  2649  			Add:  p.To.Offset,
  2650  		})
  2651  
  2652  	case 51: // mov addr,r ==> pcalau12i + lw
  2653  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
  2654  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2655  			Type: objabi.R_LOONG64_ADDR_HI,
  2656  			Off:  int32(c.pc),
  2657  			Siz:  4,
  2658  			Sym:  p.From.Sym,
  2659  			Add:  p.From.Offset,
  2660  		})
  2661  		o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
  2662  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2663  			Type: objabi.R_LOONG64_ADDR_LO,
  2664  			Off:  int32(c.pc + 4),
  2665  			Siz:  4,
  2666  			Sym:  p.From.Sym,
  2667  			Add:  p.From.Offset,
  2668  		})
  2669  
  2670  	case 52: // mov $ext, r
  2671  		// NOTE: this case does not use REGTMP. If it ever does,
  2672  		// remove the NOTUSETMP flag in optab.
  2673  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
  2674  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2675  			Type: objabi.R_LOONG64_ADDR_HI,
  2676  			Off:  int32(c.pc),
  2677  			Siz:  4,
  2678  			Sym:  p.From.Sym,
  2679  			Add:  p.From.Offset,
  2680  		})
  2681  		o2 = OP_12IRR(c.opirr(add), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
  2682  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2683  			Type: objabi.R_LOONG64_ADDR_LO,
  2684  			Off:  int32(c.pc + 4),
  2685  			Siz:  4,
  2686  			Sym:  p.From.Sym,
  2687  			Add:  p.From.Offset,
  2688  		})
  2689  
  2690  	case 53: // mov r, tlsvar ==>  lu12i.w + ori + add r2, regtmp + sw o(regtmp)
  2691  		// NOTE: this case does not use REGTMP. If it ever does,
  2692  		// remove the NOTUSETMP flag in optab.
  2693  		o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
  2694  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2695  			Type: objabi.R_LOONG64_TLS_LE_HI,
  2696  			Off:  int32(c.pc),
  2697  			Siz:  4,
  2698  			Sym:  p.To.Sym,
  2699  			Add:  p.To.Offset,
  2700  		})
  2701  		o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
  2702  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2703  			Type: objabi.R_LOONG64_TLS_LE_LO,
  2704  			Off:  int32(c.pc + 4),
  2705  			Siz:  4,
  2706  			Sym:  p.To.Sym,
  2707  			Add:  p.To.Offset,
  2708  		})
  2709  		o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
  2710  		o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
  2711  
  2712  	case 54: // lu12i.w + ori + add r2, regtmp + lw o(regtmp)
  2713  		// NOTE: this case does not use REGTMP. If it ever does,
  2714  		// remove the NOTUSETMP flag in optab.
  2715  		o1 = OP_IR(c.opir(ALU12IW), uint32(0), uint32(REGTMP))
  2716  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2717  			Type: objabi.R_LOONG64_TLS_LE_HI,
  2718  			Off:  int32(c.pc),
  2719  			Siz:  4,
  2720  			Sym:  p.From.Sym,
  2721  			Add:  p.From.Offset,
  2722  		})
  2723  		o2 = OP_12IRR(c.opirr(AOR), uint32(0), uint32(REGTMP), uint32(REGTMP))
  2724  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2725  			Type: objabi.R_LOONG64_TLS_LE_LO,
  2726  			Off:  int32(c.pc + 4),
  2727  			Siz:  4,
  2728  			Sym:  p.From.Sym,
  2729  			Add:  p.From.Offset,
  2730  		})
  2731  		o3 = OP_RRR(c.oprrr(AADDV), uint32(REG_R2), uint32(REGTMP), uint32(REGTMP))
  2732  		o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
  2733  
  2734  	case 56: // mov r, tlsvar IE model ==> (pcalau12i + ld.d)tlsvar@got + add.d + st.d
  2735  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
  2736  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2737  			Type: objabi.R_LOONG64_TLS_IE_HI,
  2738  			Off:  int32(c.pc),
  2739  			Siz:  4,
  2740  			Sym:  p.To.Sym,
  2741  		})
  2742  		o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
  2743  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2744  			Type: objabi.R_LOONG64_TLS_IE_LO,
  2745  			Off:  int32(c.pc + 4),
  2746  			Siz:  4,
  2747  			Sym:  p.To.Sym,
  2748  		})
  2749  		o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
  2750  		o4 = OP_12IRR(c.opirr(p.As), uint32(0), uint32(REGTMP), uint32(p.From.Reg))
  2751  
  2752  	case 57: // mov tlsvar, r IE model ==> (pcalau12i + ld.d)tlsvar@got + add.d + ld.d
  2753  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(REGTMP))
  2754  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2755  			Type: objabi.R_LOONG64_TLS_IE_HI,
  2756  			Off:  int32(c.pc),
  2757  			Siz:  4,
  2758  			Sym:  p.From.Sym,
  2759  		})
  2760  		o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(REGTMP))
  2761  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2762  			Type: objabi.R_LOONG64_TLS_IE_LO,
  2763  			Off:  int32(c.pc + 4),
  2764  			Siz:  4,
  2765  			Sym:  p.From.Sym,
  2766  		})
  2767  		o3 = OP_RRR(c.oprrr(AADDVU), uint32(REGTMP), uint32(REG_R2), uint32(REGTMP))
  2768  		o4 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(REGTMP), uint32(p.To.Reg))
  2769  
  2770  	case 59: // mov $dcon,r
  2771  		// NOTE: this case does not use REGTMP. If it ever does,
  2772  		// remove the NOTUSETMP flag in optab.
  2773  		v := c.vregoff(&p.From)
  2774  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2775  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
  2776  		o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2777  		o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2778  
  2779  	case 60: // add $dcon,r1,r2
  2780  		v := c.vregoff(&p.From)
  2781  		o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2782  		o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2783  		o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2784  		o4 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2785  		r := int(p.Reg)
  2786  		if r == 0 {
  2787  			r = int(p.To.Reg)
  2788  		}
  2789  		o5 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2790  
  2791  	case 61: // word C_DCON
  2792  		o1 = uint32(c.vregoff(&p.From))
  2793  		o2 = uint32(c.vregoff(&p.From) >> 32)
  2794  
  2795  	case 62: // rdtimex rd, rj
  2796  		o1 = OP_RR(c.oprr(p.As), uint32(p.To.Reg), uint32(p.RegTo2))
  2797  
  2798  	case 64: // alsl rd, rj, rk, sa2
  2799  		sa := p.From.Offset - 1
  2800  		if sa < 0 || sa > 3 {
  2801  			c.ctxt.Diag("%v: shift amount out of range[1, 4].\n", p)
  2802  		}
  2803  		r := p.GetFrom3().Reg
  2804  		o1 = OP_2IRRR(c.opirrr(p.As), uint32(sa), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
  2805  
  2806  	case 65: // mov sym@GOT, r ==> pcalau12i + ld.d
  2807  		o1 = OP_IR(c.opir(APCALAU12I), uint32(0), uint32(p.To.Reg))
  2808  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2809  			Type: objabi.R_LOONG64_GOT_HI,
  2810  			Off:  int32(c.pc),
  2811  			Siz:  4,
  2812  			Sym:  p.From.Sym,
  2813  		})
  2814  		o2 = OP_12IRR(c.opirr(-p.As), uint32(0), uint32(p.To.Reg), uint32(p.To.Reg))
  2815  		c.cursym.AddRel(c.ctxt, obj.Reloc{
  2816  			Type: objabi.R_LOONG64_GOT_LO,
  2817  			Off:  int32(c.pc + 4),
  2818  			Siz:  4,
  2819  			Sym:  p.From.Sym,
  2820  		})
  2821  
  2822  	case 66: // am* From, To, RegTo2 ==> am* RegTo2, From, To
  2823  		rk := p.From.Reg
  2824  		rj := p.To.Reg
  2825  		rd := p.RegTo2
  2826  
  2827  		// See section 2.2.7.1 of https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html
  2828  		// for the register usage constraints.
  2829  		if rd == rj || rd == rk {
  2830  			c.ctxt.Diag("illegal register combination: %v\n", p)
  2831  		}
  2832  		o1 = OP_RRR(atomicInst[p.As], uint32(rk), uint32(rj), uint32(rd))
  2833  
  2834  	case 67: // mov $dcon12_0, r
  2835  		v := c.vregoff(&p.From)
  2836  		o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(p.To.Reg))
  2837  
  2838  	case 68: // mov $dcon12_20S, r
  2839  		v := c.vregoff(&p.From)
  2840  		contype := c.aclass(&p.From)
  2841  		switch contype {
  2842  		default: // C_DCON12_20S
  2843  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2844  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2845  		case C_DCON20S_20:
  2846  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2847  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2848  		case C_DCON12_12S:
  2849  			o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(p.To.Reg))
  2850  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2851  		case C_DCON20S_12S, C_DCON20S_0:
  2852  			o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
  2853  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2854  		case C_DCON12_12U:
  2855  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
  2856  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2857  		case C_DCON20S_12U:
  2858  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
  2859  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2860  		}
  2861  
  2862  	case 69: // mov $dcon32_12S, r
  2863  		v := c.vregoff(&p.From)
  2864  		contype := c.aclass(&p.From)
  2865  		switch contype {
  2866  		default: // C_DCON32_12S, C_DCON32_0
  2867  			o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(p.To.Reg))
  2868  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2869  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2870  		case C_DCON32_20:
  2871  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2872  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2873  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2874  		case C_DCON12_32S:
  2875  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2876  			o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
  2877  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2878  		case C_DCON20S_32:
  2879  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(p.To.Reg))
  2880  			o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(p.To.Reg), uint32(p.To.Reg))
  2881  			o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2882  		case C_DCON32_12U:
  2883  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(p.To.Reg))
  2884  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(p.To.Reg))
  2885  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(p.To.Reg), uint32(p.To.Reg))
  2886  		}
  2887  
  2888  	case 70: // add $dcon12_0,[r1],r2
  2889  		v := c.vregoff(&p.From)
  2890  		r := int(p.Reg)
  2891  		if r == 0 {
  2892  			r = int(p.To.Reg)
  2893  		}
  2894  		o1 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(0), uint32(REGTMP))
  2895  		o2 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2896  
  2897  	case 71: // add $dcon12_20S,[r1],r2
  2898  		v := c.vregoff(&p.From)
  2899  		r := int(p.Reg)
  2900  		if r == 0 {
  2901  			r = int(p.To.Reg)
  2902  		}
  2903  		contype := c.aclass(&p.From)
  2904  		switch contype {
  2905  		default: // C_DCON12_20S
  2906  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2907  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2908  		case C_DCON20S_20:
  2909  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2910  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2911  		case C_DCON12_12S:
  2912  			o1 = OP_12IRR(c.opirr(AADDV), uint32(v), uint32(0), uint32(REGTMP))
  2913  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2914  		case C_DCON20S_12S, C_DCON20S_0:
  2915  			o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
  2916  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2917  		case C_DCON12_12U:
  2918  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
  2919  			o2 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2920  		case C_DCON20S_12U:
  2921  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
  2922  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2923  		}
  2924  		o3 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2925  
  2926  	case 72: // add $dcon32_12S,[r1],r2
  2927  		v := c.vregoff(&p.From)
  2928  		r := int(p.Reg)
  2929  		if r == 0 {
  2930  			r = int(p.To.Reg)
  2931  		}
  2932  		contype := c.aclass(&p.From)
  2933  		switch contype {
  2934  		default: // C_DCON32_12S, C_DCON32_0
  2935  			o1 = OP_12IRR(c.opirr(AADD), uint32(v), uint32(0), uint32(REGTMP))
  2936  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2937  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2938  		case C_DCON32_20:
  2939  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2940  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2941  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2942  		case C_DCON12_32S:
  2943  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2944  			o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2945  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2946  		case C_DCON20S_32:
  2947  			o1 = OP_IR(c.opir(ALU12IW), uint32(v>>12), uint32(REGTMP))
  2948  			o2 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(REGTMP), uint32(REGTMP))
  2949  			o3 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2950  		case C_DCON32_12U:
  2951  			o1 = OP_12IRR(c.opirr(AOR), uint32(v), uint32(0), uint32(REGTMP))
  2952  			o2 = OP_IR(c.opir(ALU32ID), uint32(v>>32), uint32(REGTMP))
  2953  			o3 = OP_12IRR(c.opirr(ALU52ID), uint32(v>>52), uint32(REGTMP), uint32(REGTMP))
  2954  		}
  2955  		o4 = OP_RRR(c.oprrr(p.As), uint32(REGTMP), uint32(r), uint32(p.To.Reg))
  2956  
  2957  	case 73:
  2958  		v := c.regoff(&p.To)
  2959  		if v&3 != 0 {
  2960  			c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
  2961  		}
  2962  		o1 = OP_14IRR(c.opirr(p.As), uint32(v>>2), uint32(p.To.Reg), uint32(p.From.Reg))
  2963  
  2964  	case 74:
  2965  		v := c.regoff(&p.From)
  2966  		if v&3 != 0 {
  2967  			c.ctxt.Diag("%v: offset must be a multiple of 4.\n", p)
  2968  		}
  2969  		o1 = OP_14IRR(c.opirr(-p.As), uint32(v>>2), uint32(p.From.Reg), uint32(p.To.Reg))
  2970  	}
  2971  
  2972  	out[0] = o1
  2973  	out[1] = o2
  2974  	out[2] = o3
  2975  	out[3] = o4
  2976  	out[4] = o5
  2977  }
  2978  
  2979  // checkoperand checks if operand >= 0 && operand <= maxoperand
  2980  func (c *ctxt0) checkoperand(p *obj.Prog, operand uint32, mask uint32) {
  2981  	if (operand & ^mask) != 0 {
  2982  		c.ctxt.Diag("operand out of range 0 to %d: %v", mask, p)
  2983  	}
  2984  }
  2985  
  2986  // checkindex checks if index >= 0 && index <= maxindex
  2987  func (c *ctxt0) checkindex(p *obj.Prog, index uint32, mask uint32) {
  2988  	if (index & ^mask) != 0 {
  2989  		c.ctxt.Diag("register element index out of range 0 to %d: %v", mask, p)
  2990  	}
  2991  }
  2992  
  2993  func (c *ctxt0) vregoff(a *obj.Addr) int64 {
  2994  	c.instoffset = 0
  2995  	c.aclass(a)
  2996  	return c.instoffset
  2997  }
  2998  
  2999  func (c *ctxt0) regoff(a *obj.Addr) int32 {
  3000  	return int32(c.vregoff(a))
  3001  }
  3002  
  3003  func (c *ctxt0) oprrrr(a obj.As) uint32 {
  3004  	switch a {
  3005  	case AFMADDF:
  3006  		return 0x81 << 20 // fmadd.s
  3007  	case AFMADDD:
  3008  		return 0x82 << 20 // fmadd.d
  3009  	case AFMSUBF:
  3010  		return 0x85 << 20 // fmsub.s
  3011  	case AFMSUBD:
  3012  		return 0x86 << 20 // fmsub.d
  3013  	case AFNMADDF:
  3014  		return 0x89 << 20 // fnmadd.f
  3015  	case AFNMADDD:
  3016  		return 0x8a << 20 // fnmadd.d
  3017  	case AFNMSUBF:
  3018  		return 0x8d << 20 // fnmsub.s
  3019  	case AFNMSUBD:
  3020  		return 0x8e << 20 // fnmsub.d
  3021  	}
  3022  
  3023  	c.ctxt.Diag("bad rrrr opcode %v", a)
  3024  	return 0
  3025  }
  3026  
  3027  func (c *ctxt0) oprrr(a obj.As) uint32 {
  3028  	switch a {
  3029  	case AADD:
  3030  		return 0x20 << 15
  3031  	case AADDU:
  3032  		return 0x20 << 15
  3033  	case ASGT:
  3034  		return 0x24 << 15 // SLT
  3035  	case ASGTU:
  3036  		return 0x25 << 15 // SLTU
  3037  	case AMASKEQZ:
  3038  		return 0x26 << 15
  3039  	case AMASKNEZ:
  3040  		return 0x27 << 15
  3041  	case AAND:
  3042  		return 0x29 << 15
  3043  	case AOR:
  3044  		return 0x2a << 15
  3045  	case AXOR:
  3046  		return 0x2b << 15
  3047  	case AORN:
  3048  		return 0x2c << 15 // orn
  3049  	case AANDN:
  3050  		return 0x2d << 15 // andn
  3051  	case ASUB:
  3052  		return 0x22 << 15
  3053  	case ASUBU, ANEGW:
  3054  		return 0x22 << 15
  3055  	case ANOR:
  3056  		return 0x28 << 15
  3057  	case ASLL:
  3058  		return 0x2e << 15
  3059  	case ASRL:
  3060  		return 0x2f << 15
  3061  	case ASRA:
  3062  		return 0x30 << 15
  3063  	case AROTR:
  3064  		return 0x36 << 15
  3065  	case ASLLV:
  3066  		return 0x31 << 15
  3067  	case ASRLV:
  3068  		return 0x32 << 15
  3069  	case ASRAV:
  3070  		return 0x33 << 15
  3071  	case AROTRV:
  3072  		return 0x37 << 15
  3073  	case AADDV:
  3074  		return 0x21 << 15
  3075  	case AADDVU:
  3076  		return 0x21 << 15
  3077  	case ASUBV:
  3078  		return 0x23 << 15
  3079  	case ASUBVU, ANEGV:
  3080  		return 0x23 << 15
  3081  
  3082  	case AMUL:
  3083  		return 0x38 << 15 // mul.w
  3084  	case AMULU:
  3085  		return 0x38 << 15 // mul.w
  3086  	case AMULH:
  3087  		return 0x39 << 15 // mulh.w
  3088  	case AMULHU:
  3089  		return 0x3a << 15 // mulhu.w
  3090  	case AMULV:
  3091  		return 0x3b << 15 // mul.d
  3092  	case AMULVU:
  3093  		return 0x3b << 15 // mul.d
  3094  	case AMULHV:
  3095  		return 0x3c << 15 // mulh.d
  3096  	case AMULHVU:
  3097  		return 0x3d << 15 // mulhu.d
  3098  	case ADIV:
  3099  		return 0x40 << 15 // div.w
  3100  	case ADIVU:
  3101  		return 0x42 << 15 // div.wu
  3102  	case ADIVV:
  3103  		return 0x44 << 15 // div.d
  3104  	case ADIVVU:
  3105  		return 0x46 << 15 // div.du
  3106  	case AREM:
  3107  		return 0x41 << 15 // mod.w
  3108  	case AREMU:
  3109  		return 0x43 << 15 // mod.wu
  3110  	case AREMV:
  3111  		return 0x45 << 15 // mod.d
  3112  	case AREMVU:
  3113  		return 0x47 << 15 // mod.du
  3114  	case ACRCWBW:
  3115  		return 0x48 << 15 // crc.w.b.w
  3116  	case ACRCWHW:
  3117  		return 0x49 << 15 // crc.w.h.w
  3118  	case ACRCWWW:
  3119  		return 0x4a << 15 // crc.w.w.w
  3120  	case ACRCWVW:
  3121  		return 0x4b << 15 // crc.w.d.w
  3122  	case ACRCCWBW:
  3123  		return 0x4c << 15 // crcc.w.b.w
  3124  	case ACRCCWHW:
  3125  		return 0x4d << 15 // crcc.w.h.w
  3126  	case ACRCCWWW:
  3127  		return 0x4e << 15 // crcc.w.w.w
  3128  	case ACRCCWVW:
  3129  		return 0x4f << 15 // crcc.w.d.w
  3130  	case AJMP:
  3131  		return 0x13 << 26 // jirl r0, rj, 0
  3132  	case AJAL:
  3133  		return (0x13 << 26) | 1 // jirl r1, rj, 0
  3134  
  3135  	case ADIVF:
  3136  		return 0x20d << 15
  3137  	case ADIVD:
  3138  		return 0x20e << 15
  3139  	case AMULF:
  3140  		return 0x209 << 15
  3141  	case AMULD:
  3142  		return 0x20a << 15
  3143  	case ASUBF:
  3144  		return 0x205 << 15
  3145  	case ASUBD:
  3146  		return 0x206 << 15
  3147  	case AADDF:
  3148  		return 0x201 << 15
  3149  	case AADDD:
  3150  		return 0x202 << 15
  3151  	case ACMPEQF:
  3152  		return 0x0c1<<20 | 0x4<<15 // FCMP.CEQ.S
  3153  	case ACMPEQD:
  3154  		return 0x0c2<<20 | 0x4<<15 // FCMP.CEQ.D
  3155  	case ACMPGED:
  3156  		return 0x0c2<<20 | 0x7<<15 // FCMP.SLE.D
  3157  	case ACMPGEF:
  3158  		return 0x0c1<<20 | 0x7<<15 // FCMP.SLE.S
  3159  	case ACMPGTD:
  3160  		return 0x0c2<<20 | 0x3<<15 // FCMP.SLT.D
  3161  	case ACMPGTF:
  3162  		return 0x0c1<<20 | 0x3<<15 // FCMP.SLT.S
  3163  	case AFMINF:
  3164  		return 0x215 << 15 // fmin.s
  3165  	case AFMIND:
  3166  		return 0x216 << 15 // fmin.d
  3167  	case AFMAXF:
  3168  		return 0x211 << 15 // fmax.s
  3169  	case AFMAXD:
  3170  		return 0x212 << 15 // fmax.d
  3171  	case AFMAXAF:
  3172  		return 0x219 << 15 // fmaxa.s
  3173  	case AFMAXAD:
  3174  		return 0x21a << 15 // fmaxa.d
  3175  	case AFMINAF:
  3176  		return 0x21d << 15 // fmina.s
  3177  	case AFMINAD:
  3178  		return 0x21e << 15 // fmina.d
  3179  	case AFSCALEBF:
  3180  		return 0x221 << 15 // fscaleb.s
  3181  	case AFSCALEBD:
  3182  		return 0x222 << 15 // fscaleb.d
  3183  	case AFCOPYSGF:
  3184  		return 0x225 << 15 // fcopysign.s
  3185  	case AFCOPYSGD:
  3186  		return 0x226 << 15 // fcopysign.d
  3187  	case -AMOVB:
  3188  		return 0x07000 << 15 // ldx.b
  3189  	case -AMOVH:
  3190  		return 0x07008 << 15 // ldx.h
  3191  	case -AMOVW:
  3192  		return 0x07010 << 15 // ldx.w
  3193  	case -AMOVV:
  3194  		return 0x07018 << 15 // ldx.d
  3195  	case -AMOVBU:
  3196  		return 0x07040 << 15 // ldx.bu
  3197  	case -AMOVHU:
  3198  		return 0x07048 << 15 // ldx.hu
  3199  	case -AMOVWU:
  3200  		return 0x07050 << 15 // ldx.wu
  3201  	case AMOVB:
  3202  		return 0x07020 << 15 // stx.b
  3203  	case AMOVH:
  3204  		return 0x07028 << 15 // stx.h
  3205  	case AMOVW:
  3206  		return 0x07030 << 15 // stx.w
  3207  	case AMOVV:
  3208  		return 0x07038 << 15 // stx.d
  3209  	case -AMOVF:
  3210  		return 0x07060 << 15 // fldx.s
  3211  	case -AMOVD:
  3212  		return 0x07068 << 15 // fldx.d
  3213  	case AMOVF:
  3214  		return 0x07070 << 15 // fstx.s
  3215  	case AMOVD:
  3216  		return 0x07078 << 15 // fstx.d
  3217  	case -AVMOVQ:
  3218  		return 0x07080 << 15 // vldx
  3219  	case -AXVMOVQ:
  3220  		return 0x07090 << 15 // xvldx
  3221  	case AVMOVQ:
  3222  		return 0x07088 << 15 // vstx
  3223  	case AXVMOVQ:
  3224  		return 0x07098 << 15 // xvstx
  3225  	case AVSEQB:
  3226  		return 0x0e000 << 15 // vseq.b
  3227  	case AXVSEQB:
  3228  		return 0x0e800 << 15 // xvseq.b
  3229  	case AVSEQH:
  3230  		return 0x0e001 << 15 // vseq.h
  3231  	case AXVSEQH:
  3232  		return 0x0e801 << 15 // xvseq.h
  3233  	case AVSEQW:
  3234  		return 0x0e002 << 15 // vseq.w
  3235  	case AXVSEQW:
  3236  		return 0x0e802 << 15 // xvseq.w
  3237  	case AVSEQV:
  3238  		return 0x0e003 << 15 // vseq.d
  3239  	case AXVSEQV:
  3240  		return 0x0e803 << 15 // xvseq.d
  3241  	case AVANDV:
  3242  		return 0x0E24C << 15 // vand.v
  3243  	case AVORV:
  3244  		return 0x0E24D << 15 // vor.v
  3245  	case AVXORV:
  3246  		return 0x0E24E << 15 // vxor.v
  3247  	case AVNORV:
  3248  		return 0x0E24F << 15 // vnor.v
  3249  	case AVANDNV:
  3250  		return 0x0E250 << 15 // vandn.v
  3251  	case AVORNV:
  3252  		return 0x0E251 << 15 // vorn.v
  3253  	case AXVANDV:
  3254  		return 0x0EA4C << 15 // xvand.v
  3255  	case AXVORV:
  3256  		return 0x0EA4D << 15 // xvor.v
  3257  	case AXVXORV:
  3258  		return 0x0EA4E << 15 // xvxor.v
  3259  	case AXVNORV:
  3260  		return 0x0EA4F << 15 // xvnor.v
  3261  	case AXVANDNV:
  3262  		return 0x0EA50 << 15 // xvandn.v
  3263  	case AXVORNV:
  3264  		return 0x0EA51 << 15 // xvorn.v
  3265  	case AVDIVB:
  3266  		return 0xe1c0 << 15 // vdiv.b
  3267  	case AVDIVH:
  3268  		return 0xe1c1 << 15 // vdiv.h
  3269  	case AVDIVW:
  3270  		return 0xe1c2 << 15 // vdiv.w
  3271  	case AVDIVV:
  3272  		return 0xe1c3 << 15 // vdiv.d
  3273  	case AVMODB:
  3274  		return 0xe1c4 << 15 // vmod.b
  3275  	case AVMODH:
  3276  		return 0xe1c5 << 15 // vmod.h
  3277  	case AVMODW:
  3278  		return 0xe1c6 << 15 // vmod.w
  3279  	case AVMODV:
  3280  		return 0xe1c7 << 15 // vmod.d
  3281  	case AVDIVBU:
  3282  		return 0xe1c8 << 15 // vdiv.bu
  3283  	case AVDIVHU:
  3284  		return 0xe1c9 << 15 // vdiv.hu
  3285  	case AVDIVWU:
  3286  		return 0xe1ca << 15 // vdiv.wu
  3287  	case AVDIVVU:
  3288  		return 0xe1cb << 15 // vdiv.du
  3289  	case AVMODBU:
  3290  		return 0xe1cc << 15 // vmod.bu
  3291  	case AVMODHU:
  3292  		return 0xe1cd << 15 // vmod.hu
  3293  	case AVMODWU:
  3294  		return 0xe1ce << 15 // vmod.wu
  3295  	case AVMODVU:
  3296  		return 0xe1cf << 15 // vmod.du
  3297  	case AXVDIVB:
  3298  		return 0xe9c0 << 15 // xvdiv.b
  3299  	case AXVDIVH:
  3300  		return 0xe9c1 << 15 // xvdiv.h
  3301  	case AXVDIVW:
  3302  		return 0xe9c2 << 15 // xvdiv.w
  3303  	case AXVDIVV:
  3304  		return 0xe9c3 << 15 // xvdiv.d
  3305  	case AXVMODB:
  3306  		return 0xe9c4 << 15 // xvmod.b
  3307  	case AXVMODH:
  3308  		return 0xe9c5 << 15 // xvmod.h
  3309  	case AXVMODW:
  3310  		return 0xe9c6 << 15 // xvmod.w
  3311  	case AXVMODV:
  3312  		return 0xe9c7 << 15 // xvmod.d
  3313  	case AXVDIVBU:
  3314  		return 0xe9c8 << 15 // xvdiv.bu
  3315  	case AXVDIVHU:
  3316  		return 0xe9c9 << 15 // xvdiv.hu
  3317  	case AXVDIVWU:
  3318  		return 0xe9ca << 15 // xvdiv.wu
  3319  	case AXVDIVVU:
  3320  		return 0xe9cb << 15 // xvdiv.du
  3321  	case AXVMODBU:
  3322  		return 0xe9cc << 15 // xvmod.bu
  3323  	case AXVMODHU:
  3324  		return 0xe9cd << 15 // xvmod.hu
  3325  	case AXVMODWU:
  3326  		return 0xe9ce << 15 // xvmod.wu
  3327  	case AXVMODVU:
  3328  		return 0xe9cf << 15 // xvmod.du
  3329  	case AVMULWEVHB:
  3330  		return 0xe120 << 15 // vmulwev.h.b
  3331  	case AVMULWEVWH:
  3332  		return 0xe121 << 15 // vmulwev.w.h
  3333  	case AVMULWEVVW:
  3334  		return 0xe122 << 15 // vmulwev.d.w
  3335  	case AVMULWEVQV:
  3336  		return 0xe123 << 15 // vmulwev.q.d
  3337  	case AVMULWODHB:
  3338  		return 0xe124 << 15 // vmulwod.h.b
  3339  	case AVMULWODWH:
  3340  		return 0xe125 << 15 // vmulwod.w.h
  3341  	case AVMULWODVW:
  3342  		return 0xe126 << 15 // vmulwod.d.w
  3343  	case AVMULWODQV:
  3344  		return 0xe127 << 15 // vmulwod.q.d
  3345  	case AVMULWEVHBU:
  3346  		return 0xe130 << 15 // vmulwev.h.bu
  3347  	case AVMULWEVWHU:
  3348  		return 0xe131 << 15 // vmulwev.w.hu
  3349  	case AVMULWEVVWU:
  3350  		return 0xe132 << 15 // vmulwev.d.wu
  3351  	case AVMULWEVQVU:
  3352  		return 0xe133 << 15 // vmulwev.q.du
  3353  	case AVMULWODHBU:
  3354  		return 0xe134 << 15 // vmulwod.h.bu
  3355  	case AVMULWODWHU:
  3356  		return 0xe135 << 15 // vmulwod.w.hu
  3357  	case AVMULWODVWU:
  3358  		return 0xe136 << 15 // vmulwod.d.wu
  3359  	case AVMULWODQVU:
  3360  		return 0xe137 << 15 // vmulwod.q.du
  3361  	case AVMULWEVHBUB:
  3362  		return 0xe140 << 15 // vmulwev.h.bu.b
  3363  	case AVMULWEVWHUH:
  3364  		return 0xe141 << 15 // vmulwev.w.hu.h
  3365  	case AVMULWEVVWUW:
  3366  		return 0xe142 << 15 // vmulwev.d.wu.w
  3367  	case AVMULWEVQVUV:
  3368  		return 0xe143 << 15 // vmulwev.q.du.d
  3369  	case AVMULWODHBUB:
  3370  		return 0xe144 << 15 // vmulwod.h.bu.b
  3371  	case AVMULWODWHUH:
  3372  		return 0xe145 << 15 // vmulwod.w.hu.h
  3373  	case AVMULWODVWUW:
  3374  		return 0xe146 << 15 // vmulwod.d.wu.w
  3375  	case AVMULWODQVUV:
  3376  		return 0xe147 << 15 // vmulwod.q.du.d
  3377  	case AXVMULWEVHB:
  3378  		return 0xe920 << 15 // xvmulwev.h.b
  3379  	case AXVMULWEVWH:
  3380  		return 0xe921 << 15 // xvmulwev.w.h
  3381  	case AXVMULWEVVW:
  3382  		return 0xe922 << 15 // xvmulwev.d.w
  3383  	case AXVMULWEVQV:
  3384  		return 0xe923 << 15 // xvmulwev.q.d
  3385  	case AXVMULWODHB:
  3386  		return 0xe924 << 15 // xvmulwod.h.b
  3387  	case AXVMULWODWH:
  3388  		return 0xe925 << 15 // xvmulwod.w.h
  3389  	case AXVMULWODVW:
  3390  		return 0xe926 << 15 // xvmulwod.d.w
  3391  	case AXVMULWODQV:
  3392  		return 0xe927 << 15 // xvmulwod.q.d
  3393  	case AXVMULWEVHBU:
  3394  		return 0xe930 << 15 // xvmulwev.h.bu
  3395  	case AXVMULWEVWHU:
  3396  		return 0xe931 << 15 // xvmulwev.w.hu
  3397  	case AXVMULWEVVWU:
  3398  		return 0xe932 << 15 // xvmulwev.d.wu
  3399  	case AXVMULWEVQVU:
  3400  		return 0xe933 << 15 // xvmulwev.q.du
  3401  	case AXVMULWODHBU:
  3402  		return 0xe934 << 15 // xvmulwod.h.bu
  3403  	case AXVMULWODWHU:
  3404  		return 0xe935 << 15 // xvmulwod.w.hu
  3405  	case AXVMULWODVWU:
  3406  		return 0xe936 << 15 // xvmulwod.d.wu
  3407  	case AXVMULWODQVU:
  3408  		return 0xe937 << 15 // xvmulwod.q.du
  3409  	case AXVMULWEVHBUB:
  3410  		return 0xe940 << 15 // xvmulwev.h.bu.b
  3411  	case AXVMULWEVWHUH:
  3412  		return 0xe941 << 15 // xvmulwev.w.hu.h
  3413  	case AXVMULWEVVWUW:
  3414  		return 0xe942 << 15 // xvmulwev.d.wu.w
  3415  	case AXVMULWEVQVUV:
  3416  		return 0xe943 << 15 // xvmulwev.q.du.d
  3417  	case AXVMULWODHBUB:
  3418  		return 0xe944 << 15 // xvmulwod.h.bu.b
  3419  	case AXVMULWODWHUH:
  3420  		return 0xe945 << 15 // xvmulwod.w.hu.h
  3421  	case AXVMULWODVWUW:
  3422  		return 0xe946 << 15 // xvmulwod.d.wu.w
  3423  	case AXVMULWODQVUV:
  3424  		return 0xe947 << 15 // xvmulwod.q.du.d
  3425  	case AVSLLB:
  3426  		return 0xe1d0 << 15 // vsll.b
  3427  	case AVSLLH:
  3428  		return 0xe1d1 << 15 // vsll.h
  3429  	case AVSLLW:
  3430  		return 0xe1d2 << 15 // vsll.w
  3431  	case AVSLLV:
  3432  		return 0xe1d3 << 15 // vsll.d
  3433  	case AVSRLB:
  3434  		return 0xe1d4 << 15 // vsrl.b
  3435  	case AVSRLH:
  3436  		return 0xe1d5 << 15 // vsrl.h
  3437  	case AVSRLW:
  3438  		return 0xe1d6 << 15 // vsrl.w
  3439  	case AVSRLV:
  3440  		return 0xe1d7 << 15 // vsrl.d
  3441  	case AVSRAB:
  3442  		return 0xe1d8 << 15 // vsra.b
  3443  	case AVSRAH:
  3444  		return 0xe1d9 << 15 // vsra.h
  3445  	case AVSRAW:
  3446  		return 0xe1da << 15 // vsra.w
  3447  	case AVSRAV:
  3448  		return 0xe1db << 15 // vsra.d
  3449  	case AVROTRB:
  3450  		return 0xe1dc << 15 // vrotr.b
  3451  	case AVROTRH:
  3452  		return 0xe1dd << 15 // vrotr.h
  3453  	case AVROTRW:
  3454  		return 0xe1de << 15 // vrotr.w
  3455  	case AVROTRV:
  3456  		return 0xe1df << 15 // vrotr.d
  3457  	case AXVSLLB:
  3458  		return 0xe9d0 << 15 // xvsll.b
  3459  	case AXVSLLH:
  3460  		return 0xe9d1 << 15 // xvsll.h
  3461  	case AXVSLLW:
  3462  		return 0xe9d2 << 15 // xvsll.w
  3463  	case AXVSLLV:
  3464  		return 0xe9d3 << 15 // xvsll.d
  3465  	case AXVSRLB:
  3466  		return 0xe9d4 << 15 // xvsrl.b
  3467  	case AXVSRLH:
  3468  		return 0xe9d5 << 15 // xvsrl.h
  3469  	case AXVSRLW:
  3470  		return 0xe9d6 << 15 // xvsrl.w
  3471  	case AXVSRLV:
  3472  		return 0xe9d7 << 15 // xvsrl.d
  3473  	case AXVSRAB:
  3474  		return 0xe9d8 << 15 // xvsra.b
  3475  	case AXVSRAH:
  3476  		return 0xe9d9 << 15 // xvsra.h
  3477  	case AXVSRAW:
  3478  		return 0xe9da << 15 // xvsra.w
  3479  	case AXVSRAV:
  3480  		return 0xe9db << 15 // xvsra.d
  3481  	case AXVROTRB:
  3482  		return 0xe9dc << 15 // xvrotr.b
  3483  	case AXVROTRH:
  3484  		return 0xe9dd << 15 // xvrotr.h
  3485  	case AXVROTRW:
  3486  		return 0xe9de << 15 // xvrotr.w
  3487  	case AXVROTRV:
  3488  		return 0xe9df << 15 // xvrotr.d
  3489  	case AVADDB:
  3490  		return 0xe014 << 15 // vadd.b
  3491  	case AVADDH:
  3492  		return 0xe015 << 15 // vadd.h
  3493  	case AVADDW:
  3494  		return 0xe016 << 15 // vadd.w
  3495  	case AVADDV:
  3496  		return 0xe017 << 15 // vadd.d
  3497  	case AVADDQ:
  3498  		return 0xe25a << 15 // vadd.q
  3499  	case AVSUBB:
  3500  		return 0xe018 << 15 // vsub.b
  3501  	case AVSUBH:
  3502  		return 0xe019 << 15 // vsub.h
  3503  	case AVSUBW:
  3504  		return 0xe01a << 15 // vsub.w
  3505  	case AVSUBV:
  3506  		return 0xe01b << 15 // vsub.d
  3507  	case AVSUBQ:
  3508  		return 0xe25b << 15 // vsub.q
  3509  	case AXVADDB:
  3510  		return 0xe814 << 15 // xvadd.b
  3511  	case AXVADDH:
  3512  		return 0xe815 << 15 // xvadd.h
  3513  	case AXVADDW:
  3514  		return 0xe816 << 15 // xvadd.w
  3515  	case AXVADDV:
  3516  		return 0xe817 << 15 // xvadd.d
  3517  	case AXVADDQ:
  3518  		return 0xea5a << 15 // xvadd.q
  3519  	case AXVSUBB:
  3520  		return 0xe818 << 15 // xvsub.b
  3521  	case AXVSUBH:
  3522  		return 0xe819 << 15 // xvsub.h
  3523  	case AXVSUBW:
  3524  		return 0xe81a << 15 // xvsub.w
  3525  	case AXVSUBV:
  3526  		return 0xe81b << 15 // xvsub.d
  3527  	case AXVSUBQ:
  3528  		return 0xea5b << 15 // xvsub.q
  3529  	case AVILVLB:
  3530  		return 0xe234 << 15 // vilvl.b
  3531  	case AVILVLH:
  3532  		return 0xe235 << 15 // vilvl.h
  3533  	case AVILVLW:
  3534  		return 0xe236 << 15 // vilvl.w
  3535  	case AVILVLV:
  3536  		return 0xe237 << 15 // vilvl.d
  3537  	case AVILVHB:
  3538  		return 0xe238 << 15 // vilvh.b
  3539  	case AVILVHH:
  3540  		return 0xe239 << 15 // vilvh.h
  3541  	case AVILVHW:
  3542  		return 0xe23a << 15 // vilvh.w
  3543  	case AVILVHV:
  3544  		return 0xe23b << 15 // vilvh.d
  3545  	case AXVILVLB:
  3546  		return 0xea34 << 15 // xvilvl.b
  3547  	case AXVILVLH:
  3548  		return 0xea35 << 15 // xvilvl.h
  3549  	case AXVILVLW:
  3550  		return 0xea36 << 15 // xvilvl.w
  3551  	case AXVILVLV:
  3552  		return 0xea37 << 15 // xvilvl.d
  3553  	case AXVILVHB:
  3554  		return 0xea38 << 15 // xvilvh.b
  3555  	case AXVILVHH:
  3556  		return 0xea39 << 15 // xvilvh.h
  3557  	case AXVILVHW:
  3558  		return 0xea3a << 15 // xvilvh.w
  3559  	case AXVILVHV:
  3560  		return 0xea3b << 15 // xvilvh.d
  3561  	case AVMULB:
  3562  		return 0xe108 << 15 // vmul.b
  3563  	case AVMULH:
  3564  		return 0xe109 << 15 // vmul.h
  3565  	case AVMULW:
  3566  		return 0xe10a << 15 // vmul.w
  3567  	case AVMULV:
  3568  		return 0xe10b << 15 // vmul.d
  3569  	case AVMUHB:
  3570  		return 0xe10c << 15 // vmuh.b
  3571  	case AVMUHH:
  3572  		return 0xe10d << 15 // vmuh.h
  3573  	case AVMUHW:
  3574  		return 0xe10e << 15 // vmuh.w
  3575  	case AVMUHV:
  3576  		return 0xe10f << 15 // vmuh.d
  3577  	case AVMUHBU:
  3578  		return 0xe110 << 15 // vmuh.bu
  3579  	case AVMUHHU:
  3580  		return 0xe111 << 15 // vmuh.hu
  3581  	case AVMUHWU:
  3582  		return 0xe112 << 15 // vmuh.wu
  3583  	case AVMUHVU:
  3584  		return 0xe113 << 15 // vmuh.du
  3585  	case AXVMULB:
  3586  		return 0xe908 << 15 // xvmul.b
  3587  	case AXVMULH:
  3588  		return 0xe909 << 15 // xvmul.h
  3589  	case AXVMULW:
  3590  		return 0xe90a << 15 // xvmul.w
  3591  	case AXVMULV:
  3592  		return 0xe90b << 15 // xvmul.d
  3593  	case AXVMUHB:
  3594  		return 0xe90c << 15 // xvmuh.b
  3595  	case AXVMUHH:
  3596  		return 0xe90d << 15 // xvmuh.h
  3597  	case AXVMUHW:
  3598  		return 0xe90e << 15 // xvmuh.w
  3599  	case AXVMUHV:
  3600  		return 0xe90f << 15 // xvmuh.d
  3601  	case AXVMUHBU:
  3602  		return 0xe910 << 15 // xvmuh.bu
  3603  	case AXVMUHHU:
  3604  		return 0xe911 << 15 // xvmuh.hu
  3605  	case AXVMUHWU:
  3606  		return 0xe912 << 15 // xvmuh.wu
  3607  	case AXVMUHVU:
  3608  		return 0xe913 << 15 // xvmuh.du
  3609  	case AVADDF:
  3610  		return 0xe261 << 15 // vfadd.s
  3611  	case AVADDD:
  3612  		return 0xe262 << 15 // vfadd.d
  3613  	case AVSUBF:
  3614  		return 0xe265 << 15 // vfsub.s
  3615  	case AVSUBD:
  3616  		return 0xe266 << 15 // vfsub.d
  3617  	case AVMULF:
  3618  		return 0xe271 << 15 // vfmul.s
  3619  	case AVMULD:
  3620  		return 0xe272 << 15 // vfmul.d
  3621  	case AVDIVF:
  3622  		return 0xe275 << 15 // vfdiv.s
  3623  	case AVDIVD:
  3624  		return 0xe276 << 15 // vfdiv.d
  3625  	case AXVADDF:
  3626  		return 0xea61 << 15 // xvfadd.s
  3627  	case AXVADDD:
  3628  		return 0xea62 << 15 // xvfadd.d
  3629  	case AXVSUBF:
  3630  		return 0xea65 << 15 // xvfsub.s
  3631  	case AXVSUBD:
  3632  		return 0xea66 << 15 // xvfsub.d
  3633  	case AXVMULF:
  3634  		return 0xea71 << 15 // xvfmul.s
  3635  	case AXVMULD:
  3636  		return 0xea72 << 15 // xvfmul.d
  3637  	case AXVDIVF:
  3638  		return 0xea75 << 15 // xvfdiv.s
  3639  	case AXVDIVD:
  3640  		return 0xea76 << 15 // xvfdiv.d
  3641  	case AVBITCLRB:
  3642  		return 0xe218 << 15 // vbitclr.b
  3643  	case AVBITCLRH:
  3644  		return 0xe219 << 15 // vbitclr.h
  3645  	case AVBITCLRW:
  3646  		return 0xe21a << 15 // vbitclr.w
  3647  	case AVBITCLRV:
  3648  		return 0xe21b << 15 // vbitclr.d
  3649  	case AVBITSETB:
  3650  		return 0xe21c << 15 // vbitset.b
  3651  	case AVBITSETH:
  3652  		return 0xe21d << 15 // vbitset.h
  3653  	case AVBITSETW:
  3654  		return 0xe21e << 15 // vbitset.w
  3655  	case AVBITSETV:
  3656  		return 0xe21f << 15 // vbitset.d
  3657  	case AVBITREVB:
  3658  		return 0xe220 << 15 // vbitrev.b
  3659  	case AVBITREVH:
  3660  		return 0xe221 << 15 // vbitrev.h
  3661  	case AVBITREVW:
  3662  		return 0xe222 << 15 // vbitrev.w
  3663  	case AVBITREVV:
  3664  		return 0xe223 << 15 // vbitrev.d
  3665  	case AXVBITCLRB:
  3666  		return 0xea18 << 15 // xvbitclr.b
  3667  	case AXVBITCLRH:
  3668  		return 0xea19 << 15 // xvbitclr.h
  3669  	case AXVBITCLRW:
  3670  		return 0xea1a << 15 // xvbitclr.w
  3671  	case AXVBITCLRV:
  3672  		return 0xea1b << 15 // xvbitclr.d
  3673  	case AXVBITSETB:
  3674  		return 0xea1c << 15 // xvbitset.b
  3675  	case AXVBITSETH:
  3676  		return 0xea1d << 15 // xvbitset.h
  3677  	case AXVBITSETW:
  3678  		return 0xea1e << 15 // xvbitset.w
  3679  	case AXVBITSETV:
  3680  		return 0xea1f << 15 // xvbitset.d
  3681  	case AXVBITREVB:
  3682  		return 0xea20 << 15 // xvbitrev.b
  3683  	case AXVBITREVH:
  3684  		return 0xea21 << 15 // xvbitrev.h
  3685  	case AXVBITREVW:
  3686  		return 0xea22 << 15 // xvbitrev.w
  3687  	case AXVBITREVV:
  3688  		return 0xea23 << 15 // xvbitrev.d
  3689  	}
  3690  
  3691  	if a < 0 {
  3692  		c.ctxt.Diag("bad rrr opcode -%v", -a)
  3693  	} else {
  3694  		c.ctxt.Diag("bad rrr opcode %v", a)
  3695  	}
  3696  	return 0
  3697  }
  3698  
  3699  func (c *ctxt0) oprr(a obj.As) uint32 {
  3700  	switch a {
  3701  	case ACLOW:
  3702  		return 0x4 << 10 // clo.w
  3703  	case ACLZW:
  3704  		return 0x5 << 10 // clz.w
  3705  	case ACTOW:
  3706  		return 0x6 << 10 // cto.w
  3707  	case ACTZW:
  3708  		return 0x7 << 10 // ctz.w
  3709  	case ACLOV:
  3710  		return 0x8 << 10 // clo.d
  3711  	case ACLZV:
  3712  		return 0x9 << 10 // clz.d
  3713  	case ACTOV:
  3714  		return 0xa << 10 // cto.d
  3715  	case ACTZV:
  3716  		return 0xb << 10 // ctz.d
  3717  	case AREVB2H:
  3718  		return 0xc << 10 // revb.2h
  3719  	case AREVB4H:
  3720  		return 0xd << 10 // revb.4h
  3721  	case AREVB2W:
  3722  		return 0xe << 10 // revb.2w
  3723  	case AREVBV:
  3724  		return 0xf << 10 // revb.d
  3725  	case AREVH2W:
  3726  		return 0x10 << 10 // revh.2w
  3727  	case AREVHV:
  3728  		return 0x11 << 10 // revh.d
  3729  	case ABITREV4B:
  3730  		return 0x12 << 10 // bitrev.4b
  3731  	case ABITREV8B:
  3732  		return 0x13 << 10 // bitrev.8b
  3733  	case ABITREVW:
  3734  		return 0x14 << 10 // bitrev.w
  3735  	case ABITREVV:
  3736  		return 0x15 << 10 // bitrev.d
  3737  	case AEXTWH:
  3738  		return 0x16 << 10 // ext.w.h
  3739  	case AEXTWB:
  3740  		return 0x17 << 10 // ext.w.h
  3741  	case ACPUCFG:
  3742  		return 0x1b << 10
  3743  	case ARDTIMELW:
  3744  		return 0x18 << 10
  3745  	case ARDTIMEHW:
  3746  		return 0x19 << 10
  3747  	case ARDTIMED:
  3748  		return 0x1a << 10
  3749  	case ATRUNCFV:
  3750  		return 0x46a9 << 10
  3751  	case ATRUNCDV:
  3752  		return 0x46aa << 10
  3753  	case ATRUNCFW:
  3754  		return 0x46a1 << 10
  3755  	case ATRUNCDW:
  3756  		return 0x46a2 << 10
  3757  	case AMOVFV:
  3758  		return 0x46c9 << 10
  3759  	case AMOVDV:
  3760  		return 0x46ca << 10
  3761  	case AMOVVF:
  3762  		return 0x4746 << 10
  3763  	case AMOVVD:
  3764  		return 0x474a << 10
  3765  	case AMOVFW:
  3766  		return 0x46c1 << 10
  3767  	case AMOVDW:
  3768  		return 0x46c2 << 10
  3769  	case AMOVWF:
  3770  		return 0x4744 << 10
  3771  	case AMOVDF:
  3772  		return 0x4646 << 10
  3773  	case AMOVWD:
  3774  		return 0x4748 << 10
  3775  	case AMOVFD:
  3776  		return 0x4649 << 10
  3777  	case AABSF:
  3778  		return 0x4501 << 10
  3779  	case AABSD:
  3780  		return 0x4502 << 10
  3781  	case AMOVF:
  3782  		return 0x4525 << 10
  3783  	case AMOVD:
  3784  		return 0x4526 << 10
  3785  	case ANEGF:
  3786  		return 0x4505 << 10
  3787  	case ANEGD:
  3788  		return 0x4506 << 10
  3789  	case ASQRTF:
  3790  		return 0x4511 << 10
  3791  	case ASQRTD:
  3792  		return 0x4512 << 10
  3793  	case AFLOGBF:
  3794  		return 0x4509 << 10 // flogb.s
  3795  	case AFLOGBD:
  3796  		return 0x450a << 10 // flogb.d
  3797  	case AFCLASSF:
  3798  		return 0x450d << 10 // fclass.s
  3799  	case AFCLASSD:
  3800  		return 0x450e << 10 // fclass.d
  3801  	case AFFINTFW:
  3802  		return 0x4744 << 10 // ffint.s.w
  3803  	case AFFINTFV:
  3804  		return 0x4746 << 10 // ffint.s.l
  3805  	case AFFINTDW:
  3806  		return 0x4748 << 10 // ffint.d.w
  3807  	case AFFINTDV:
  3808  		return 0x474a << 10 // ffint.d.l
  3809  	case AFTINTWF:
  3810  		return 0x46c1 << 10 // ftint.w.s
  3811  	case AFTINTWD:
  3812  		return 0x46c2 << 10 // ftint.w.d
  3813  	case AFTINTVF:
  3814  		return 0x46c9 << 10 // ftint.l.s
  3815  	case AFTINTVD:
  3816  		return 0x46ca << 10 // ftint.l.d
  3817  	case AFTINTRMWF:
  3818  		return 0x4681 << 10 // ftintrm.w.s
  3819  	case AFTINTRMWD:
  3820  		return 0x4682 << 10 // ftintrm.w.d
  3821  	case AFTINTRMVF:
  3822  		return 0x4689 << 10 // ftintrm.l.s
  3823  	case AFTINTRMVD:
  3824  		return 0x468a << 10 // ftintrm.l.d
  3825  	case AFTINTRPWF:
  3826  		return 0x4691 << 10 // ftintrp.w.s
  3827  	case AFTINTRPWD:
  3828  		return 0x4692 << 10 // ftintrp.w.d
  3829  	case AFTINTRPVF:
  3830  		return 0x4699 << 10 // ftintrp.l.s
  3831  	case AFTINTRPVD:
  3832  		return 0x469a << 10 // ftintrp.l.d
  3833  	case AFTINTRZWF:
  3834  		return 0x46a1 << 10 // ftintrz.w.s
  3835  	case AFTINTRZWD:
  3836  		return 0x46a2 << 10 // ftintrz.w.d
  3837  	case AFTINTRZVF:
  3838  		return 0x46a9 << 10 // ftintrz.l.s
  3839  	case AFTINTRZVD:
  3840  		return 0x46aa << 10 // ftintrz.l.d
  3841  	case AFTINTRNEWF:
  3842  		return 0x46b1 << 10 // ftintrne.w.s
  3843  	case AFTINTRNEWD:
  3844  		return 0x46b2 << 10 // ftintrne.w.d
  3845  	case AFTINTRNEVF:
  3846  		return 0x46b9 << 10 // ftintrne.l.s
  3847  	case AFTINTRNEVD:
  3848  		return 0x46ba << 10 // ftintrne.l.d
  3849  	case AVPCNTB:
  3850  		return 0x1ca708 << 10 // vpcnt.b
  3851  	case AVPCNTH:
  3852  		return 0x1ca709 << 10 // vpcnt.h
  3853  	case AVPCNTW:
  3854  		return 0x1ca70a << 10 // vpcnt.w
  3855  	case AVPCNTV:
  3856  		return 0x1ca70b << 10 // vpcnt.v
  3857  	case AXVPCNTB:
  3858  		return 0x1da708 << 10 // xvpcnt.b
  3859  	case AXVPCNTH:
  3860  		return 0x1da709 << 10 // xvpcnt.h
  3861  	case AXVPCNTW:
  3862  		return 0x1da70a << 10 // xvpcnt.w
  3863  	case AXVPCNTV:
  3864  		return 0x1da70b << 10 // xvpcnt.v
  3865  	case AVFSQRTF:
  3866  		return 0x1ca739 << 10 // vfsqrt.s
  3867  	case AVFSQRTD:
  3868  		return 0x1ca73a << 10 // vfsqrt.d
  3869  	case AVFRECIPF:
  3870  		return 0x1ca73d << 10 // vfrecip.s
  3871  	case AVFRECIPD:
  3872  		return 0x1ca73e << 10 // vfrecip.d
  3873  	case AVFRSQRTF:
  3874  		return 0x1ca741 << 10 // vfrsqrt.s
  3875  	case AVFRSQRTD:
  3876  		return 0x1ca742 << 10 // vfrsqrt.d
  3877  	case AXVFSQRTF:
  3878  		return 0x1da739 << 10 // xvfsqrt.s
  3879  	case AXVFSQRTD:
  3880  		return 0x1da73a << 10 // xvfsqrt.d
  3881  	case AXVFRECIPF:
  3882  		return 0x1da73d << 10 // xvfrecip.s
  3883  	case AXVFRECIPD:
  3884  		return 0x1da73e << 10 // xvfrecip.d
  3885  	case AXVFRSQRTF:
  3886  		return 0x1da741 << 10 // xvfrsqrt.s
  3887  	case AXVFRSQRTD:
  3888  		return 0x1da742 << 10 // xvfrsqrt.d
  3889  	case AVNEGB:
  3890  		return 0x1ca70c << 10 // vneg.b
  3891  	case AVNEGH:
  3892  		return 0x1ca70d << 10 // vneg.h
  3893  	case AVNEGW:
  3894  		return 0x1ca70e << 10 // vneg.w
  3895  	case AVNEGV:
  3896  		return 0x1ca70f << 10 // vneg.d
  3897  	case AXVNEGB:
  3898  		return 0x1da70c << 10 // xvneg.b
  3899  	case AXVNEGH:
  3900  		return 0x1da70d << 10 // xvneg.h
  3901  	case AXVNEGW:
  3902  		return 0x1da70e << 10 // xvneg.w
  3903  	case AXVNEGV:
  3904  		return 0x1da70f << 10 // xvneg.d
  3905  	case AVFRINTRNEF:
  3906  		return 0x1ca75d << 10 // vfrintrne.s
  3907  	case AVFRINTRNED:
  3908  		return 0x1ca75e << 10 // vfrintrne.d
  3909  	case AVFRINTRZF:
  3910  		return 0x1ca759 << 10 // vfrintrz.s
  3911  	case AVFRINTRZD:
  3912  		return 0x1ca75a << 10 // vfrintrz.d
  3913  	case AVFRINTRPF:
  3914  		return 0x1ca755 << 10 // vfrintrp.s
  3915  	case AVFRINTRPD:
  3916  		return 0x1ca756 << 10 // vfrintrp.d
  3917  	case AVFRINTRMF:
  3918  		return 0x1ca751 << 10 // vfrintrm.s
  3919  	case AVFRINTRMD:
  3920  		return 0x1ca752 << 10 // vfrintrm.d
  3921  	case AVFRINTF:
  3922  		return 0x1ca74d << 10 // vfrint.s
  3923  	case AVFRINTD:
  3924  		return 0x1ca74e << 10 // vfrint.d
  3925  	case AXVFRINTRNEF:
  3926  		return 0x1da75d << 10 // xvfrintrne.s
  3927  	case AXVFRINTRNED:
  3928  		return 0x1da75e << 10 // xvfrintrne.d
  3929  	case AXVFRINTRZF:
  3930  		return 0x1da759 << 10 // xvfrintrz.s
  3931  	case AXVFRINTRZD:
  3932  		return 0x1da75a << 10 // xvfrintrz.d
  3933  	case AXVFRINTRPF:
  3934  		return 0x1da755 << 10 // xvfrintrp.s
  3935  	case AXVFRINTRPD:
  3936  		return 0x1da756 << 10 // xvfrintrp.d
  3937  	case AXVFRINTRMF:
  3938  		return 0x1da751 << 10 // xvfrintrm.s
  3939  	case AXVFRINTRMD:
  3940  		return 0x1da752 << 10 // xvfrintrm.d
  3941  	case AXVFRINTF:
  3942  		return 0x1da74d << 10 // xvfrint.s
  3943  	case AXVFRINTD:
  3944  		return 0x1da74e << 10 // xvfrint.d
  3945  	case AVFCLASSF:
  3946  		return 0x1ca735 << 10 // vfclass.s
  3947  	case AVFCLASSD:
  3948  		return 0x1ca736 << 10 // vfclass.d
  3949  	case AXVFCLASSF:
  3950  		return 0x1da735 << 10 // xvfclass.s
  3951  	case AXVFCLASSD:
  3952  		return 0x1da736 << 10 // xvfclass.d
  3953  	case AVSETEQV:
  3954  		return 0x1ca726<<10 | 0x0<<3 // vseteqz.v
  3955  	case AVSETNEV:
  3956  		return 0x1ca727<<10 | 0x0<<3 // vsetnez.v
  3957  	case AVSETANYEQB:
  3958  		return 0x1ca728<<10 | 0x0<<3 // vsetanyeqz.b
  3959  	case AVSETANYEQH:
  3960  		return 0x1ca729<<10 | 0x0<<3 // vsetanyeqz.h
  3961  	case AVSETANYEQW:
  3962  		return 0x1ca72a<<10 | 0x0<<3 // vsetanyeqz.w
  3963  	case AVSETANYEQV:
  3964  		return 0x1ca72b<<10 | 0x0<<3 // vsetanyeqz.d
  3965  	case AVSETALLNEB:
  3966  		return 0x1ca72c<<10 | 0x0<<3 // vsetallnez.b
  3967  	case AVSETALLNEH:
  3968  		return 0x1ca72d<<10 | 0x0<<3 // vsetallnez.h
  3969  	case AVSETALLNEW:
  3970  		return 0x1ca72e<<10 | 0x0<<3 // vsetallnez.w
  3971  	case AVSETALLNEV:
  3972  		return 0x1ca72f<<10 | 0x0<<3 // vsetallnez.d
  3973  	case AXVSETEQV:
  3974  		return 0x1da726<<10 | 0x0<<3 // xvseteqz.v
  3975  	case AXVSETNEV:
  3976  		return 0x1da727<<10 | 0x0<<3 // xvsetnez.v
  3977  	case AXVSETANYEQB:
  3978  		return 0x1da728<<10 | 0x0<<3 // xvsetanyeqz.b
  3979  	case AXVSETANYEQH:
  3980  		return 0x1da729<<10 | 0x0<<3 // xvsetanyeqz.h
  3981  	case AXVSETANYEQW:
  3982  		return 0x1da72a<<10 | 0x0<<3 // xvsetanyeqz.w
  3983  	case AXVSETANYEQV:
  3984  		return 0x1da72b<<10 | 0x0<<3 // xvsetanyeqz.d
  3985  	case AXVSETALLNEB:
  3986  		return 0x1da72c<<10 | 0x0<<3 // xvsetallnez.b
  3987  	case AXVSETALLNEH:
  3988  		return 0x1da72d<<10 | 0x0<<3 // xvsetallnez.h
  3989  	case AXVSETALLNEW:
  3990  		return 0x1da72e<<10 | 0x0<<3 // xvsetallnez.w
  3991  	case AXVSETALLNEV:
  3992  		return 0x1da72f<<10 | 0x0<<3 // xvsetallnez.d
  3993  	}
  3994  
  3995  	c.ctxt.Diag("bad rr opcode %v", a)
  3996  	return 0
  3997  }
  3998  
  3999  func (c *ctxt0) opi(a obj.As) uint32 {
  4000  	switch a {
  4001  	case ASYSCALL:
  4002  		return 0x56 << 15
  4003  	case ABREAK:
  4004  		return 0x54 << 15
  4005  	case ADBAR:
  4006  		return 0x70e4 << 15
  4007  	}
  4008  
  4009  	c.ctxt.Diag("bad ic opcode %v", a)
  4010  
  4011  	return 0
  4012  }
  4013  
  4014  func (c *ctxt0) opir(a obj.As) uint32 {
  4015  	switch a {
  4016  	case ALU12IW:
  4017  		return 0x0a << 25
  4018  	case ALU32ID:
  4019  		return 0x0b << 25
  4020  	case APCALAU12I:
  4021  		return 0x0d << 25
  4022  	case APCADDU12I:
  4023  		return 0x0e << 25
  4024  	}
  4025  	return 0
  4026  }
  4027  
  4028  func (c *ctxt0) opirr(a obj.As) uint32 {
  4029  	switch a {
  4030  	case AADD, AADDU:
  4031  		return 0x00a << 22
  4032  	case ASGT:
  4033  		return 0x008 << 22
  4034  	case ASGTU:
  4035  		return 0x009 << 22
  4036  	case AAND:
  4037  		return 0x00d << 22
  4038  	case AOR:
  4039  		return 0x00e << 22
  4040  	case ALU52ID:
  4041  		return 0x00c << 22
  4042  	case AXOR:
  4043  		return 0x00f << 22
  4044  	case ASLL:
  4045  		return 0x00081 << 15
  4046  	case ASRL:
  4047  		return 0x00089 << 15
  4048  	case ASRA:
  4049  		return 0x00091 << 15
  4050  	case AROTR:
  4051  		return 0x00099 << 15
  4052  	case AADDV:
  4053  		return 0x00b << 22
  4054  	case AADDVU:
  4055  		return 0x00b << 22
  4056  	case AADDV16:
  4057  		return 0x4 << 26
  4058  
  4059  	case AJMP:
  4060  		return 0x14 << 26
  4061  	case AJAL:
  4062  		return 0x15 << 26
  4063  
  4064  	case AJIRL:
  4065  		return 0x13 << 26
  4066  	case ABLTU:
  4067  		return 0x1a << 26
  4068  	case ABLT, ABLTZ, ABGTZ:
  4069  		return 0x18 << 26
  4070  	case ABGEU:
  4071  		return 0x1b << 26
  4072  	case ABGE, ABGEZ, ABLEZ:
  4073  		return 0x19 << 26
  4074  	case -ABEQ: // beqz
  4075  		return 0x10 << 26
  4076  	case -ABNE: // bnez
  4077  		return 0x11 << 26
  4078  	case ABEQ:
  4079  		return 0x16 << 26
  4080  	case ABNE:
  4081  		return 0x17 << 26
  4082  	case ABFPT:
  4083  		return 0x12<<26 | 0x1<<8
  4084  	case ABFPF:
  4085  		return 0x12<<26 | 0x0<<8
  4086  	case APRELDX:
  4087  		return 0x07058 << 15 // preldx
  4088  	case AMOVB,
  4089  		AMOVBU:
  4090  		return 0x0a4 << 22
  4091  	case AMOVH,
  4092  		AMOVHU:
  4093  		return 0x0a5 << 22
  4094  	case AMOVW,
  4095  		AMOVWU:
  4096  		return 0x0a6 << 22
  4097  	case AMOVV:
  4098  		return 0x0a7 << 22
  4099  	case AMOVF:
  4100  		return 0x0ad << 22
  4101  	case AMOVD:
  4102  		return 0x0af << 22
  4103  	case AMOVVP:
  4104  		return 0x27 << 24 // stptr.d
  4105  	case AMOVWP:
  4106  		return 0x25 << 24 // stptr.w
  4107  	case -AMOVB:
  4108  		return 0x0a0 << 22
  4109  	case -AMOVBU:
  4110  		return 0x0a8 << 22
  4111  	case -AMOVH:
  4112  		return 0x0a1 << 22
  4113  	case -AMOVHU:
  4114  		return 0x0a9 << 22
  4115  	case -AMOVW:
  4116  		return 0x0a2 << 22
  4117  	case -AMOVWU:
  4118  		return 0x0aa << 22
  4119  	case -AMOVV:
  4120  		return 0x0a3 << 22
  4121  	case -AMOVF:
  4122  		return 0x0ac << 22
  4123  	case -AMOVD:
  4124  		return 0x0ae << 22
  4125  	case -AMOVVP:
  4126  		return 0x26 << 24 // ldptr.d
  4127  	case -AMOVWP:
  4128  		return 0x24 << 24 // ldptr.w
  4129  	case -AVMOVQ:
  4130  		return 0x0b0 << 22 // vld
  4131  	case -AXVMOVQ:
  4132  		return 0x0b2 << 22 // xvld
  4133  	case AVMOVQ:
  4134  		return 0x0b1 << 22 // vst
  4135  	case AXVMOVQ:
  4136  		return 0x0b3 << 22 // xvst
  4137  	case ASLLV:
  4138  		return 0x0041 << 16
  4139  	case ASRLV:
  4140  		return 0x0045 << 16
  4141  	case ASRAV:
  4142  		return 0x0049 << 16
  4143  	case AROTRV:
  4144  		return 0x004d << 16
  4145  	case -ALL:
  4146  		return 0x020 << 24
  4147  	case -ALLV:
  4148  		return 0x022 << 24
  4149  	case ASC:
  4150  		return 0x021 << 24
  4151  	case ASCV:
  4152  		return 0x023 << 24
  4153  	case AVANDB:
  4154  		return 0x1CF4 << 18 // vandi.b
  4155  	case AVORB:
  4156  		return 0x1CF5 << 18 // vori.b
  4157  	case AVXORB:
  4158  		return 0x1CF6 << 18 // xori.b
  4159  	case AVNORB:
  4160  		return 0x1CF7 << 18 // xnori.b
  4161  	case AXVANDB:
  4162  		return 0x1DF4 << 18 // xvandi.b
  4163  	case AXVORB:
  4164  		return 0x1DF5 << 18 // xvori.b
  4165  	case AXVXORB:
  4166  		return 0x1DF6 << 18 // xvxori.b
  4167  	case AXVNORB:
  4168  		return 0x1DF7 << 18 // xvnor.b
  4169  	case AVSEQB:
  4170  		return 0x0E500 << 15 //vseqi.b
  4171  	case AVSEQH:
  4172  		return 0x0E501 << 15 // vseqi.h
  4173  	case AVSEQW:
  4174  		return 0x0E502 << 15 //vseqi.w
  4175  	case AVSEQV:
  4176  		return 0x0E503 << 15 //vseqi.d
  4177  	case AXVSEQB:
  4178  		return 0x0ED00 << 15 //xvseqi.b
  4179  	case AXVSEQH:
  4180  		return 0x0ED01 << 15 // xvseqi.h
  4181  	case AXVSEQW:
  4182  		return 0x0ED02 << 15 // xvseqi.w
  4183  	case AXVSEQV:
  4184  		return 0x0ED03 << 15 // xvseqi.d
  4185  	case AVROTRB:
  4186  		return 0x1ca8<<18 | 0x1<<13 // vrotri.b
  4187  	case AVROTRH:
  4188  		return 0x1ca8<<18 | 0x1<<14 // vrotri.h
  4189  	case AVROTRW:
  4190  		return 0x1ca8<<18 | 0x1<<15 // vrotri.w
  4191  	case AVROTRV:
  4192  		return 0x1ca8<<18 | 0x1<<16 // vrotri.d
  4193  	case AXVROTRB:
  4194  		return 0x1da8<<18 | 0x1<<13 // xvrotri.b
  4195  	case AXVROTRH:
  4196  		return 0x1da8<<18 | 0x1<<14 // xvrotri.h
  4197  	case AXVROTRW:
  4198  		return 0x1da8<<18 | 0x1<<15 // xvrotri.w
  4199  	case AXVROTRV:
  4200  		return 0x1da8<<18 | 0x1<<16 // xvrotri.d
  4201  	case AVSLLB:
  4202  		return 0x1ccb<<18 | 0x1<<13 // vslli.b
  4203  	case AVSLLH:
  4204  		return 0x1ccb<<18 | 0x1<<14 // vslli.h
  4205  	case AVSLLW:
  4206  		return 0x1ccb<<18 | 0x1<<15 // vslli.w
  4207  	case AVSLLV:
  4208  		return 0x1ccb<<18 | 0x1<<16 // vslli.d
  4209  	case AVSRLB:
  4210  		return 0x1ccc<<18 | 0x1<<13 // vsrli.b
  4211  	case AVSRLH:
  4212  		return 0x1ccc<<18 | 0x1<<14 // vsrli.h
  4213  	case AVSRLW:
  4214  		return 0x1ccc<<18 | 0x1<<15 // vsrli.w
  4215  	case AVSRLV:
  4216  		return 0x1ccc<<18 | 0x1<<16 // vsrli.d
  4217  	case AVSRAB:
  4218  		return 0x1ccd<<18 | 0x1<<13 // vsrai.b
  4219  	case AVSRAH:
  4220  		return 0x1ccd<<18 | 0x1<<14 // vsrai.h
  4221  	case AVSRAW:
  4222  		return 0x1ccd<<18 | 0x1<<15 // vsrai.w
  4223  	case AVSRAV:
  4224  		return 0x1ccd<<18 | 0x1<<16 // vsrai.d
  4225  	case AXVSLLB:
  4226  		return 0x1dcb<<18 | 0x1<<13 // xvslli.b
  4227  	case AXVSLLH:
  4228  		return 0x1dcb<<18 | 0x1<<14 // xvslli.h
  4229  	case AXVSLLW:
  4230  		return 0x1dcb<<18 | 0x1<<15 // xvslli.w
  4231  	case AXVSLLV:
  4232  		return 0x1dcb<<18 | 0x1<<16 // xvslli.d
  4233  	case AXVSRLB:
  4234  		return 0x1dcc<<18 | 0x1<<13 // xvsrli.b
  4235  	case AXVSRLH:
  4236  		return 0x1dcc<<18 | 0x1<<14 // xvsrli.h
  4237  	case AXVSRLW:
  4238  		return 0x1dcc<<18 | 0x1<<15 // xvsrli.w
  4239  	case AXVSRLV:
  4240  		return 0x1dcc<<18 | 0x1<<16 // xvsrli.d
  4241  	case AXVSRAB:
  4242  		return 0x1dcd<<18 | 0x1<<13 // xvsrai.b
  4243  	case AXVSRAH:
  4244  		return 0x1dcd<<18 | 0x1<<14 // xvsrai.h
  4245  	case AXVSRAW:
  4246  		return 0x1dcd<<18 | 0x1<<15 // xvsrai.w
  4247  	case AXVSRAV:
  4248  		return 0x1dcd<<18 | 0x1<<16 // xvsrai.d
  4249  	case AVADDBU:
  4250  		return 0xe514 << 15 // vaddi.bu
  4251  	case AVADDHU:
  4252  		return 0xe515 << 15 // vaddi.hu
  4253  	case AVADDWU:
  4254  		return 0xe516 << 15 // vaddi.wu
  4255  	case AVADDVU:
  4256  		return 0xe517 << 15 // vaddi.du
  4257  	case AVSUBBU:
  4258  		return 0xe518 << 15 // vsubi.bu
  4259  	case AVSUBHU:
  4260  		return 0xe519 << 15 // vsubi.hu
  4261  	case AVSUBWU:
  4262  		return 0xe51a << 15 // vsubi.wu
  4263  	case AVSUBVU:
  4264  		return 0xe51b << 15 // vsubi.du
  4265  	case AXVADDBU:
  4266  		return 0xed14 << 15 // xvaddi.bu
  4267  	case AXVADDHU:
  4268  		return 0xed15 << 15 // xvaddi.hu
  4269  	case AXVADDWU:
  4270  		return 0xed16 << 15 // xvaddi.wu
  4271  	case AXVADDVU:
  4272  		return 0xed17 << 15 // xvaddi.du
  4273  	case AXVSUBBU:
  4274  		return 0xed18 << 15 // xvsubi.bu
  4275  	case AXVSUBHU:
  4276  		return 0xed19 << 15 // xvsubi.hu
  4277  	case AXVSUBWU:
  4278  		return 0xed1a << 15 // xvsubi.wu
  4279  	case AXVSUBVU:
  4280  		return 0xed1b << 15 // xvsubi.du
  4281  	case AVSHUF4IB:
  4282  		return 0x1ce4 << 18 // vshuf4i.b
  4283  	case AVSHUF4IH:
  4284  		return 0x1ce5 << 18 // vshuf4i.h
  4285  	case AVSHUF4IW:
  4286  		return 0x1ce6 << 18 // vshuf4i.w
  4287  	case AVSHUF4IV:
  4288  		return 0x1ce7 << 18 // vshuf4i.d
  4289  	case AXVSHUF4IB:
  4290  		return 0x1de4 << 18 // xvshuf4i.b
  4291  	case AXVSHUF4IH:
  4292  		return 0x1de5 << 18 // xvshuf4i.h
  4293  	case AXVSHUF4IW:
  4294  		return 0x1de6 << 18 // xvshuf4i.w
  4295  	case AXVSHUF4IV:
  4296  		return 0x1de7 << 18 // xvshuf4i.d
  4297  	case AVBITCLRB:
  4298  		return 0x1CC4<<18 | 0x1<<13 // vbitclri.b
  4299  	case AVBITCLRH:
  4300  		return 0x1CC4<<18 | 0x1<<14 // vbitclri.h
  4301  	case AVBITCLRW:
  4302  		return 0x1CC4<<18 | 0x1<<15 // vbitclri.w
  4303  	case AVBITCLRV:
  4304  		return 0x1CC4<<18 | 0x1<<16 // vbitclri.d
  4305  	case AVBITSETB:
  4306  		return 0x1CC5<<18 | 0x1<<13 // vbitseti.b
  4307  	case AVBITSETH:
  4308  		return 0x1CC5<<18 | 0x1<<14 // vbitseti.h
  4309  	case AVBITSETW:
  4310  		return 0x1CC5<<18 | 0x1<<15 // vbitseti.w
  4311  	case AVBITSETV:
  4312  		return 0x1CC5<<18 | 0x1<<16 // vbitseti.d
  4313  	case AVBITREVB:
  4314  		return 0x1CC6<<18 | 0x1<<13 // vbitrevi.b
  4315  	case AVBITREVH:
  4316  		return 0x1CC6<<18 | 0x1<<14 // vbitrevi.h
  4317  	case AVBITREVW:
  4318  		return 0x1CC6<<18 | 0x1<<15 // vbitrevi.w
  4319  	case AVBITREVV:
  4320  		return 0x1CC6<<18 | 0x1<<16 // vbitrevi.d
  4321  	case AXVBITCLRB:
  4322  		return 0x1DC4<<18 | 0x1<<13 // xvbitclri.b
  4323  	case AXVBITCLRH:
  4324  		return 0x1DC4<<18 | 0x1<<14 // xvbitclri.h
  4325  	case AXVBITCLRW:
  4326  		return 0x1DC4<<18 | 0x1<<15 // xvbitclri.w
  4327  	case AXVBITCLRV:
  4328  		return 0x1DC4<<18 | 0x1<<16 // xvbitclri.d
  4329  	case AXVBITSETB:
  4330  		return 0x1DC5<<18 | 0x1<<13 // xvbitseti.b
  4331  	case AXVBITSETH:
  4332  		return 0x1DC5<<18 | 0x1<<14 // xvbitseti.h
  4333  	case AXVBITSETW:
  4334  		return 0x1DC5<<18 | 0x1<<15 // xvbitseti.w
  4335  	case AXVBITSETV:
  4336  		return 0x1DC5<<18 | 0x1<<16 // xvbitseti.d
  4337  	case AXVBITREVB:
  4338  		return 0x1DC6<<18 | 0x1<<13 // xvbitrevi.b
  4339  	case AXVBITREVH:
  4340  		return 0x1DC6<<18 | 0x1<<14 // xvbitrevi.h
  4341  	case AXVBITREVW:
  4342  		return 0x1DC6<<18 | 0x1<<15 // xvbitrevi.w
  4343  	case AXVBITREVV:
  4344  		return 0x1DC6<<18 | 0x1<<16 // xvbitrevi.d
  4345  	}
  4346  
  4347  	if a < 0 {
  4348  		c.ctxt.Diag("bad irr opcode -%v", -a)
  4349  	} else {
  4350  		c.ctxt.Diag("bad irr opcode %v", a)
  4351  	}
  4352  	return 0
  4353  }
  4354  
  4355  func (c *ctxt0) opirrr(a obj.As) uint32 {
  4356  	switch a {
  4357  	case AALSLW:
  4358  		return 0x2 << 17 // alsl.w
  4359  	case AALSLWU:
  4360  		return 0x3 << 17 // alsl.wu
  4361  	case AALSLV:
  4362  		return 0x16 << 17 // alsl.d
  4363  	}
  4364  
  4365  	return 0
  4366  }
  4367  
  4368  func (c *ctxt0) opirir(a obj.As) uint32 {
  4369  	switch a {
  4370  	case ABSTRINSW:
  4371  		return 0x3<<21 | 0x0<<15 // bstrins.w
  4372  	case ABSTRINSV:
  4373  		return 0x2 << 22 // bstrins.d
  4374  	case ABSTRPICKW:
  4375  		return 0x3<<21 | 0x1<<15 // bstrpick.w
  4376  	case ABSTRPICKV:
  4377  		return 0x3 << 22 // bstrpick.d
  4378  	}
  4379  
  4380  	return 0
  4381  }
  4382  
  4383  func (c *ctxt0) opiir(a obj.As) uint32 {
  4384  	switch a {
  4385  	case APRELD:
  4386  		return 0x0AB << 22 // preld
  4387  	}
  4388  
  4389  	return 0
  4390  }
  4391  
  4392  func (c *ctxt0) specialFpMovInst(a obj.As, fclass int, tclass int) uint32 {
  4393  	switch a {
  4394  	case AMOVV:
  4395  		switch fclass {
  4396  		case C_REG:
  4397  			switch tclass {
  4398  			case C_FREG:
  4399  				return 0x452a << 10 // movgr2fr.d
  4400  			case C_FCCREG:
  4401  				return 0x4536 << 10 // movgr2cf
  4402  			case C_FCSRREG:
  4403  				return 0x4530 << 10 // movgr2fcsr
  4404  			}
  4405  		case C_FREG:
  4406  			switch tclass {
  4407  			case C_REG:
  4408  				return 0x452e << 10 // movfr2gr.d
  4409  			case C_FCCREG:
  4410  				return 0x4534 << 10 // movfr2cf
  4411  			}
  4412  		case C_FCCREG:
  4413  			switch tclass {
  4414  			case C_REG:
  4415  				return 0x4537 << 10 // movcf2gr
  4416  			case C_FREG:
  4417  				return 0x4535 << 10 // movcf2fr
  4418  			}
  4419  		case C_FCSRREG:
  4420  			switch tclass {
  4421  			case C_REG:
  4422  				return 0x4532 << 10 // movfcsr2gr
  4423  			}
  4424  		}
  4425  
  4426  	case AMOVW:
  4427  		switch fclass {
  4428  		case C_REG:
  4429  			switch tclass {
  4430  			case C_FREG:
  4431  				return 0x4529 << 10 // movgr2fr.w
  4432  			}
  4433  		case C_FREG:
  4434  			switch tclass {
  4435  			case C_REG:
  4436  				return 0x452d << 10 // movfr2gr.s
  4437  			}
  4438  		}
  4439  	}
  4440  
  4441  	c.ctxt.Diag("bad class combination: %s %d,%d\n", a, fclass, tclass)
  4442  
  4443  	return 0
  4444  }
  4445  
  4446  func (c *ctxt0) specialLsxMovInst(a obj.As, fReg, tReg int16, offset_flag bool) (op_code, index_mask uint32) {
  4447  	farng := (fReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
  4448  	tarng := (tReg >> EXT_TYPE_SHIFT) & EXT_TYPE_MASK
  4449  	fclass := c.rclass(fReg)
  4450  	tclass := c.rclass(tReg)
  4451  
  4452  	switch fclass | (tclass << 16) {
  4453  	case C_REG | (C_ELEM << 16):
  4454  		// vmov Rn, Vd.<T>[index]
  4455  		switch a {
  4456  		case AVMOVQ:
  4457  			switch tarng {
  4458  			case ARNG_B:
  4459  				return (0x01CBAE << 14), 0xf // vinsgr2vr.b
  4460  			case ARNG_H:
  4461  				return (0x03975E << 13), 0x7 // vinsgr2vr.h
  4462  			case ARNG_W:
  4463  				return (0x072EBE << 12), 0x3 // vinsgr2vr.w
  4464  			case ARNG_V:
  4465  				return (0x0E5D7E << 11), 0x1 // vinsgr2vr.d
  4466  			}
  4467  		case AXVMOVQ:
  4468  			switch tarng {
  4469  			case ARNG_W:
  4470  				return (0x03B75E << 13), 0x7 // xvinsgr2vr.w
  4471  			case ARNG_V:
  4472  				return (0x076EBE << 12), 0x3 // xvinsgr2vr.d
  4473  			}
  4474  		}
  4475  
  4476  	case C_ELEM | (C_REG << 16):
  4477  		// vmov Vd.<T>[index], Rn
  4478  		switch a {
  4479  		case AVMOVQ:
  4480  			switch farng {
  4481  			case ARNG_B:
  4482  				return (0x01CBBE << 14), 0xf // vpickve2gr.b
  4483  			case ARNG_H:
  4484  				return (0x03977E << 13), 0x7 // vpickve2gr.h
  4485  			case ARNG_W:
  4486  				return (0x072EFE << 12), 0x3 // vpickve2gr.w
  4487  			case ARNG_V:
  4488  				return (0x0E5DFE << 11), 0x1 // vpickve2gr.d
  4489  			case ARNG_BU:
  4490  				return (0x01CBCE << 14), 0xf // vpickve2gr.bu
  4491  			case ARNG_HU:
  4492  				return (0x03979E << 13), 0x7 // vpickve2gr.hu
  4493  			case ARNG_WU:
  4494  				return (0x072F3E << 12), 0x3 // vpickve2gr.wu
  4495  			case ARNG_VU:
  4496  				return (0x0E5E7E << 11), 0x1 // vpickve2gr.du
  4497  			}
  4498  		case AXVMOVQ:
  4499  			switch farng {
  4500  			case ARNG_W:
  4501  				return (0x03B77E << 13), 0x7 // xvpickve2gr.w
  4502  			case ARNG_V:
  4503  				return (0x076EFE << 12), 0x3 // xvpickve2gr.d
  4504  			case ARNG_WU:
  4505  				return (0x03B79E << 13), 0x7 // xvpickve2gr.wu
  4506  			case ARNG_VU:
  4507  				return (0x076F3E << 12), 0x3 // xvpickve2gr.du
  4508  			}
  4509  		}
  4510  
  4511  	case C_REG | (C_ARNG << 16):
  4512  		switch {
  4513  		case offset_flag:
  4514  			// vmov offset(vj), vd.<T>
  4515  			switch a {
  4516  			case AVMOVQ:
  4517  				switch tarng {
  4518  				case ARNG_16B:
  4519  					return (0xC2 << 22), 0x0 // vldrepl.b
  4520  				case ARNG_8H:
  4521  					return (0x182 << 21), 0x0 // vldrepl.h
  4522  				case ARNG_4W:
  4523  					return (0x302 << 20), 0x0 // vldrepl.w
  4524  				case ARNG_2V:
  4525  					return (0x602 << 19), 0x0 // vldrepl.d
  4526  				}
  4527  			case AXVMOVQ:
  4528  				switch tarng {
  4529  				case ARNG_32B:
  4530  					return (0xCA << 22), 0x0 // xvldrepl.b
  4531  				case ARNG_16H:
  4532  					return (0x192 << 21), 0x0 // xvldrepl.h
  4533  				case ARNG_8W:
  4534  					return (0x322 << 20), 0x0 // xvldrepl.w
  4535  				case ARNG_4V:
  4536  					return (0x642 << 19), 0x0 // xvldrepl.d
  4537  				}
  4538  			}
  4539  		default:
  4540  			// vmov Rn, Vd.<T>
  4541  			switch a {
  4542  			case AVMOVQ:
  4543  				switch tarng {
  4544  				case ARNG_16B:
  4545  					return (0x1CA7C0 << 10), 0x0 // vreplgr2vr.b
  4546  				case ARNG_8H:
  4547  					return (0x1CA7C1 << 10), 0x0 // vreplgr2vr.h
  4548  				case ARNG_4W:
  4549  					return (0x1CA7C2 << 10), 0x0 // vreplgr2vr.w
  4550  				case ARNG_2V:
  4551  					return (0x1CA7C3 << 10), 0x0 // vreplgr2vr.d
  4552  				}
  4553  			case AXVMOVQ:
  4554  				switch tarng {
  4555  				case ARNG_32B:
  4556  					return (0x1DA7C0 << 10), 0x0 // xvreplgr2vr.b
  4557  				case ARNG_16H:
  4558  					return (0x1DA7C1 << 10), 0x0 // xvreplgr2vr.h
  4559  				case ARNG_8W:
  4560  					return (0x1DA7C2 << 10), 0x0 // xvreplgr2vr.w
  4561  				case ARNG_4V:
  4562  					return (0x1DA7C3 << 10), 0x0 // xvreplgr2vr.d
  4563  				}
  4564  			}
  4565  		}
  4566  
  4567  	case C_XREG | (C_ARNG << 16):
  4568  		// vmov  xj, xd.<T>
  4569  		switch a {
  4570  		case AVMOVQ:
  4571  			return 0, 0 // unsupported op
  4572  		case AXVMOVQ:
  4573  			switch tarng {
  4574  			case ARNG_32B:
  4575  				return (0x1DC1C0 << 10), 0x0 // xvreplve0.b
  4576  			case ARNG_16H:
  4577  				return (0x1DC1E0 << 10), 0x0 // xvreplve0.h
  4578  			case ARNG_8W:
  4579  				return (0x1DC1F0 << 10), 0x0 // xvreplve0.w
  4580  			case ARNG_4V:
  4581  				return (0x1DC1F8 << 10), 0x0 // xvreplve0.d
  4582  			case ARNG_2Q:
  4583  				return (0x1DC1FC << 10), 0x0 // xvreplve0.q
  4584  			}
  4585  		}
  4586  
  4587  	case C_XREG | (C_ELEM << 16):
  4588  		// vmov  xj, xd.<T>[index]
  4589  		switch a {
  4590  		case AVMOVQ:
  4591  			return 0, 0 // unsupported op
  4592  		case AXVMOVQ:
  4593  			switch tarng {
  4594  			case ARNG_W:
  4595  				return (0x03B7FE << 13), 0x7 // xvinsve0.w
  4596  			case ARNG_V:
  4597  				return (0x076FFE << 12), 0x3 // xvinsve0.d
  4598  			}
  4599  		}
  4600  
  4601  	case C_ELEM | (C_XREG << 16):
  4602  		// vmov  xj.<T>[index], xd
  4603  		switch a {
  4604  		case AVMOVQ:
  4605  			return 0, 0 // unsupported op
  4606  		case AXVMOVQ:
  4607  			switch farng {
  4608  			case ARNG_W:
  4609  				return (0x03B81E << 13), 0x7 // xvpickve.w
  4610  			case ARNG_V:
  4611  				return (0x07703E << 12), 0x3 // xvpickve.d
  4612  			}
  4613  		}
  4614  
  4615  	case C_ELEM | (C_ARNG << 16):
  4616  		// vmov  vj.<T>[index], vd.<T>
  4617  		switch a {
  4618  		case AVMOVQ:
  4619  			switch int32(farng) | (int32(tarng) << 16) {
  4620  			case int32(ARNG_B) | (int32(ARNG_16B) << 16):
  4621  				return (0x01CBDE << 14), 0xf // vreplvei.b
  4622  			case int32(ARNG_H) | (int32(ARNG_8H) << 16):
  4623  				return (0x0397BE << 13), 0x7 // vreplvei.h
  4624  			case int32(ARNG_W) | (int32(ARNG_4W) << 16):
  4625  				return (0x072F7E << 12), 0x3 // vreplvei.w
  4626  			case int32(ARNG_V) | (int32(ARNG_2V) << 16):
  4627  				return (0x0E5EFE << 11), 0x1 // vreplvei.d
  4628  			}
  4629  		case AXVMOVQ:
  4630  			return 0, 0 // unsupported op
  4631  		}
  4632  	}
  4633  
  4634  	return 0, 0
  4635  }
  4636  
  4637  func vshift(a obj.As) bool {
  4638  	switch a {
  4639  	case ASLLV,
  4640  		ASRLV,
  4641  		ASRAV,
  4642  		AROTRV:
  4643  		return true
  4644  	}
  4645  	return false
  4646  }
  4647  

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