Text file src/simd/archsimd/_gen/simdgen/ops/BitwiseLogic/go_arm64.yaml

     1  !sum
     2  - go: And
     3    asm: "VAND"
     4    in:
     5    - &any
     6      go: $t
     7    - *any
     8    out:
     9    - *any
    10  - go: Or
    11    asm: "VORR"
    12    in:
    13    - *any
    14    - *any
    15    out:
    16    - *any
    17  - go: Xor
    18    asm: "VEOR"
    19    in:
    20    - *any
    21    - *any
    22    out:
    23    - *any
    24  - go: AndNot
    25    asm: "VBIC"
    26    in:
    27    - *any
    28    - *any
    29    out:
    30    - *any
    31  - go: OrNot
    32    asm: "VORN"
    33    in:
    34    - *any
    35    - *any
    36    out:
    37    - *any
    38  - go: Not
    39    asm: "VNOT"
    40    in:
    41    - *any
    42    out:
    43    - *any
    44  

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