Text file src/simd/archsimd/_gen/simdgen/ops/Mul/go_sve.yaml

     1  !sum
     2  # Mul — integer multiply (low half), ZMUL. The unpredicated vector encoding is
     3  # SVE2; the merging-predicated sibling is baseline SVE.
     4  - go: Mul
     5    asm: "ZMUL"
     6    in:
     7    - &int
     8      go: $t
     9      base: int
    10    - *int
    11    out:
    12    - *int
    13  
    14  - go: Mul
    15    asm: "ZMUL"
    16    in:
    17    - &uint
    18      go: $t
    19      base: uint
    20    - *uint
    21    out:
    22    - *uint
    23  
    24  # Mul — floating-point multiply, ZFMUL (baseline SVE, both forms).
    25  - go: Mul
    26    asm: "ZFMUL"
    27    in:
    28    - &float
    29      go: $t
    30      base: float
    31    - *float
    32    out:
    33    - *float
    34  
    35  # MulHigh — integer multiply returning the high half, ZSMULH/ZUMULH. Like ZMUL,
    36  # the unpredicated encodings are SVE2 and the predicated siblings baseline SVE.
    37  - go: MulHigh
    38    asm: "ZSMULH"
    39    in:
    40    - *int
    41    - *int
    42    out:
    43    - *int
    44  
    45  - go: MulHigh
    46    asm: "ZUMULH"
    47    in:
    48    - *uint
    49    - *uint
    50    out:
    51    - *uint
    52  

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