Source file src/vendor/golang.org/x/sys/cpu/cpu.go
1 // Copyright 2018 The Go Authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style 3 // license that can be found in the LICENSE file. 4 5 // Package cpu implements processor feature detection for 6 // various CPU architectures. 7 package cpu 8 9 import ( 10 "os" 11 "strings" 12 ) 13 14 // Initialized reports whether the CPU features were initialized. 15 // 16 // For some GOOS/GOARCH combinations initialization of the CPU features depends 17 // on reading an operating specific file, e.g. /proc/self/auxv on linux/arm 18 // Initialized will report false if reading the file fails. 19 var Initialized bool 20 21 // CacheLinePad is used to pad structs to avoid false sharing. 22 type CacheLinePad struct{ _ [cacheLineSize]byte } 23 24 // X86 contains the supported CPU features of the 25 // current X86/AMD64 platform. If the current platform 26 // is not X86/AMD64 then all feature flags are false. 27 // 28 // X86 is padded to avoid false sharing. Further the HasAVX 29 // and HasAVX2 are only set if the OS supports XMM and YMM 30 // registers in addition to the CPUID feature bit being set. 31 var X86 struct { 32 _ CacheLinePad 33 HasAES bool // AES hardware implementation (AES NI) 34 HasADX bool // Multi-precision add-carry instruction extensions 35 HasAVX bool // Advanced vector extension 36 HasAVX2 bool // Advanced vector extension 2 37 HasAVX512 bool // Advanced vector extension 512 38 HasAVX512F bool // Advanced vector extension 512 Foundation Instructions 39 HasAVX512CD bool // Advanced vector extension 512 Conflict Detection Instructions 40 HasAVX512ER bool // Advanced vector extension 512 Exponential and Reciprocal Instructions 41 HasAVX512PF bool // Advanced vector extension 512 Prefetch Instructions 42 HasAVX512VL bool // Advanced vector extension 512 Vector Length Extensions 43 HasAVX512BW bool // Advanced vector extension 512 Byte and Word Instructions 44 HasAVX512DQ bool // Advanced vector extension 512 Doubleword and Quadword Instructions 45 HasAVX512IFMA bool // Advanced vector extension 512 Integer Fused Multiply Add 46 HasAVX512VBMI bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 47 HasAVX5124VNNIW bool // Advanced vector extension 512 Vector Neural Network Instructions Word variable precision 48 HasAVX5124FMAPS bool // Advanced vector extension 512 Fused Multiply Accumulation Packed Single precision 49 HasAVX512VPOPCNTDQ bool // Advanced vector extension 512 Double and quad word population count instructions 50 HasAVX512VPCLMULQDQ bool // Advanced vector extension 512 Vector carry-less multiply operations 51 HasAVX512VNNI bool // Advanced vector extension 512 Vector Neural Network Instructions 52 HasAVX512GFNI bool // Advanced vector extension 512 Galois field New Instructions 53 HasAVX512VAES bool // Advanced vector extension 512 Vector AES instructions 54 HasAVX512VBMI2 bool // Advanced vector extension 512 Vector Byte Manipulation Instructions 2 55 HasAVX512BITALG bool // Advanced vector extension 512 Bit Algorithms 56 HasAVX512BF16 bool // Advanced vector extension 512 BFloat16 Instructions 57 HasAMXTile bool // Advanced Matrix Extension Tile instructions 58 HasAMXInt8 bool // Advanced Matrix Extension Int8 instructions 59 HasAMXBF16 bool // Advanced Matrix Extension BFloat16 instructions 60 HasBMI1 bool // Bit manipulation instruction set 1 61 HasBMI2 bool // Bit manipulation instruction set 2 62 HasCX16 bool // Compare and exchange 16 Bytes 63 HasERMS bool // Enhanced REP for MOVSB and STOSB 64 HasFMA bool // Fused-multiply-add instructions 65 HasOSXSAVE bool // OS supports XSAVE/XRESTOR for saving/restoring XMM registers. 66 HasPCLMULQDQ bool // PCLMULQDQ instruction - most often used for AES-GCM 67 HasPOPCNT bool // Hamming weight instruction POPCNT. 68 HasRDRAND bool // RDRAND instruction (on-chip random number generator) 69 HasRDSEED bool // RDSEED instruction (on-chip random number generator) 70 HasSSE2 bool // Streaming SIMD extension 2 (always available on amd64) 71 HasSSE3 bool // Streaming SIMD extension 3 72 HasSSSE3 bool // Supplemental streaming SIMD extension 3 73 HasSSE41 bool // Streaming SIMD extension 4 and 4.1 74 HasSSE42 bool // Streaming SIMD extension 4 and 4.2 75 HasAVXIFMA bool // Advanced vector extension Integer Fused Multiply Add 76 HasAVXVNNI bool // Advanced vector extension Vector Neural Network Instructions 77 HasAVXVNNIInt8 bool // Advanced vector extension Vector Neural Network Int8 instructions 78 _ CacheLinePad 79 } 80 81 // ARM64 contains the supported CPU features of the 82 // current ARMv8(aarch64) platform. If the current platform 83 // is not arm64 then all feature flags are false. 84 var ARM64 struct { 85 _ CacheLinePad 86 HasFP bool // Floating-point instruction set (always available) 87 HasASIMD bool // Advanced SIMD (always available) 88 HasEVTSTRM bool // Event stream support 89 HasAES bool // AES hardware implementation 90 HasPMULL bool // Polynomial multiplication instruction set 91 HasSHA1 bool // SHA1 hardware implementation 92 HasSHA2 bool // SHA2 hardware implementation 93 HasCRC32 bool // CRC32 hardware implementation 94 HasATOMICS bool // Atomic memory operation instruction set 95 HasFPHP bool // Half precision floating-point instruction set 96 HasASIMDHP bool // Advanced SIMD half precision instruction set 97 HasCPUID bool // CPUID identification scheme registers 98 HasASIMDRDM bool // Rounding double multiply add/subtract instruction set 99 HasJSCVT bool // Javascript conversion from floating-point to integer 100 HasFCMA bool // Floating-point multiplication and addition of complex numbers 101 HasLRCPC bool // Release Consistent processor consistent support 102 HasDCPOP bool // Persistent memory support 103 HasSHA3 bool // SHA3 hardware implementation 104 HasSM3 bool // SM3 hardware implementation 105 HasSM4 bool // SM4 hardware implementation 106 HasASIMDDP bool // Advanced SIMD double precision instruction set 107 HasSHA512 bool // SHA512 hardware implementation 108 HasSVE bool // Scalable Vector Extensions 109 HasSVE2 bool // Scalable Vector Extensions 2 110 HasASIMDFHM bool // Advanced SIMD multiplication FP16 to FP32 111 HasDIT bool // Data Independent Timing support 112 HasI8MM bool // Advanced SIMD Int8 matrix multiplication instructions 113 _ CacheLinePad 114 } 115 116 // ARM contains the supported CPU features of the current ARM (32-bit) platform. 117 // All feature flags are false if: 118 // 1. the current platform is not arm, or 119 // 2. the current operating system is not Linux. 120 var ARM struct { 121 _ CacheLinePad 122 HasSWP bool // SWP instruction support 123 HasHALF bool // Half-word load and store support 124 HasTHUMB bool // ARM Thumb instruction set 125 Has26BIT bool // Address space limited to 26-bits 126 HasFASTMUL bool // 32-bit operand, 64-bit result multiplication support 127 HasFPA bool // Floating point arithmetic support 128 HasVFP bool // Vector floating point support 129 HasEDSP bool // DSP Extensions support 130 HasJAVA bool // Java instruction set 131 HasIWMMXT bool // Intel Wireless MMX technology support 132 HasCRUNCH bool // MaverickCrunch context switching and handling 133 HasTHUMBEE bool // Thumb EE instruction set 134 HasNEON bool // NEON instruction set 135 HasVFPv3 bool // Vector floating point version 3 support 136 HasVFPv3D16 bool // Vector floating point version 3 D8-D15 137 HasTLS bool // Thread local storage support 138 HasVFPv4 bool // Vector floating point version 4 support 139 HasIDIVA bool // Integer divide instruction support in ARM mode 140 HasIDIVT bool // Integer divide instruction support in Thumb mode 141 HasVFPD32 bool // Vector floating point version 3 D15-D31 142 HasLPAE bool // Large Physical Address Extensions 143 HasEVTSTRM bool // Event stream support 144 HasAES bool // AES hardware implementation 145 HasPMULL bool // Polynomial multiplication instruction set 146 HasSHA1 bool // SHA1 hardware implementation 147 HasSHA2 bool // SHA2 hardware implementation 148 HasCRC32 bool // CRC32 hardware implementation 149 _ CacheLinePad 150 } 151 152 // The booleans in Loong64 contain the correspondingly named cpu feature bit. 153 // The struct is padded to avoid false sharing. 154 var Loong64 struct { 155 _ CacheLinePad 156 HasLSX bool // support 128-bit vector extension 157 HasLASX bool // support 256-bit vector extension 158 HasCRC32 bool // support CRC instruction 159 HasLAMCAS bool // support AMCAS[_DB].{B/H/W/D} 160 HasLAM_BH bool // support AM{SWAP/ADD}[_DB].{B/H} instruction 161 HasLLACQ_SCREL bool // support LLACQ.{W/D}, SCREL.{W/D} instruction 162 HasSCQ bool // support SC.Q instruction 163 HasDBAR_HINTS bool // supports finer-grained DBAR hints 164 165 _ CacheLinePad 166 } 167 168 // MIPS64X contains the supported CPU features of the current mips64/mips64le 169 // platforms. If the current platform is not mips64/mips64le or the current 170 // operating system is not Linux then all feature flags are false. 171 var MIPS64X struct { 172 _ CacheLinePad 173 HasMSA bool // MIPS SIMD architecture 174 _ CacheLinePad 175 } 176 177 // PPC64 contains the supported CPU features of the current ppc64/ppc64le platforms. 178 // If the current platform is not ppc64/ppc64le then all feature flags are false. 179 // 180 // For ppc64/ppc64le, it is safe to check only for ISA level starting on ISA v3.00, 181 // since there are no optional categories. There are some exceptions that also 182 // require kernel support to work (DARN, SCV), so there are feature bits for 183 // those as well. The struct is padded to avoid false sharing. 184 var PPC64 struct { 185 _ CacheLinePad 186 HasDARN bool // Hardware random number generator (requires kernel enablement) 187 HasSCV bool // Syscall vectored (requires kernel enablement) 188 IsPOWER8 bool // ISA v2.07 (POWER8) 189 IsPOWER9 bool // ISA v3.00 (POWER9), implies IsPOWER8 190 _ CacheLinePad 191 } 192 193 // S390X contains the supported CPU features of the current IBM Z 194 // (s390x) platform. If the current platform is not IBM Z then all 195 // feature flags are false. 196 // 197 // S390X is padded to avoid false sharing. Further HasVX is only set 198 // if the OS supports vector registers in addition to the STFLE 199 // feature bit being set. 200 var S390X struct { 201 _ CacheLinePad 202 HasZARCH bool // z/Architecture mode is active [mandatory] 203 HasSTFLE bool // store facility list extended 204 HasLDISP bool // long (20-bit) displacements 205 HasEIMM bool // 32-bit immediates 206 HasDFP bool // decimal floating point 207 HasETF3EH bool // ETF-3 enhanced 208 HasMSA bool // message security assist (CPACF) 209 HasAES bool // KM-AES{128,192,256} functions 210 HasAESCBC bool // KMC-AES{128,192,256} functions 211 HasAESCTR bool // KMCTR-AES{128,192,256} functions 212 HasAESGCM bool // KMA-GCM-AES{128,192,256} functions 213 HasGHASH bool // KIMD-GHASH function 214 HasSHA1 bool // K{I,L}MD-SHA-1 functions 215 HasSHA256 bool // K{I,L}MD-SHA-256 functions 216 HasSHA512 bool // K{I,L}MD-SHA-512 functions 217 HasSHA3 bool // K{I,L}MD-SHA3-{224,256,384,512} and K{I,L}MD-SHAKE-{128,256} functions 218 HasVX bool // vector facility 219 HasVXE bool // vector-enhancements facility 1 220 _ CacheLinePad 221 } 222 223 // RISCV64 contains the supported CPU features and performance characteristics for riscv64 224 // platforms. The booleans in RISCV64, with the exception of HasFastMisaligned, indicate 225 // the presence of RISC-V extensions. 226 // 227 // It is safe to assume that all the RV64G extensions are supported and so they are omitted from 228 // this structure. As riscv64 Go programs require at least RV64G, the code that populates 229 // this structure cannot run successfully if some of the RV64G extensions are missing. 230 // The struct is padded to avoid false sharing. 231 var RISCV64 struct { 232 _ CacheLinePad 233 HasFastMisaligned bool // Fast misaligned accesses 234 HasC bool // Compressed instruction-set extension 235 HasV bool // Vector extension compatible with RVV 1.0 236 HasZba bool // Address generation instructions extension 237 HasZbb bool // Basic bit-manipulation extension 238 HasZbs bool // Single-bit instructions extension 239 HasZbc bool // Carryless multiplication extension 240 HasZvbb bool // Vector Basic Bit-manipulation 241 HasZvbc bool // Vector Carryless Multiplication 242 HasZvkb bool // Vector Cryptography Bit-manipulation 243 HasZvkt bool // Vector Data-Independent Execution Latency 244 HasZvkg bool // Vector GCM/GMAC 245 HasZvkn bool // NIST Algorithm Suite (AES/SHA256/SHA512) 246 HasZvknc bool // NIST Algorithm Suite with carryless multiply 247 HasZvkng bool // NIST Algorithm Suite with GCM 248 HasZvks bool // ShangMi Algorithm Suite 249 HasZvksc bool // ShangMi Algorithm Suite with carryless multiplication 250 HasZvksg bool // ShangMi Algorithm Suite with GCM 251 _ CacheLinePad 252 } 253 254 func init() { 255 archInit() 256 initOptions() 257 processOptions() 258 } 259 260 // options contains the cpu debug options that can be used in GODEBUG. 261 // Options are arch dependent and are added by the arch specific initOptions functions. 262 // Features that are mandatory for the specific GOARCH should have the Required field set 263 // (e.g. SSE2 on amd64). 264 var options []option 265 266 // Option names should be lower case. e.g. avx instead of AVX. 267 type option struct { 268 Name string 269 Feature *bool 270 Specified bool // whether feature value was specified in GODEBUG 271 Enable bool // whether feature should be enabled 272 Required bool // whether feature is mandatory and can not be disabled 273 } 274 275 func processOptions() { 276 env := os.Getenv("GODEBUG") 277 field: 278 for env != "" { 279 field := "" 280 i := strings.IndexByte(env, ',') 281 if i < 0 { 282 field, env = env, "" 283 } else { 284 field, env = env[:i], env[i+1:] 285 } 286 if len(field) < 4 || field[:4] != "cpu." { 287 continue 288 } 289 i = strings.IndexByte(field, '=') 290 if i < 0 { 291 print("GODEBUG sys/cpu: no value specified for \"", field, "\"\n") 292 continue 293 } 294 key, value := field[4:i], field[i+1:] // e.g. "SSE2", "on" 295 296 var enable bool 297 switch value { 298 case "on": 299 enable = true 300 case "off": 301 enable = false 302 default: 303 print("GODEBUG sys/cpu: value \"", value, "\" not supported for cpu option \"", key, "\"\n") 304 continue field 305 } 306 307 if key == "all" { 308 for i := range options { 309 options[i].Specified = true 310 options[i].Enable = enable || options[i].Required 311 } 312 continue field 313 } 314 315 for i := range options { 316 if options[i].Name == key { 317 options[i].Specified = true 318 options[i].Enable = enable 319 continue field 320 } 321 } 322 323 print("GODEBUG sys/cpu: unknown cpu feature \"", key, "\"\n") 324 } 325 326 for _, o := range options { 327 if !o.Specified { 328 continue 329 } 330 331 if o.Enable && !*o.Feature { 332 print("GODEBUG sys/cpu: can not enable \"", o.Name, "\", missing CPU support\n") 333 continue 334 } 335 336 if !o.Enable && o.Required { 337 print("GODEBUG sys/cpu: can not disable \"", o.Name, "\", required CPU feature\n") 338 continue 339 } 340 341 *o.Feature = o.Enable 342 } 343 } 344